CN203909782U

CN203909782U - Watchdog circuit control module for state of self-adaption processor

Info

Publication number: CN203909782U
Application number: CN201420317624.1U
Authority: CN
Inventors: 陈庆宇; 吴龙胜; 段青亚
Original assignee: 771 Research Institute of 9th Academy of CASC
Current assignee: 771 Research Institute of 9th Academy of CASC
Priority date: 2014-06-13
Filing date: 2014-06-13
Publication date: 2014-10-29
Anticipated expiration: 2024-06-13

Abstract

The utility model discloses a watchdog circuit control module for the state of a self-adaption processor. According to the attribute that the module executes a task through an autonomous detection processor, when the task of the processor needs a long time and the processor is free of abnormality, hardware automatically generates a dog feeding signal within a set time of a watchdog circuit, dog feeding operation of the processor is not needed, and therefore division of the long-time task by the processor and use of a PCB programmable logic device are avoided. When the task of the processor needs a long time and the processor is abnormal, output of the dog feeding signal automatically generated by the hardware is disabled, and a CPU system is reset when the watchdog circuit does not detect the dog feeding signal within the set time.

Description

A kind of watchdog circuit control module of adaptive processor state

Technical field

The utility model belongs to Design of Digital Integrated Circuit field, relates to a kind of watchdog circuit control module, is specifically related to a kind of watchdog circuit control module of adaptive processor state.

Background technology

Spaceborne computer veneer adopts watchdog circuit (as MAX706) to carry out electrification reset conventionally, monitoring power supply and CPU running status simultaneously, when powering on, the too low or processor of supply voltage is when (as 1.6s) " feeds dog " at the appointed time (the input WDI of watchdog circuit does not change), watchdog circuit resets to processor.

Along with increasing of satellite spatial task, required control program and data volume exponentially increase, and the time overhead of loading procedure or deal with data can increase.After reset finishes, when satellite-borne processor is loaded on the program area in sheet by program in nonvolatile memory from sheet, or while processing not interruptable big data quantity task, all may make processor " feed dog " at the appointed time, watchdog circuit is thought processor operation exception according to this, thereby processor is resetted, cause the generation of exceptional reset.

Current solution of the above problems mainly contains: (1) splits long-time task, operation that middle insertion " fed dog "; (2) between processor and watchdog circuit, insert programmable logic device (PLD) (specifically referring to patent ZL200510041382.3, ZL03123333.3), the in the situation that of needs, processor is configured programming device, realize the control to watchdog circuit with programmable logic device (PLD), thereby extend " feeding dog " time.

The subject matter existing: scheme (1) obviously can reduce system performance, and cannot process can not be split of task; The extra programmable logic device (PLD) of introducing of scheme (2) has reduced the reliability of space application, and increases pcb board area and system complexity, needs software to participate in controlling complicated.

Utility model content

The purpose of this utility model is to overcome the shortcoming of above-mentioned prior art, a kind of watchdog circuit control module of adaptive processor state is provided, this module can realize watchdog circuit control, split, and reliability is high without the long-time task of processor.

For achieving the above object, the watchdog circuit control module of adaptive processor state described in the utility model comprises subtracter, register module, MUX, counter register, first detection module, the first AND circuit, the second AND circuit and second detection module of whether normally working for detection of processor, register module comprises divide ratio register and feeds dog enable register, processor is connected with divide ratio register and hello dog enable register, the high level input end of MUX and low level input end are connected with the output terminal of divide ratio register and the output terminal of subtracter respectively, the control end of MUX is connected with the output terminal of the first AND circuit, the output terminal of MUX is connected with the input end of counter register, input end of the output terminal of counter register and subtracter and the input end of first detection module are connected, another input end of subtracter is connected with high level voltage source, input end of the output terminal of first detection module and the first AND circuit and an input end of the second AND circuit are connected, another input end of the first AND circuit is connected with the output terminal of feeding dog enable register, another input end of the second AND circuit is connected with the output terminal of the second detection module, the output terminal of the second AND circuit is connected with the control end of watchdog circuit, clock signal input terminal on counter register and reset terminal are connected with clock signal output terminal and the reset terminal of processor respectively.

The maximum bit wide of described divide ratio register is 32.

Described processor is connected with divide ratio register and hello dog enable register respectively by bus APBI and bus APB0.

The utlity model has following beneficial effect:

The watchdog circuit control module of adaptive processor state described in the utility model is in to the control procedure of watchdog circuit, when user is during in executive chairman's time task, only need the output signal of feeding dog enable register be adjusted into high level signal by processor, can in the time of counter register underflow, automatically " feed dog ", long-time task without processor splits, also without being extended and fed the dog time by programmable logic device (PLD) in watchdog circuit, reliability is high.There is mistake during processor is being fed dog time, the second detection module output low level signal, and make the second AND circuit produce low level signal, and then described low level signal is input in watchdog circuit, ensure the system reset after watchdog circuit is at the appointed time; Therefore only need judge task attribute by processor, without the schematic diagram of change watchdog circuit, simple and easy to use.

Brief description of the drawings

Fig. 1 is structural representation of the present utility model;

Fig. 2 is the annexation figure of the utility model and watchdog circuit and processor.

Wherein, 101 is that subtracter, 102 is that MUX, 103 is that counter register, 104 is that first detection module, 105 is that register module, 106 is that the first AND circuit, 107 is that the second AND circuit, 108 is the second detection module.

Embodiment

Below in conjunction with accompanying drawing, the utility model is described in further detail:

With reference to figure 1 and Fig. 2, the watchdog circuit control module of adaptive processor state described in the utility model comprises subtracter 101, register module 105, MUX 102, counter register 103, first detection module 104, the first AND circuit 106, the second AND circuit 107 and second detection module 108 of whether normally working for detection of processor, register module 105 comprises divide ratio register and feeds dog enable register, processor is connected with divide ratio register and hello dog enable register, the high level input end of MUX 102 and low level input end are connected with the output terminal of divide ratio register and the output terminal of subtracter 101 respectively, the control end of MUX 102 is connected with the output terminal of the first AND circuit 106, the output terminal of MUX 102 is connected with the input end of counter register 103, input end of the output terminal of counter register 103 and subtracter 101 and the input end of first detection module 104 are connected, another input end of subtracter 101 is connected with high level voltage source, input end of the output terminal of first detection module 104 and the first AND circuit 106 and an input end of the second AND circuit 107 are connected, another input end of the first AND circuit 106 is connected with the output terminal of feeding dog enable register, another input end of the second AND circuit 107 is connected with the output terminal of the second detection module 108, second output terminal of AND circuit 107 and the control end of watchdog circuit are connected, clock signal input terminal on counter register 103 and reset terminal are connected with clock signal output terminal and the reset terminal of processor respectively.

It should be noted that, the maximum bit wide of described divide ratio register is 32; Processor is connected with divide ratio register and hello dog enable register respectively by bus APBI and bus APB0.

The high level input end of MUX 102 exported to divide ratio by divide ratio register, feed the input end that dog enable register enables hardware automatic dog feeding to output to the first AND circuit 106, the input end of MUX 102 is connected with the output terminal of the first AND circuit 106 and the output terminal of subtracter 101 respectively, in the time that the signal of the first AND circuit 106 output terminal outputs is high level signal, 102 divide ratios that divide ratio register is exported of MUX are input in counter register 103, in the time that the signal of the first AND circuit 106 output terminal outputs is low level signal, the signal of subtracter 101 being exported is input in counter register 103, an input end that outputs to first detection module 104 and subtracter 101 after a clock period deposited the signal of input by counter register 103 under clock CK effect, another input end input high level signal of subtracter 101, in the time of first detection module 104 input low level signal, do not process, in the time of the input high level signal of first detection module 104, described high level signal is input to another input end of the first AND circuit 106 and an input end of the second AND circuit 107, the second detection module 108 is input to the operation result of processor another input end of the second AND circuit 107, in the time that processor normally moves, the second detection module 108 is exported high level signal, in the time of processor irregular operating, output low level signal, the signal that the signal that the second AND circuit 107 is exported through first detection module 104 and the second detection module 108 are exported carries out and processing, and result is input to the control end of watchdog circuit.

Watchdog circuit control module based on adaptive processor state of the present utility model, by the watchdog circuit control module at the inner integrated adaptation processor state of processor, first processor enables hardware and " feeds dog " in the time of executive chairman's time task, can avoid the fractionation of processor to long-time task; In the time that watchdog circuit is normal, only need forbid hardware " hello dog " by processor, can improve the performance of processor in the time that plate level is applied, and reduce plate level complicacy, improve reliability when apply in space.

Claims

1. the watchdog circuit control module of an adaptive processor state, it is characterized in that, comprise subtracter (101), register module (105), MUX (102), counter register (103), first detection module (104), the first AND circuit (106), the second AND circuit (107) and second detection module (108) of whether normally working for detection of processor, register module (105) comprises divide ratio register and feeds dog enable register, processor is connected with divide ratio register and hello dog enable register, the high level input end of MUX (102) and low level input end are connected with the output terminal of divide ratio register and the output terminal of subtracter (101) respectively, the control end of MUX (102) is connected with the output terminal of the first AND circuit (106), the output terminal of MUX (102) is connected with the input end of counter register (103), input end of the output terminal of counter register (103) and subtracter (101) and the input end of first detection module (104) are connected, another input end of subtracter (101) is connected with high level voltage source, input end of the output terminal of first detection module (104) and the first AND circuit (106) and an input end of the second AND circuit (107) are connected, another input end of the first AND circuit (106) is connected with the output terminal of feeding dog enable register, another input end of the second AND circuit (107) is connected with the output terminal of the second detection module (108), the output terminal of the second AND circuit (107) is connected with the control end of watchdog circuit, clock signal input terminal on counter register (103) and reset terminal are connected with clock signal output terminal and the reset terminal of processor respectively.

2. the watchdog circuit control module of adaptive processor state according to claim 1, is characterized in that, the maximum bit wide of described divide ratio register is 32.

3. the watchdog circuit control module of adaptive processor state according to claim 1, is characterized in that, described processor is connected with divide ratio register and hello dog enable register respectively by bus APBI and bus APBO.