CN102946185A - Control circuit for improving switching power supply output voltage transient response - Google Patents
Control circuit for improving switching power supply output voltage transient response Download PDFInfo
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Abstract
The invention relates to a switching power supply technology and discloses a control circuit for improving switching power supply output voltage transient response. The control circuit comprises a frequency divider unit, a memory unit and a comparator unit, wherein the frequency divider unit is connected to a drive signal of a switching power supply high-end switch tube and is used for controlling the memory unit through the control signal generated by the drive signal, the memory unit is connected to feedback voltage and is used for collecting and storing the maximum value of later period feedback voltage under the control of the control signal, the comparator unit is connected to the memory unit and is used for comparing the instant value of the feedback voltage with the maximum value, and when the instant value of the feedback voltage is larger than the maximum value, the output signal of the comparator unit is turned over and a switching power supply high-end power tube is turned off. By the aid of the control circuit, good output recovery can be achieved, the recovery time is shortened, the overshoot voltage is reduced and the control circuit can be widely used in switching power supplies and direct current (DC)-direct current (DC) converters.
Description
Technical field
The present invention relates to switch power technology, particularly the DC-DC(DC-to-DC) dc-dc converter output voltage transient response control circuit.
Background technology
The DC-DC dc-dc converter is that the modern power electronics technology field utilizes PWM(pulse width modulation) or the PFM(pulse frequency modulated) etc. the modulation system control switch pipe time ratio of opening and turn-offing, keep the converter of regulated output voltage.At present, control mode commonly used has voltage mode control, Controlled in Current Mode and Based and constant on-time (COT) control etc., and the COT control model is simple in structure with its control loop in recent years, advantages such as system response time is fast and being widely used, but be based on the Switching Power Supply of COT control model when its load jumps to underloading by heavy duty, the transient response of output voltage is very poor.
In the COT control model, when load jumped to underloading by heavy duty, output voltage can be made corresponding adjustment.If circuit is desirable, output voltage is adjusted very soon so, transient response can be finished in a short period of time, but causing exporting the reason that transient response can not adjust very soon is that output voltage overshoot this moment is very large, the output current of adding at this moment is smaller, so the time of output voltage adjustment just becomes very long, the poor performance of Switching Power Supply transient response that Here it is.
Summary of the invention
Technical problem to be solved by this invention, exactly for Switching Power Supply when load jumps to underloading by heavy duty, output voltage can not in time be finished adjustment, the shortcoming that transient response is poor, a kind of control circuit that improves the switch power source output voltage transient response is provided, improves the transient response of Switching Power Supply.
The present invention solve the technical problem, and the technical scheme of employing is, improves the control circuit of switch power source output voltage transient response, it is characterized in that, comprises divider unit, memory cell, comparator unit;
Described divider unit is connected with the driving signal of Switching Power Supply high-end switch pipe, is used for producing control signal according to this driving signal described memory cell is controlled;
Described memory cell is connected with feedback voltage, under the control of described control signal on the maximum of one-period feedback voltage gather and store;
Described comparator unit is connected with memory cell, instantaneous value and the described maximum of feedback voltage compared, and when the instantaneous value of feedback voltage during greater than maximum, described comparator unit output signal upset, the high-end power tube of stopcock power supply.
Concrete, described control signal is a pair of inversion signal.
Further, described divider unit has competition and suppresses mechanism, is used for avoiding occurring race hazard.
Concrete, described divider unit comprises electrical level shift units, D flip-flop, NAND gate and 3 inverters.
Concrete, described memory cell comprises the current mirror of two cascodes, an amplifier unit, a storage capacitance and a transmission gate unit.
Concrete, described comparator unit comprises a comparator and a NAND gate.
The invention has the beneficial effects as follows that the very poor shortcoming of transient response when having overcome the load of traditional C OT control model Switching Power Supply and being underloading by heavily loaded saltus step has realized that good output recovers, and has shortened recovery time and has reduced overshoot voltage.The present invention also has the advantages such as circuit structure is simple, and load response is fast, can improve the transient response process of Switching Power Supply when heavily loaded saltus step is underloading.
Description of drawings
Fig. 1 is prior art Switching Power Supply structural representation;
Fig. 2 is structural representation of the present invention;
Fig. 3 is the divider unit structural representation of embodiment;
Fig. 4 is the memory unit schematic diagram of embodiment;
Fig. 5 is the comparator unit structural representation of embodiment;
Fig. 6 is prior art switch power source output voltage waveform schematic diagram;
Fig. 7 is the switch power source output voltage waveform schematic diagram that adopts control circuit of the present invention.
Correspondence position signal voltage in signal label symbol: SW, HSD, the LSD difference presentation graphs among the figure; HSD is the driving signal of high-end switch pipe HS-FET, and LSD is the driving signal of low-end switch pipe LS-FET; BST is bootstrap voltage mode; Vdd is digital power; VSS is for digitally; Vin is input voltage; Vout is output voltage; VFB is feedback voltage; VFBmax is the maximum of one-period feedback voltage; Ctro1 and Ctro2 are the control signal of divider unit output, are two anti-phase signals; Vsoft is the switch power soft-start signal; LOG is the comparator unit output signal; The bias current that IB provides for switch power supply system.
Embodiment
Below in conjunction with drawings and Examples, describe technical scheme of the present invention in detail.
Switching Power Supply basic structure comprises control unit, Logical processing unit, drive circuit, high-end switch pipe HS-FET, low-end switch pipe LS-FET as shown in Figure 1, and NMOS pipe M1, diode D1 and bootstrap capacitor C
BSTThe boostrap circuit that consists of etc.Drive circuit is followed the output logic that Logical processing unit provides and is moved accordingly, when Logical processing unit so that the high-end switch pipe HS-FET of drive circuit output to drive signal HSD effective, when driving signal LSD is invalid, high-end switch pipe HSFET conducting, low-end switch pipe LS-FET turn-offs, power supply charges to inductance L, and inductive current flows on the output capacitance Cout simultaneously, follows the ripple that inductive current rises so that output voltage V out produces; Otherwise, when Logical processing unit so that the driving signal HSD of drive circuit is invalid, when driving signal LSD is effective, high-end switch pipe HS-FET turn-offs, low-end switch pipe LS-FET opens, and Switching Power Supply is in the afterflow stage, and inductance L is carried out afterflow by the parasitic diode of low-end switch pipe LS-FET, electric current descends gradually, and corresponding output voltage produces follows the downward ripple of inductive current.In this process, the sample circuit that resistance R _ f 1 and Rf2 consist of is also constantly sampled to output voltage, and its output voltage is feedback voltage V FB.NMOS pipe M1, diode D1 and bootstrap capacitor C among the figure
BSTThe boostrap circuit that consists of, its function is when making high-end switch pipe HS-FETHSD unlatching and shutoff, voltage between its grid and the source electrode (being the voltage between HSD and the SW among Fig. 1) can remain in the more rational scope, is unlikely to make the driving voltage of high-end switch pipe HS-FETHSD excessive.
The control circuit structure that the present invention improves the switch power source output voltage transient response comprises divider unit, memory cell, comparator unit as shown in Figure 2.Divider unit is connected with the driving signal HSD of Switching Power Supply high-end switch pipe HS-FET, produces a pair of anti-phase control signal according to driving signal HSD memory cell is controlled.Memory cell is connected with feedback voltage V FB, under control signal control on the maximum VFBmax of one-period feedback voltage gather and store.Comparator unit is connected with memory cell, instantaneous value and this maximum VFBmax of feedback voltage V FB are compared, when the instantaneous value of feedback voltage V FB during greater than this maximum VFBmax, the upset of comparator unit output signal is by Logical processing unit and drive circuit stopcock power supply high-end switch pipe HS-FET.
The effect of divider unit is that the driving signal HSD to high-end switch pipe HS-FET does two frequency divisions, and two fractional frequency signals pass through after the follow-up digital processing as the control signal of memory cell again, carry out the storage operation to VFB.The signal of memory cell stores is that feedback voltage V FB is at the maximum VFBmax of upper one-period, it is the input end signal of device unit as a comparison, meanwhile feedback voltage V FB also is sent to the input of comparator unit, instantaneous value and this maximum VFBmax to feedback voltage V FB compare, because VFB is periodically variable with driving signal HSD, and each cycle of the storage signal of feedback voltage V FB (VFBmax) replaces once, and what that is to say the comparator unit comparison is the situation of change of VFB signal between adjacent two cycles.During normal operation, because the VFB between the adjacent work period is consistent, so, comparator unit just can not overturn, only have when output loading is underloading by heavily loaded saltus step, because overshoot can appear in output voltage, overshoot also can occur in VFB so, at this moment, because VFB has reached the comparison upper limit of comparator unit, so, the upset of comparator unit output level, this level turn-offs high-end switch pipe HS-FET through Logical processing unit and the drive circuit of rear class.Control circuit of the present invention is exactly to shorten output recovery time and overshoot voltage by such mode, reaches the purpose of improving the output transient response.
Embodiment
Fig. 3, Fig. 4 and Fig. 5 show respectively the structure of this routine divider unit, memory cell and comparator unit.
Divider unit shown in Figure 3 comprises electrical level shift units, D flip-flop, the first NAND gate NAND1 and the first inverter INV1, the second inverter INV2 and the 3rd inverter INV3, and wherein D flip-flop is connected into frequency divider (two-divider).The driving signal HSD of an input termination switch power supply high-end switch pipe HS-FET of electrical level shift units, other four inputs meet respectively BST, SW, Vdd and VSS.Its effect is that scope is displaced to digital power Vdd and digitally on the VSS at the square-wave signal between SW and the BST (drive signal HSD), drive signal HSD and just become the square-wave signal of scope between VSS and Vdd after shift unit, this signal is as the clock signal of frequency divider and the input signal of the first inverter.The output of electrical level shift units connects the clock signal terminal CLK of frequency divider and the input of the first inverter, and the RD of frequency divider is its clear terminal, starts with system to be associated, and when system started, RD carried out initialization to frequency divider.The input D of frequency divider links to each other with output QN, and Vdd and VSS provide VDD-to-VSS for frequency divider.The output of the first inverter INV1 connects the input of the second inverter INV2 and the end of capacitor C delay, the other end ground connection of capacitor C delay.Signal after the displacement produces a very little time-delay through the first inverter INV1 and capacitor C delay, and the signal after the time-delay carries out NAND operation through being input to the first NAND gate NAND1 with the output Q of frequency divider behind the second inverter INV2 again.The purpose of doing like this is race hazard to occur for fear of signal, because HSD has a rising edge in practice after being shifted, so this signal carries out NAND operation with the output of frequency divider after by the processing of the first inverter INV1, capacitor C delay and the second inverter INV2 again, so just avoided two signals all at rising edge may, thereby avoided race hazard, guaranteed the circuit normal operation, Here it is, and competition of the present invention suppresses mechanism.The output of the first NAND gate NAND1 is control signal Ctro1, and this signal is exported control signal Ctro2 after the 3rd inverter INV3 is anti-phase.
Two anti-phase control signal Ctro1 and Ctro2 are used for the course of work of control storage unit.This routine memory cell is by the current mirror of two cascodes, amplifier unit A0, a memory cell C
REF(in fact being exactly an electric capacity) and a transmission gate unit form.NMOS current mirror (current mirror that is made of the NMOS pipe) is used for processing external bias electric current I B, provides biasing for amplifier A0 behind the electric current of PMOS current mirror (current mirror that the PMOS pipe consists of) mirror image NMOS current mirror.Amplifier A0 is connected into the degenerative form of unit gain, such structure so that the voltage of end of oppisite phase and output be clamped on the VFB, when certain cycle H SD signal when being high, control signal Ctro1 and Ctro2 are respectively low level and high level, the transmission gate unit is opened like this, and the maximum VFBmax of VFB is stored in memory cell C within this cycle
REFOn, C here
REFVery little, the purpose of doing like this is in order to guarantee sampling precision, because the maximum VFBmax of feedback voltage V FB in the last cycle that the reverse input end of comparator unit is sampling to be obtained, consider simultaneously the offset voltage Vos that comparator unit is introduced, so just be provided with a relatively upper limit to VFB, its value is: VFBmax+Vos.This upper limit is in real time variable, and control circuit just can be realized the function of Real-Time Monitoring output voltage ripple like this.
This routine memory cell circuits structure comprises 5 NMOS pipes as shown in Figure 4: MN1~5,5 a PMOS pipe: MP1~5, one a capacitor C REF and an amplifier A0.Wherein MN1~4 consist of the NMOS current mirror of cascodes, and MP1~4 consist of the PMOS current mirror of cascodes, and MP5 and MN5 consist of the transmission gate unit.Among Fig. 4, grid and the drain electrode of the one NMOS pipe MN1 meet electric current I B, the grid of the 3rd NMOS pipe MN3 and drain electrode connect the source electrode of NMOS pipe MN1, the grid of the 3rd NMOS pipe MN3 connects the grid of the 4th NMOS pipe, the source ground VSS of the 3rd NMOS pipe MN3 and the 4th NMOS pipe MN4, the drain electrode of the 4th NMOS pipe MN4 connects the source electrode of the 2nd NMOS pipe MN2, the grid of the 2nd NMOS pipe MN2 connects the grid of NMOS pipe MN1, the drain electrode of the 2nd NMOS pipe MN2 connects grid and the drain electrode of the 3rd PMOS pipe MP3, the source electrode of the 3rd PMOS pipe MP3 connects grid and the drain electrode of PMOS pipe MP1, the source electrode of the one PMOS pipe MP1 and the 2nd PMOS pipe MP2 meets power supply Vdd, the grid of the 2nd PMOS pipe MP2 connects the grid of PMOS pipe MP1, the drain electrode of the 2nd PMOS pipe MP2 connects the source electrode of the 4th PMOS pipe MP4, the source electrode of the 4th PMOS pipe MP4 connects the current offset point of amplifier A0, the grid of the 4th PMOS pipe MP4 connects the grid of the 3rd PMOS pipe MP3, the homophase termination feedback voltage V FB of amplifier A0, end of oppisite phase links to each other with the output of amplifier, and be connected on the source electrode of the drain electrode of the 5th NMOS pipe MN5 and the 5th PMOS pipe MP5, the drain electrode of the source electrode of the 5th NMOS pipe MN5 and the 5th PMOS pipe MP5 is connected to VFBmax and capacitor C
REFOne end, capacitor C
REFOther end ground connection.
This routine comparator unit structure comprises comparator C OMP and the second NAND gate NAND2 as shown in Figure 5.The homophase termination feedback voltage V FB of comparator C OMP, anti-phase termination VFBmax, output connects the input of the second NAND gate NAND2, the soft-start signal Vsoft of another input termination switch power supply of the second NAND gate NAND2, and the output signal of the second NAND gate is LOG.Like this, the soft-start signal Vsoft of the output signal of comparator and Switching Power Supply carries out just can outputing to Logical processing unit after the NAND operation.When certain cycle output jumps to underloading by heavy duty, output voltage just has a larger overshoot so, at this moment VFB can trigger the comparison higher limit VFBmax+Vos of setting, thereby the output generation upset that makes comparator becomes high level and (it is worthy of note, the Vsoft here is a signal relevant with the system soft start, when system's soft start, its value is for low level, is used for the initialization comparator unit, when soft start is finished, its value becomes high level, has so just decontroled comparator, at this moment, the function of the second NAND gate NAND2 of rear end just is equivalent to an inverter), corresponding, signal LOG upset is low level, then this signal function is in drive circuit, high-end switch pipe HS-FET is closed, thereby reaching the improvement system is overshoot in the underloading situation in heavily loaded saltus step, raises the efficiency, and reduces the generation of electromagnetic interference.
Fig. 6 and Fig. 7 show the prior art Switching Power Supply and have adopted the Switching Power Supply of control circuit of the present invention, the waveform of output current Iout and output voltage waveforms Vout when output is underloading by heavily loaded saltus step.
Contrast by Fig. 6 and Fig. 7 as seen, the prior art Switching Power Supply is when output loading generation saltus step, and overshoot voltage is larger, is Δ V, and be subjected to the little impact of restoring current, so that output voltage is long recovery time, be Δ t, recovery process is slower, and adopted the Switching Power Supply of control circuit of the present invention owing in time turn-offed high-end switch pipe HS-FET, so can make output when the load saltus step, overshoot value is reduced to Δ V1, and shortens to Δ t1 recovery time.In addition, it is evident that, because output voltage generation overshoot, ON time Ton increases so, the peak value of output voltage V out also increases to some extent, this is because Ton is directly proportional with Vout, and the overshoot of Vout is so that Ton has a small variation, and is final so that all to some extent increases of the peak value of the cycle after the saltus step and output voltage.
To sum up, control circuit that the present invention improves the kind switch source output of switch electricity transient response has overcome traditional C OT control circuit very poor transient response when heavily loaded saltus step is underloading, realized that good output recovers, and has shortened recovery time and has reduced overshoot voltage.
Those of ordinary skill in the art will appreciate that the embodiments described herein is in order to help reader understanding's principle of the present invention, should to be understood to that protection scope of the present invention is not limited to such special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combinations that do not break away from essence of the present invention according to these technology enlightenments disclosed by the invention, and these distortion and combination are still in protection scope of the present invention.Particularly electrical level shift units and frequency divider can have a variety of implementation methods, and certainly, the current-mirror structure in the memory cell also can adopt other forms, and the conventional substitute mode that these those skilled in the art adopt is all in protection scope of the present invention.
Claims (6)
1. improve the control circuit of switch power source output voltage transient response, it is characterized in that, comprise divider unit, memory cell, comparator unit;
Described divider unit is connected with the driving signal of Switching Power Supply high-end switch pipe, is used for producing control signal according to this driving signal described memory cell is controlled;
Described memory cell is connected with feedback voltage, under the control of described control signal on the maximum of one-period feedback voltage gather and store;
Described comparator unit is connected with memory cell, instantaneous value and the described maximum of feedback voltage compared, and when the instantaneous value of feedback voltage during greater than maximum, described comparator unit output signal upset, the high-end power tube of stopcock power supply.
2. the control circuit that improves the switch power source output voltage transient response according to claim 1 is characterized in that, described control signal is a pair of inversion signal.
3. the control circuit that improves the switch power source output voltage transient response according to claim 1 is characterized in that, described divider unit has competition and suppresses mechanism, is used for avoiding occurring race hazard.
4. the control circuit that improves the switch power source output voltage transient response according to claim 3 is characterized in that, described divider unit comprises electrical level shift units, D flip-flop, NAND gate and 3 inverters.
5. the control circuit that improves the switch power source output voltage transient response according to claim 1 is characterized in that, described memory cell comprises the current mirror of two cascodes, an amplifier unit, a storage capacitance and a transmission gate unit.
6. the control circuit that improves the switch power source output voltage transient response according to claim 1 is characterized in that, described comparator unit comprises a comparator and a NAND gate.
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CN103904875A (en) * | 2014-03-24 | 2014-07-02 | 合肥工业大学 | Digital soft start circuit in switching power source |
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