CN105207668A - Overcurrent counter for soft start protection - Google Patents
Overcurrent counter for soft start protection Download PDFInfo
- Publication number
- CN105207668A CN105207668A CN201510575170.7A CN201510575170A CN105207668A CN 105207668 A CN105207668 A CN 105207668A CN 201510575170 A CN201510575170 A CN 201510575170A CN 105207668 A CN105207668 A CN 105207668A
- Authority
- CN
- China
- Prior art keywords
- output
- signal
- connects
- input
- termination
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Logic Circuits (AREA)
Abstract
The invention belongs to the technical field of power supplies, and relates to an overcurrent counter for soft start protection. The overcurrent counter for soft start protection mainly comprises a clock frequency division module, a clock selection module, a timing module, a first logic processing module and a second logic processing module; the input end of the clock frequency division module is connected with an external clock signal, and the output end of the clock frequency division module is connected with the clock selection module; the input end of the clock selection module is connected with an external clock selection signal; the input end of the timing module is connected with an external overcurrent signal and an external soft start signal; the input end of the first logic processing module is connected with the external overcurrent signal, and the output end of the first logic processing module is connected with an overcurrent state protection signal; the input end of the second logic processing module is connected with the external soft start signal, and the output end of the second logic processing module is connected with a soft start monitor signal. The overcurrent counter for soft start protection has the advantages that the existing necessary modules are effectively utilized for the optimal design of system control; meanwhile, on the condition that a narrow-band pulse signal filtering circuit is additionally arranged, the anti-noise capacity of the system is improved, and false triggering caused by noise is effectively filtered out.
Description
Technical field
The invention belongs to power technique fields, relate to a kind of mistake flow counter for soft start protection.
Background technology
In technical field of power management, system-level control is the guarantee of power-supply system reliability.The carrying out of soft start is that the phenomenons such as the surge in order to prevent power up cause damage to system, and this process is the tie that power-supply system starts to normal work.It is the important component part ensureing that whole system works without any confusion to the protection of abnormality; crossing flow accounting is the common protection form of power-supply management system to this abnormality of overcurrent, and the mode of counting not only efficiently avoid because some interference causes the of short duration exception of system but also ensured the response of system to this state in a range of tolerable variance.
The system of the counting protection form of over-current state realizes as shown in Figure 1, and it comprises counting module and logical process two parts.Segment count is by clock signal (CLK) and over-current state information signal (OC_inf) two signals as input, and it exports and over-current state information signal (OC_inf) carries out logical process and obtains over-current state and output signal (OC_out).System is the response to overcurrent abnormality to the response that over-current state outputs signal.
Soft start-up process is the process that power-supply system output voltage is slowly lifted to stable state; it has great significance for the reliable of system and steady operation; in very many power-supply systems, relevant state one monitoring protected and carry out it is not carried out to soft start-up process at present; and the exception of soft start directly will cause the paralysis of whole system; simultaneously because most of protecting control modules of system in soft start-up process do not enter operating state, the reliability of system is by discount.
Summary of the invention
To be solved by this invention, be exactly for the problems referred to above, propose a kind of mistake flow counter for soft start protection.
For achieving the above object, the present invention adopts following technical scheme:
For a mistake flow counter for soft start protection, comprise clock frequency division module, clock selection module, timing module, the first logic processing module and the second logic processing module; The input termination external timing signal of described clock frequency division module, the first input end of its first output termination clock selection module, the second input of its second output termination clock selection module; Signal selected by 3rd input termination external clock of described clock selection module, and it exports the first input end of termination timing module; The outside over-current signal of second input termination of described timing module, the outside soft-start signal of its 3rd input termination, it exports the first input end of termination first logic processing module and the first input end of the second logic processing module; The outside over-current signal of second input termination of described first logic processing module, its output is over-current state guard signal; The outside soft-start signal of second input termination of the second logic processing module, its output is soft start monitor signal;
Described clock frequency division module receives external timing signal, produces length two-way clock signal, selects a road to be input to timing module under the effect of outside clock selection signal;
Described timing module is under the control of clock frequency division module, timing carried out to outside over-current signal and exports the over-current signal after timing to the first logic processing module, exporting the soft-start signal after timing after timing is carried out to outside soft-start signal to the second logic processing module;
Described first logic processing module is used for the over-current signal after outside over-current signal and timing being compared process and obtains finally crossing stream information; Described second logic processing module is used for the soft-start signal after outside soft-start signal and timing being compared process and obtains final soft start information.
Further, described clock frequency division module is made up of the first d type flip flop, the second d type flip flop, 3d flip-flop, four d flip-flop, the 5th d type flip flop, the 6th d type flip flop; The clock signal termination external timing signal of the first d type flip flop, its reversed-phase output connects its D input; The in-phase input end of clock signal termination first d type flip flop of the second d type flip flop, its reversed-phase output connects its D input; The in-phase input end of clock signal termination second d type flip flop of 3d flip-flop, its reversed-phase output connects its D input; The in-phase input end of the clock signal termination 3d flip-flop of four d flip-flop, its reversed-phase output connects its D input; The in-phase input end of the clock signal termination four d flip-flop of the 5th d type flip flop, its reversed-phase output connects its D input; The in-phase input end of clock signal termination the 5th d type flip flop of the 6th d type flip flop, its reversed-phase output connects its D input; The outside enable signal of clearing termination of all d type flip flops; The in-phase output end of the second d type flip flop is the first output of clock frequency division module, output short-range clock signal; The homophase of the 6th d type flip flop exports the second output for clock frequency division module, exports long clock signal.
Further, described clock selection module is by the first PMOS MP1, the second PMOS MP2, the first NMOS tube, and N1, the second NMOS tube MN2 and the first inverter INV1 are formed; The grid of the first NMOS tube MN1 connects external clock and selects signal, and its source electrode connects the second output of clock frequency division module, and it misses the drain electrode meeting the first PMOS MP1; The grid of the first PMOS MP1 connects the output of the first inverter INV1, and its source electrode connects the second output of clock frequency division module; Signal selected by the input termination external clock of the first inverter INV1; The grid of the second NMOS tube MN2 connects the output of the first inverter INV1, and its source electrode connects the first output of clock frequency division module, and it misses the drain electrode meeting the second PMOS MP2; The grid of the second PMOS MP2 connects external clock and selects signal, and its source electrode connects the first output of clock frequency division module; First PMOS MP1 drain electrode drains with the second PMOS MP2 and is connected, and is the output of clock selection module.
Further, described timing module is made up of the 7th d type flip flop, the 8th d type flip flop, the 9th d type flip flop, the tenth d type flip flop, the 11 d type flip flop, the tenth 2-D trigger, the tenth 3d flip-flop, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 3rd NMOS tube N3, the 4th NMOS tube N4, the 5th NMOS tube MN5, the second inverter INV2, the 3rd inverter INV3, the 4th inverter INV4, the first resistance R1 and the first Schmidt trigger;
The grid of the 3rd NMOS tube MN3 connects outside soft-start signal, and its source electrode connects the output of clock selection module, and it misses the drain electrode meeting the 3rd PMOS MP3; The grid of the 3rd PMOS MP3 connects the output of the second inverter INV2, and its source electrode connects the output of clock selection module; The outside soft-start signal of input termination of the second inverter INV2; The grid of the 4th NMOS tube MN4 connects the output of the second inverter INV2, and its source electrode connects the output of clock selection module, and its drain electrode connects the drain electrode of the 4th PMOS MP4; The grid of the 4th PMOS MP4 connects outside soft-start signal, and its source electrode connects the output of clock selection module; The tie point that 3rd PMOS MP3 drain electrode and the 4th PMOS MP4 drain connects the input of the 3rd inverter INV3;
The source electrode of the 5th PMOS MP5 connects power supply, and its grid connects the output of the 3rd inverter INV3, and its drain electrode is by connecing the drain electrode of the 5th NMOS tube MN5 and the input of Schmidt trigger after the first resistance R1; The grid of the 5th NMOS tube N5 connects the output of the 3rd inverter INV3, its source ground; The input of output termination the 4th inverter INV4 of Schmidt trigger; The D input of output termination the tenth 3d flip-flop of the 4th inverter INV4;
The output of the clock signal termination clock selection module of the 7th d type flip flop, its reversed-phase output connects its D input; The in-phase input end of clock signal termination the 7th d type flip flop of the 8th d type flip flop, its reversed-phase output connects its D input; The in-phase input end of clock signal termination the 8th d type flip flop of the 9th d type flip flop, its reversed-phase output connects its D input; The in-phase input end of clock signal termination the 9th d type flip flop of the tenth d type flip flop, its reversed-phase output connects its D input; The in-phase input end of clock signal termination the tenth d type flip flop of the 11 d type flip flop, its reversed-phase output connects its D input; The in-phase input end of clock signal termination the 11 d type flip flop of the tenth 2-D trigger, its reversed-phase output connects its D input, and its in-phase output end connects the clock signal terminal of the tenth 3d flip-flop; The outside enable signal of clearing termination of all d type flip flops; The in-phase output end of the tenth 3d flip-flop is the output of clock count module.
Further, described second logic processing module is made up of the 5th inverter INV5, hex inverter INV6, the 6th PMOS MP6, the 6th NMOS tube MN6, the second Schmidt trigger, the second resistance R2 and two input nand gates; The outside soft-start signal of input termination of the 5th inverter INV5; The grid of the 6th PMOS MP6 connects the output of the 5th inverter INV5, and its source electrode connects power supply, and its drain electrode is by connecing the drain electrode of the 6th NMOS tube MN6 and the output of the second Schmidt trigger after the second resistance R2; The grid of the 6th NMOS tube MN6 connects the output of the 5th inverter INV5, its source ground; The input of the output termination hex inverter INV6 of the second Schmidt trigger; The first input end of output termination two input nand gate of hex inverter INV6; The output of the second input termination timing module of two input nand gates, its output is the output of the second logic module.
Beneficial effect of the present invention is, utilize requisite overcurrent protection module in power-supply system to carry out multiplexing this structure that makes and monitor soft start-up process simultaneously and protect, the module efficiently utilizing existing necessity carries out the optimal design of Systematical control.Simultaneously under the adding of narrow-band ping filtering circuit, improve the anti-noise ability of system, the false triggering that causes due to noise of filtering effectively.The multiplexing original system module raises reliability of system on the basis that need not increase module newly, under the requirement of high reliability, less chip area, this invention can use and obtains expected effect well.
Accompanying drawing explanation
Fig. 1 is overcurrent protection module schematic diagram common in existing power supply system;
Fig. 2 is the soft start protecting control configuration diagram of multiplexing overcurrent protection module of the present invention;
Fig. 3 is clock frequency division module structural representation;
Fig. 4 is clock selection module structural representation;
Fig. 5 is timing module schematic diagram;
Fig. 6 is logic processing module.
Embodiment
Below in conjunction with accompanying drawing, describe technical scheme of the present invention in detail:
For overcurrent protection counting module necessary in conventional power source system and the demand to soft start-up process monitoring and protection; the present invention proposes a kind of flow accounting multiplexing structure being excessively applicable to soft start-up process monitoring and protection, and design is optimized to the false triggering effect produced due to reasons such as noises in system.Physical circuit framework as shown in Figure 2, comprises clock frequency division module, clock selection module, timing module, logic processing module four parts.Length (CLK_L) short (CLK_S) the two-way clock signal wherein produced by clock frequency division module is input to clock selection module for its choice for use under different phase; Select above-mentioned length two-way clock Zhong mono-tunnel to output to timing module by clock selection signal (CLK_Select) in different phase in clock selection module and do clock use; The clocking information of different phase is processed in timing module, what be respectively normal cycle crosses stream information (OC_inf) or the soft start information (SS_Flag) of soft start-up process, finally exports the state information (Counter_out) after its timing; In logic processing module, finally process the state information after soft start state information and above-mentioned timing, finally export soft start status signal (SS_State) for system-level control logic process.
As shown in Figure 3, described clock frequency division module is made up of the first d type flip flop, the second d type flip flop, 3d flip-flop, four d flip-flop, the 5th d type flip flop, the 6th d type flip flop; The clock signal termination external timing signal of the first d type flip flop, its reversed-phase output connects its D input; The in-phase input end of clock signal termination first d type flip flop of the second d type flip flop, its reversed-phase output connects its D input; The in-phase input end of clock signal termination second d type flip flop of 3d flip-flop, its reversed-phase output connects its D input; The in-phase input end of the clock signal termination 3d flip-flop of four d flip-flop, its reversed-phase output connects its D input; The in-phase input end of the clock signal termination four d flip-flop of the 5th d type flip flop, its reversed-phase output connects its D input; The in-phase input end of clock signal termination the 5th d type flip flop of the 6th d type flip flop, its reversed-phase output connects its D input; The outside enable signal of clearing termination of all d type flip flops; The in-phase output end of the second d type flip flop is the first output of clock frequency division module, output short-range clock signal; The homophase of the 6th d type flip flop exports the second output for clock frequency division module, exports long clock signal.
As shown in Figure 4, described clock selection module is by the first PMOS MP1, the second PMOS MP2, the first NMOS tube, and N1, the second NMOS tube MN2 and the first inverter INV1 are formed; The grid of the first NMOS tube MN1 connects external clock and selects signal, and its source electrode connects the second output of clock frequency division module, and it misses the drain electrode meeting the first PMOS MP1; The grid of the first PMOS MP1 connects the output of the first inverter INV1, and its source electrode connects the second output of clock frequency division module; Signal selected by the input termination external clock of the first inverter INV1; The grid of the second NMOS tube MN2 connects the output of the first inverter INV1, and its source electrode connects the first output of clock frequency division module, and it misses the drain electrode meeting the second PMOS MP2; The grid of the second PMOS MP2 connects external clock and selects signal, and its source electrode connects the first output of clock frequency division module; First PMOS MP1 drain electrode drains with the second PMOS MP2 and is connected, and is the output of clock selection module.
As shown in Figure 5, described timing module is made up of the 7th d type flip flop, the 8th d type flip flop, the 9th d type flip flop, the tenth d type flip flop, the 11 d type flip flop, the tenth 2-D trigger, the tenth 3d flip-flop, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 3rd NMOS tube N3, the 4th NMOS tube N4, the 5th NMOS tube MN5, the second inverter INV2, the 3rd inverter INV3, the 4th inverter INV4, the first resistance R1 and the first Schmidt trigger;
The grid of the 3rd NMOS tube MN3 connects outside soft-start signal, and its source electrode connects the output of clock selection module, and it misses the drain electrode meeting the 3rd PMOS MP3; The grid of the 3rd PMOS MP3 connects the output of the second inverter INV2, and its source electrode connects the output of clock selection module; The outside soft-start signal of input termination of the second inverter INV2; The grid of the 4th NMOS tube MN4 connects the output of the second inverter INV2, and its source electrode connects the output of clock selection module, and its drain electrode connects the drain electrode of the 4th PMOS MP4; The grid of the 4th PMOS MP4 connects outside soft-start signal, and its source electrode connects the output of clock selection module; The tie point that 3rd PMOS MP3 drain electrode and the 4th PMOS MP4 drain connects the input of the 3rd inverter INV3;
The source electrode of the 5th PMOS MP5 connects power supply, and its grid connects the output of the 3rd inverter INV3, and its drain electrode is by connecing the drain electrode of the 5th NMOS tube MN5 and the input of Schmidt trigger after the first resistance R1; The grid of the 5th NMOS tube N5 connects the output of the 3rd inverter INV3, its source ground; The input of output termination the 4th inverter INV4 of Schmidt trigger; The D input of output termination the tenth 3d flip-flop of the 4th inverter INV4;
The output of the clock signal termination clock selection module of the 7th d type flip flop, its reversed-phase output connects its D input; The in-phase input end of clock signal termination the 7th d type flip flop of the 8th d type flip flop, its reversed-phase output connects its D input; The in-phase input end of clock signal termination the 8th d type flip flop of the 9th d type flip flop, its reversed-phase output connects its D input; The in-phase input end of clock signal termination the 9th d type flip flop of the tenth d type flip flop, its reversed-phase output connects its D input; The in-phase input end of clock signal termination the tenth d type flip flop of the 11 d type flip flop, its reversed-phase output connects its D input; The in-phase input end of clock signal termination the 11 d type flip flop of the tenth 2-D trigger, its reversed-phase output connects its D input, and its in-phase output end connects the clock signal terminal of the tenth 3d flip-flop; The outside enable signal of clearing termination of all d type flip flops; The in-phase output end of the tenth 3d flip-flop is the output of clock count module.
As shown in Figure 6, described second logic processing module is made up of the 5th inverter INV5, hex inverter INV6, the 6th PMOS MP6, the 6th NMOS tube MN6, the second Schmidt trigger, the second resistance R2 and two input nand gates; The outside soft-start signal of input termination of the 5th inverter INV5; The grid of the 6th PMOS MP6 connects the output of the 5th inverter INV5, and its source electrode connects power supply, and its drain electrode is by connecing the drain electrode of the 6th NMOS tube MN6 and the output of the second Schmidt trigger after the second resistance R2; The grid of the 6th NMOS tube MN6 connects the output of the 5th inverter INV5, its source ground; The input of the output termination hex inverter INV6 of the second Schmidt trigger; The first input end of output termination two input nand gate of hex inverter INV6; The output of the second input termination timing module of two input nand gates, its output is the output of the second logic module.
First logic processing module and the second logic processing module can adopt same structure.
Operation principle of the present invention is:
The present invention is mainly by carrying out multiplexing to clock signal, to the flow accounting excessively of power-supply management system, its clock is produced by the output of Current Limits comparator and obtains, conventional set Current Limits is not generally reached for soft start stage inductive current, then for this multiplexing structure, first the problem solving the generation of soft start phase clock is needed, the scheme that the present invention proposes is: arrange a lower Current Limits in the soft start stage, soft start information is utilized to carry out selecting Current Limits completing the generation of clock signal, reusable-design clock generation circuit dexterously.
In the middle of clock frequency division module; the length setting long clock (CLK_L) is needed according to soft-start time; guarantee can monitor soft start state effectively again can not false triggering guard mode, then timing duration (TCounter) and soft-start time (TSS) relation that will meet is as follows:
T
SS+Δt≥T
Counter≥T
SS
Wherein Δ t is the allowance time, and this allowance time ensures that system can start and concrete monitoring to soft-start time effectively.
For concrete case study on implementation, the period-luminosity relation obtaining the output signal of length two-way clock and Current Limits comparator is as follows:
T
CLK_S＝4T
CLK
T
CLK_L＝64T
CLK
The two-way clock signal produced outputs to timing module via clock selection module, in the middle of clock selection module, clock selection signal (CLK_Select) adopts soft-start signal (SS_Flag) to complete in present case, this signal has two different states in soft start stage and normal cycle, in the present invention, soft start stage SS_Flag=H, selects long clock signal to carry out timing.
After clock is input to timing module, exported through timing, timing time is in the present invention:
T
Counter＝64T
CLK_L
Namely have:
T
Counter＝64T
CLK_L＝4096T
CLK
This duration is set by soft start concrete institute elapsed time, can set the d type flip flop trimmed ensure can effectively monitor and protect completing smoothly of soft start in its range of application according to application in timing.
Burst pulse filtering circuit in the present invention improves the fault-tolerance of this control framework effectively, and MP5, MN5, R1 and SMIT1 form burst pulse filtering circuit; This circuit can the narrow pulse signal that produces due to interference signal of filtering, its principle is as follows: have the inverter structure of resistance and Schmidt trigger to form by string in this circuit, because its duration is shorter for burst pulse, the upset that next stage exports cannot be completed in the RC time constant that circuit structure determines, and then by the hysteresis effect of Schmidt trigger, this burst pulse shows as by filtration result for next stage structure, effectively improves the serious forgiveness of the false triggering caused due to noise.
In the middle of logic processing module; the object information of timing and soft start state information are carried out and non-logical operation; its flag information of the soft start stage (SS_Flag) remains high level; and its upset is low level at the end of soft start; then have: if do not complete within the timing time of soft start set by this structure; the soft start protection information (SS_state) then now exported is then invalid low level; this information that will be prompt system soft start exception, system will respond this.Can draw thus: this structure is multiplex system existing structure effectively, add some modules and complete difunctional.
Claims (5)
1., for a mistake flow counter for soft start protection, comprise clock frequency division module, clock selection module, timing module, the first logic processing module and the second logic processing module; The input termination external timing signal of described clock frequency division module, the first input end of its first output termination clock selection module, the second input of its second output termination clock selection module; Signal selected by 3rd input termination external clock of described clock selection module, and it exports the first input end of termination timing module; The outside over-current signal of second input termination of described timing module, the outside soft-start signal of its 3rd input termination, it exports the first input end of termination first logic processing module and the first input end of the second logic processing module; The outside over-current signal of second input termination of described first logic processing module, its output is over-current state guard signal; The outside soft-start signal of second input termination of the second logic processing module, its output is soft start monitor signal;
Described clock frequency division module receives external timing signal, produces length two-way clock signal, selects a road to be input to timing module under the effect of outside clock selection signal;
Described timing module is under the control of clock frequency division module, timing carried out to outside over-current signal and exports the over-current signal after timing to the first logic processing module, exporting the soft-start signal after timing after timing is carried out to outside soft-start signal to the second logic processing module;
Described first logic processing module is used for the over-current signal after outside over-current signal and timing being compared process and obtains finally crossing stream information; Described second logic processing module is used for the soft-start signal after outside soft-start signal and timing being compared process and obtains final soft start information.
2. according to front a kind of mistake flow counter for soft start protection according to claim 1, it is characterized in that, described clock frequency division module is made up of the first d type flip flop, the second d type flip flop, 3d flip-flop, four d flip-flop, the 5th d type flip flop, the 6th d type flip flop; The clock signal termination external timing signal of the first d type flip flop, its reversed-phase output connects its D input; The in-phase input end of clock signal termination first d type flip flop of the second d type flip flop, its reversed-phase output connects its D input; The in-phase input end of clock signal termination second d type flip flop of 3d flip-flop, its reversed-phase output connects its D input; The in-phase input end of the clock signal termination 3d flip-flop of four d flip-flop, its reversed-phase output connects its D input; The in-phase input end of the clock signal termination four d flip-flop of the 5th d type flip flop, its reversed-phase output connects its D input; The in-phase input end of clock signal termination the 5th d type flip flop of the 6th d type flip flop, its reversed-phase output connects its D input; The outside enable signal of clearing termination of all d type flip flops; The in-phase output end of the second d type flip flop is the first output of clock frequency division module, output short-range clock signal; The homophase of the 6th d type flip flop exports the second output for clock frequency division module, exports long clock signal.
3. according to front a kind of mistake flow counter for soft start protection according to claim 2, it is characterized in that, described clock selection module is by the first PMOS MP1, the second PMOS MP2, the first NMOS tube, and N1, the second NMOS tube MN2 and the first inverter INV1 are formed; The grid of the first NMOS tube MN1 connects external clock and selects signal, and its source electrode connects the second output of clock frequency division module, and it misses the drain electrode meeting the first PMOS MP1; The grid of the first PMOS MP1 connects the output of the first inverter INV1, and its source electrode connects the second output of clock frequency division module; Signal selected by the input termination external clock of the first inverter INV1; The grid of the second NMOS tube MN2 connects the output of the first inverter INV1, and its source electrode connects the first output of clock frequency division module, and it misses the drain electrode meeting the second PMOS MP2; The grid of the second PMOS MP2 connects external clock and selects signal, and its source electrode connects the first output of clock frequency division module; First PMOS MP1 drain electrode drains with the second PMOS MP2 and is connected, and is the output of clock selection module.
4. a kind of mistake flow counter for soft start protection according to claim 3, it is characterized in that, described timing module is made up of the 7th d type flip flop, the 8th d type flip flop, the 9th d type flip flop, the tenth d type flip flop, the 11 d type flip flop, the tenth 2-D trigger, the tenth 3d flip-flop, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 3rd NMOS tube N3, the 4th NMOS tube N4, the 5th NMOS tube MN5, the second inverter INV2, the 3rd inverter INV3, the 4th inverter INV4, the first resistance R1 and the first Schmidt trigger;
The grid of the 3rd NMOS tube MN3 connects outside soft-start signal, and its source electrode connects the output of clock selection module, and it misses the drain electrode meeting the 3rd PMOS MP3; The grid of the 3rd PMOS MP3 connects the output of the second inverter INV2, and its source electrode connects the output of clock selection module; The outside soft-start signal of input termination of the second inverter INV2; The grid of the 4th NMOS tube MN4 connects the output of the second inverter INV2, and its source electrode connects the output of clock selection module, and its drain electrode connects the drain electrode of the 4th PMOS MP4; The grid of the 4th PMOS MP4 connects outside soft-start signal, and its source electrode connects the output of clock selection module; The tie point that 3rd PMOS MP3 drain electrode and the 4th PMOS MP4 drain connects the input of the 3rd inverter INV3;
The source electrode of the 5th PMOS MP5 connects power supply, and its grid connects the output of the 3rd inverter INV3, and its drain electrode is by connecing the drain electrode of the 5th NMOS tube MN5 and the input of Schmidt trigger after the first resistance R1; The grid of the 5th NMOS tube N5 connects the output of the 3rd inverter INV3, its source ground; The input of output termination the 4th inverter INV4 of Schmidt trigger; The D input of output termination the tenth 3d flip-flop of the 4th inverter INV4;
The output of the clock signal termination clock selection module of the 7th d type flip flop, its reversed-phase output connects its D input; The in-phase input end of clock signal termination the 7th d type flip flop of the 8th d type flip flop, its reversed-phase output connects its D input; The in-phase input end of clock signal termination the 8th d type flip flop of the 9th d type flip flop, its reversed-phase output connects its D input; The in-phase input end of clock signal termination the 9th d type flip flop of the tenth d type flip flop, its reversed-phase output connects its D input; The in-phase input end of clock signal termination the tenth d type flip flop of the 11 d type flip flop, its reversed-phase output connects its D input; The in-phase input end of clock signal termination the 11 d type flip flop of the tenth 2-D trigger, its reversed-phase output connects its D input, and its in-phase output end connects the clock signal terminal of the tenth 3d flip-flop; The outside enable signal of clearing termination of all d type flip flops; The in-phase output end of the tenth 3d flip-flop is the output of clock count module.
5. a kind of mistake flow counter for soft start protection according to claim 4, it is characterized in that, described second logic processing module is made up of the 5th inverter INV5, hex inverter INV6, the 6th PMOS MP6, the 6th NMOS tube MN6, the second Schmidt trigger, the second resistance R2 and two input nand gates; The outside soft-start signal of input termination of the 5th inverter INV5; The grid of the 6th PMOS MP6 connects the output of the 5th inverter INV5, and its source electrode connects power supply, and its drain electrode is by connecing the drain electrode of the 6th NMOS tube MN6 and the output of the second Schmidt trigger after the second resistance R2; The grid of the 6th NMOS tube MN6 connects the output of the 5th inverter INV5, its source ground; The input of the output termination hex inverter INV6 of the second Schmidt trigger; The first input end of output termination two input nand gate of hex inverter INV6; The output of the second input termination timing module of two input nand gates, its output is the output of the second logic module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510575170.7A CN105207668B (en) | 2015-09-10 | 2015-09-10 | A kind of mistake flow counter protected for soft start |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510575170.7A CN105207668B (en) | 2015-09-10 | 2015-09-10 | A kind of mistake flow counter protected for soft start |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105207668A true CN105207668A (en) | 2015-12-30 |
| CN105207668B CN105207668B (en) | 2017-08-25 |
Family
ID=54955147
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510575170.7A Expired - Fee Related CN105207668B (en) | 2015-09-10 | 2015-09-10 | A kind of mistake flow counter protected for soft start |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105207668B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111428847A (en) * | 2020-03-20 | 2020-07-17 | 湖南品腾电子科技有限公司 | Touch detection counter |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040000934A1 (en) * | 2002-06-28 | 2004-01-01 | Young-Jin Jeon | Clock divider and method for dividing clock signal in DLL circuit |
| CN102566640A (en) * | 2011-12-24 | 2012-07-11 | 西安启芯微电子有限公司 | Voltage-stabilizing circuit with hiccup mode over-current protection function |
| CN102946185A (en) * | 2012-11-26 | 2013-02-27 | 电子科技大学 | Control circuit for improving switching power supply output voltage transient response |
-
2015
- 2015-09-10 CN CN201510575170.7A patent/CN105207668B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040000934A1 (en) * | 2002-06-28 | 2004-01-01 | Young-Jin Jeon | Clock divider and method for dividing clock signal in DLL circuit |
| CN102566640A (en) * | 2011-12-24 | 2012-07-11 | 西安启芯微电子有限公司 | Voltage-stabilizing circuit with hiccup mode over-current protection function |
| CN102946185A (en) * | 2012-11-26 | 2013-02-27 | 电子科技大学 | Control circuit for improving switching power supply output voltage transient response |
Non-Patent Citations (1)
| Title |
|---|
| 陈友福: "单片集成DC-DC智能电源芯片研究与设计", 《中国优秀博硕士学位论文全文数据库 (硕士) 工程科技Ⅱ辑》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111428847A (en) * | 2020-03-20 | 2020-07-17 | 湖南品腾电子科技有限公司 | Touch detection counter |
| CN111428847B (en) * | 2020-03-20 | 2023-08-15 | 湖南品腾电子科技有限公司 | Touch detection counter |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105207668B (en) | 2017-08-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101394171B (en) | Static zero-consumption power-on resetting circuit | |
| CN106532629B (en) | A kind of current foldback circuit with self-recovering function | |
| CN105281726B (en) | A kind of electrification reset circuit | |
| CN102566640B (en) | Voltage-stabilizing circuit with hiccup mode over-current protection function | |
| CN106325449B (en) | A kind of power-on-reset circuit with low power consumption | |
| CN104459564A (en) | Power source burr signal detecting circuit and method preventing power source attack | |
| CN108418420A (en) | A kind of charge pump circuit based on the non-overlapping clock of multichannel | |
| CN105577160A (en) | Self-recovery single particle resistance latch register structure based on time-delay unit | |
| CN102006039A (en) | Reset circuit | |
| CN108551257A (en) | A kind of charge pump construction | |
| CN103983836A (en) | Electric energy meter full voltage loss detection method | |
| CN109428567A (en) | A kind of device for realizing duty ratio adjustment | |
| CN101566645B (en) | Detection circuit for power supply voltage pulse interference | |
| CN105207668A (en) | Overcurrent counter for soft start protection | |
| CN204465490U (en) | A kind of power-on-reset circuit with low power consumption | |
| CN105306023B (en) | Pulse delay circuit | |
| CN104021246B (en) | Self-adaptive length predictor applied to low power consumption fault-tolerant circuit | |
| CN203788252U (en) | Clock filter circuit | |
| CN106200846A (en) | Power on and off reset circuit and chip | |
| CN206259915U (en) | A kind of electrification reset circuit of low-power consumption small size | |
| CN100495915C (en) | CMOS single stabilization circuit | |
| CN206096990U (en) | Electric chip is got to single live wire | |
| CN106230411A (en) | A kind of low-power consumption undersized electrification reset circuit | |
| CN103795378B (en) | Clock filter circuits | |
| CN201210174Y (en) | Detection circuit used for main voltage pulse interference |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170825 Termination date: 20180910 |