CN206259915U - A kind of electrification reset circuit of low-power consumption small size - Google Patents
A kind of electrification reset circuit of low-power consumption small size Download PDFInfo
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- CN206259915U CN206259915U CN201621123317.5U CN201621123317U CN206259915U CN 206259915 U CN206259915 U CN 206259915U CN 201621123317 U CN201621123317 U CN 201621123317U CN 206259915 U CN206259915 U CN 206259915U
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Abstract
The utility model discloses a kind of electrification reset circuit of low-power consumption small size, including power supply time delay module, rising edge generation module, trailing edge generation module, reset pulse generation module and shaping pulse module.Power supply time delay module enters line delay to supply voltage and produces time delay voltage；Rising edge generation module carries out level detection and anti-phase, the step signal of generation rising edge to time delay voltage；Trailing edge generation module enters line delay and anti-phase twice, the step signal of generation trailing edge to time delay voltage；Then both step signals are input to reset pulse generation module, produce low effective reset pulse；Power-on reset signal is exported finally by shaping pulse module.The utility model simple structure, using voltage time delay module and two kinds along generation module, in the case of small size, low-power consumption, realizes the output of stabilization, broad pulse width power-on reset signal.
Description
Technical field
The utility model is related to a kind of electrification reset circuit, more particularly to it is a kind of be applied to low-power consumption small size on reply by cable
Position circuit, belongs to technical field of integrated circuits.
Background technology
With continuing to develop for CMOS on-chip integration systems (SOC), the integrated level of chip is improved constantly, and the function of chip is got over
Come more powerful, Analogous Integrated Electronic Circuits and digital integrated electronic circuit are generally integrated on same chip, and use unified power supply
Power supply.During outside power supply electrifying, due to the state that supply voltage is also not up to stable, the voltage of many circuit nodes
With logic state all in unstable state, in this time period, circuit is more likely to produce the mistake of undesirable appearance, especially
The digital circuit higher for integrated level, indefinite level may produce the mistake of avalanche type, and then influence later stage circuit
Operation.
In order to solve the above problems, electrification reset circuit (Power-On Reset, POR) is arisen at the historic moment.Electrification reset electricity
Road is during power supply electrifying, to detect supply voltage, and normal operating voltage is reached (commonly referred to as in supply voltage
" playing pull-up voltage ") after, initialization clearing is carried out to digital circuit, to ensure the correctness sum-mould hybrid chip of Digital Logic
Normal work.
Fig. 1 show traditional integral form electrification reset circuit structure, when supply voltage VDD begins to ramp up from 0, power supply
RC circuits are begun through to be charged to electric capacity, it is no-delay logical during when charging voltage so that phase inverter is low level by high level upset
The voltage of A points is sent to NAND gate after road overturns phase inverter, realizes the rising edge of electrification reset, when A points voltage passes through time delay
When module reaches another input of NAND gate, the trailing edge of reset signal is realized, finally give power-on reset signal.This electricity
Road there may be problems with：If 1) to realize the power-on reset signal of broad pulse width, very big area may be sacrificed
Could realize；2) want to reach a big pull-up voltage, it is necessary to adjust the device size of RC loops and first phase inverter, this meeting
Reduce selectivity of the electrification reset circuit to power-on time.
The content of the invention
For the technical problem that presently, there are, the utility model provide a kind of low-power consumption, small size, reset pulsewidth wide it is upper
Reset circuit, with simple structure, high performance feature.
To achieve the above object, the utility model is realized by the following technical solutions：
A kind of electrification reset circuit of low-power consumption small size, at least includes：Power supply time delay module, is connected to an external electrical
Source, for entering line delay to described external power source, and exports a time delay voltage；Rising edge generation module, is connected to the electricity
Source time delay module, for carrying out voltage detecting to the time delay voltage, and the voltage after detection is carried out it is anti-phase, to produce rising
The step signal on edge, this signal as reset signal trailing edge ready signal；Trailing edge generation module, is connected to the power supply
Time delay module, it is anti-phase for the first time for being carried out to described time delay voltage, then line delay is entered to the voltage after anti-phase, then to prolonging
When after voltage carry out second anti-phase, to produce the step signal of trailing edge, this signal is accurate as the rising edge of reset signal
Standby signal；Reset pulse generation module, is connected to described rising edge generation module and the trailing edge generation module, for right
The rising edge step signal and trailing edge step signal for receiving carry out with it is non-, using NAND gate logic produce reset pulse；Arteries and veins
Shaping Module is rushed, described reset pulse generation module is connected to, for being amplified and shaping to described reset pulse, and
The output signal as electrification reset circuit with the voltage signal after shaping will be amplified.
Further, in electrification reset circuit of the present utility model, the power supply time delay module circuit contains the first electricity
Hold C1, the second electric capacity C2, p-type metal-oxide-semiconductor M1, p-type metal-oxide-semiconductor M2 and p-type metal-oxide-semiconductor M3, it is defeated for entering line delay to the power supply being input into
Go out time delay voltage.One end of first electric capacity C1, the source electrode of p-type metal-oxide-semiconductor M2 and power supply are connected with each other；First electric capacity C1's is another
The grid of end, the source electrode of p-type metal-oxide-semiconductor M1 and p-type metal-oxide-semiconductor M3 is connected with each other；The drain electrode of p-type metal-oxide-semiconductor M1, the one of the second electric capacity C2
End is connected with each other with ground；The source electrode of the grid, the drain electrode of p-type metal-oxide-semiconductor M2 and p-type metal-oxide-semiconductor M3 of p-type metal-oxide-semiconductor M2 is connected with each other；P
The output end of the grid of type metal-oxide-semiconductor M1, the drain electrode of p-type metal-oxide-semiconductor M3, the other end of the second electric capacity C2 and power supply time delay module is mutual
Connection.
Further, in electrification reset circuit of the present utility model, described rising edge generation module contains first liang
Input nand gate NAND1 constitutes level sensitive circuit, and conjunction is designed by adjusting first liang of device size of input nand gate NAND1
Suitable trigging signal；Described rising edge generation module contains the first phase inverter INV1 and constitutes voltage inversion circuit, for producing
The step signal of rising edge.One input of first liang of input nand gate NAND1 is connected with power supply；First liang of input nand gate
Another input of NAND1 is connected with the output end of power supply time delay module；First liang of output end of input nand gate NAND1 and the
The input connection of one phase inverter INV1；The output of the first phase inverter INV1 is connected with the output end of rising edge generation module.
Further, in electrification reset circuit of the present utility model, described trailing edge generation module contains p-type MOS
Pipe M4, N-type metal-oxide-semiconductor M5 and second liang of input nand gate NAND2 constitute time delay module, by adjusting p-type metal-oxide-semiconductor M4, N-type MOS
Pipe M5 and second liang of device size of input nand gate NAND2 design suitable delay time；Described trailing edge generation module
Voltage inversion circuit is constituted containing the second phase inverter INV2, for producing the step signal of trailing edge.The grid of p-type metal-oxide-semiconductor M4,
The grid of N-type metal-oxide-semiconductor M5 is connected with each other with the output of power supply time delay module；The source electrode of p-type metal-oxide-semiconductor M4, second liang input with it is non-
One input of door NAND2 is connected with each other with power supply；Drain electrode, the drain electrode of N-type metal-oxide-semiconductor M5 and second liang of input of p-type metal-oxide-semiconductor M4
Another input of NAND gate NAND2 is connected with each other；The source electrode of N-type metal-oxide-semiconductor M5 is connected to ground；Second liang of input nand gate
The output end of NAND2 is connected with the input of the second phase inverter INV2；The output end of the second phase inverter INV2 is produced with trailing edge
The output end connection of module.
Further, in electrification reset circuit of the present utility model, described reset pulse generation module contains the 3rd
Two input nand gate NAND3, using NAND gate logic, produce the output of reseting pulse signal.3rd liang of input nand gate NAND3
An input be connected with the output of rising edge generation module；3rd liang of another input of input nand gate NAND3 and decline
Connected along the output of generation module；The output end of the 3rd liang of output end of input nand gate NAND3 and reset pulse generation module
Connection.
Further, in electrification reset circuit of the present utility model, described shaping pulse modular circuit contains the 3rd
Phase inverter INV3 and the 4th phase inverter INV4, is amplified and shaping to input signal, exports power-on reset signal.3rd is anti-phase
The input of device INV3 is connected with the output end of reset pulse generation module；The output end of the 3rd phase inverter INV3 is anti-phase with the 4th
The input connection of device INV4；The output end output power-on reset signal RST of the 4th phase inverter INV4.
Compared with prior art, the utility model has advantages below：
(1) electrification reset circuit in the utility model, power supply time delay module is novel time-lapse module, the addition of the module
So that electrification reset circuit is in the case of small size, remain to realize the power-on reset signal of broad pulse；
(2) electrification reset circuit in the utility model, power supply time delay module on two branch roads due to having electric capacity, electric capacity
Value is smaller, and the voltage change at electric capacity two ends is smaller, and the electric current on two branch roads is all than relatively low；Simultaneously because circuit structure is simple
It is single, substantially reduce the power consumption of electrification reset circuit；
(3) the electrification reset circuit simple structure in the utility model, semiconductor devices only has metal-oxide-semiconductor and electric capacity, reduces
Other devices in different operating environment to circuit produce influence；
(4) the supply voltage allowed band of the electrification reset circuit in the utility model is wider.
Brief description of the drawings
Fig. 1 is the powered reset circuit schematic diagram in background technology；
Fig. 2 is the basic framework figure of electrification reset circuit in the present embodiment；
Fig. 3 is the circuit structure diagram of electrification reset circuit in the present embodiment；
Fig. 4 is the electrification reset voltage waveform view that electrification reset circuit of the present utility model is produced.
Specific embodiment
Implementation method of the present utility model is illustrated below in conjunction with specific embodiments and the drawings.
A kind of electrification reset circuit of the low-power consumption small size in the present embodiment, its basic framework figure is as shown in Figure 2.Including
Power supply time delay module 11, rising edge generation module 12, trailing edge generation module 13, reset pulse generation module 14 and shaping pulse
Module 15, the input termination external power source of power supply time delay module 11, output end and the rising edge generation module of power supply time delay module 11
The input connection of 12 input and trailing edge generation module 13；One input and rising edge of reset pulse generation module 14
The output end connection of generation module 12；The output of another input and trailing edge generation module 13 of reset pulse generation module 14
End connection；The output end of reset pulse generation module 14 is connected with the input of shaping pulse module；Shaping pulse module it is defeated
Go out the voltage at end as the output signal of electrification reset circuit.Wherein, power supply time delay module 11, for prolonging to external power source
When, and export a time delay voltage；Rising edge generation module 12, for carrying out voltage detecting to time delay voltage, and by after detection
Voltage carry out it is anti-phase, to produce the step signal of rising edge, this signal as reset signal trailing edge ready signal；Trailing edge
Generation module 13, it is anti-phase for the first time for being carried out to time delay voltage, then line delay is entered to the voltage after anti-phase, then to time delay after
Voltage carry out second anti-phase, to produce the step signal of trailing edge, this signal prepares letter as the rising edge of reset signal
Number；Reset pulse generation module 14, is carried out and non-, profit for the rising edge step signal and trailing edge step signal to receiving
Reset pulse is produced with NAND gate logic；Shaping pulse module 15, for being amplified to reset pulse and shaping, and will amplify
With the voltage signal after shaping as electrification reset circuit output signal.Physical circuit figure such as Fig. 3 in embodiment.Power supply prolongs
When the circuit of module 11 be made up of the first electric capacity C1, the second electric capacity C2, p-type metal-oxide-semiconductor M1, p-type metal-oxide-semiconductor M2 and p-type metal-oxide-semiconductor M3；On
Rise and be made up of first liang of input nand gate NAND1 and the first phase inverter INV1 along generation module 12；Trailing edge generation module 13 is by P
Type metal-oxide-semiconductor M4, N-type metal-oxide-semiconductor M5, second liang of input nand gate NAND2 and the second phase inverter INV2 are constituted；Reset pulse produces mould
Block 14 is made up of the 3rd liang of input nand gate NAND3；Shaping pulse module is by the 3rd phase inverter INV3 and the 4th phase inverter INV4
Constitute.
On the whole, the circuit structure is connected in the following manner：One end, the source electrode of p-type metal-oxide-semiconductor M2, of the first electric capacity C1
One input of one or two input nand gate NAND1, the source electrode of p-type metal-oxide-semiconductor M4 and second liang of input of input nand gate NAND2
End is connected with each other with power supply；The other end of the first electric capacity C1, the source electrode of p-type metal-oxide-semiconductor M1 are mutually interconnected with the grid of p-type metal-oxide-semiconductor M3
Connect；The drain electrode of p-type metal-oxide-semiconductor M1, one end of the second electric capacity C2, the source electrode of N-type metal-oxide-semiconductor M5 and ground are connected with each other；P-type metal-oxide-semiconductor M2
Grid, the drain electrode of p-type metal-oxide-semiconductor M2 and p-type metal-oxide-semiconductor M3 source electrode be connected with each other；The grid of p-type metal-oxide-semiconductor M1, p-type metal-oxide-semiconductor M3
Drain electrode, the other end of the second electric capacity C2, another input, the grid of p-type metal-oxide-semiconductor M4 of first liang of input nand gate NAND1
Grid with N-type metal-oxide-semiconductor M5 is connected with each other；First liang of output end of input nand gate NAND1 is defeated with the first phase inverter INV1's
Enter end connection；The output of the first phase inverter INV1 is connected with the 3rd liang of input of input nand gate NAND3 mono-.P-type metal-oxide-semiconductor M4's
Drain electrode, the drain electrode of N-type metal-oxide-semiconductor M5 and second liang of another input of input nand gate NAND2 are connected with each other；Second liang input with
The output end of not gate NAND2 is connected with the input of the second phase inverter INV2；The output end of the second phase inverter INV2 with the 3rd liang
Another input connections of input nand gate NAND3.The input of the 3rd phase inverter INV3 is defeated with the 3rd liang of input nand gate NAND3
Go out end connection；The output end of the 3rd phase inverter INV3 is connected with the input of the 4th phase inverter INV4；4th phase inverter INV4's
Output end output power-on reset signal RST.
In the present embodiment, in chip power power up, electrification reset circuit exports a reset signal, concrete analysis
It is as follows：
During electricity on supply voltage VDD, original state, when VDD is zero, the voltage of A points and B points is all zero.
When supply voltage VDD begins to ramp up from 0, due to there is parasitic capacitance, therefore first electric capacity C1, A point and B between A points and B points
Parasitic capacitance CC and the second electric capacity C2 between point form a path, and then supply voltage VDD starts to fill the second electric capacity C2
Electricity.During beginning, A point voltages the comparison of the growth is rapid, and the voltage the comparison of the growth of B points is slow.Voltage between A points and B points
Difference is when reaching the on state threshold voltage of p-type metal-oxide-semiconductor M1, p-type metal-oxide-semiconductor M1 conductings, so as to start drop-down A points voltage so that A points with
The voltage difference increase of VDD.Voltage difference with A points and VDD increases, when the threshold of the voltage difference more than p-type metal-oxide-semiconductor M3 of A points and K points
During threshold voltage, p-type metal-oxide-semiconductor M3 conductings, now B points voltage increase, simultaneously because the presence of p-type metal-oxide-semiconductor M2, the final electricity of B points
Pressure is about：VDD-| VTHP |, wherein threshold voltages of | the VTHP | for p-type metal-oxide-semiconductor.As B points voltage rises, A points and B
The voltage difference of point reduces, and p-type metal-oxide-semiconductor M1 is most turned off at last.Rise because the voltage of B points is first slow, then rise again, finally reach
A value for threshold voltage is subtracted to VDD, therefore the voltage of B points is equivalent to make supply voltage VDD one difference time delay,
Final B points output time delay voltage is about：VDD - |VTHP | .
Because an input C points of first liang of input nand gate NAND1 meet VDD, another input termination B of this NAND gate
Point, with the rising of vdd voltage and B point voltages, when the voltage of VDD and B points reaches first liang of upset of input nand gate NAND1
During level, that is, first liang of detection level of input nand gate NAND1 is reached, first liang of input nand gate NAND1 is realized from electricity high
Low level upset is put down, and sends the voltage after upset to first phase inverter INV1, then the first phase inverter INV1 is to defeated
The voltage for entering realizes anti-phase and shaping, obtains a step signal for rising edge.
For the phase inverter being made up of p-type metal-oxide-semiconductor M4 and N-type metal-oxide-semiconductor M5, signal when phase inverter overturns will be input into
To second liang of input of input nand gate NAND2.Because second liang of another input of input nand gate NAND2 is power supply
Voltage VDD, when second liang of input nand gate NAND2 detects VDD for high level, when D points voltage is low level, second liang of input
NAND gate NAND2 realizes the upset from low level to high level, and sends the voltage after upset to second phase inverter INV2, so
The second phase inverter INV2 realizes anti-phase and shaping to the voltage being input into afterwards, obtains a step signal for trailing edge.
One end of 3rd liang of input nand gate NAND3 connects rising edge step signal, and the 3rd liang of input nand gate NAND3's is another
One termination trailing edge step signal, by after the 3rd liang of NAND gate of input nand gate NAND3, producing a low effective reset
Pulse is exported gives shaping pulse module.
Shaping pulse module is amplified using the 3rd phase inverter IN3 and the 4th phase inverter IN4 to the reset pulse being input into
And shaping, and export a low effective reset signal RST.Fig. 4 is the upper electricity that electrification reset circuit of the present utility model is produced
Resetting voltage waveform diagram.
Additionally, for example, supply voltage allowed band of the present utility model is wider, if it is desired to reduce supply voltage, can be with
Realized by the size for increasing all of PMOS in power supply time delay module 11 and the capacitance for reducing electric capacity C1 and electric capacity C2.This
Outward, the reseting pulse width scope of electrification reset circuit output of the present utility model is about：1us ~ 1ms, again may be by adjusting
The device size of whole power supply time delay module 11 is realized.
The content not being described in detail in this specification belongs to prior art known to professional and technical personnel in the field.
Above example is only basic embodiment of the present utility model, but the not whole of the utility model overlay content,
All equivalents done within the utility model scope, all will be within the utility model protection domain.
Claims (6)
1. a kind of electrification reset circuit of low-power consumption small size, it is characterised in that at least include：
Power supply time delay module (11), is connected to an external power source, prolongs for entering line delay to described external power source, and exporting one
When voltage；
Rising edge generation module (12), is connected to the power supply time delay module (11), for carrying out voltage to the time delay voltage
Detection, and the voltage after detection is carried out it is anti-phase, to produce the step signal of rising edge, this signal as reset signal decline
Along ready signal；
Trailing edge generation module (13), is connected to the power supply time delay module (11), for carrying out to described time delay voltage
It is once anti-phase, line delay then is entered to the voltage after anti-phase, it is that the time delay of reset signal is prepared, then the voltage after time delay is entered
Row second is anti-phase, to produce the step signal of trailing edge, this signal as reset signal rising edge ready signal；
Reset pulse generation module (14), is connected to described rising edge generation module (12) and the trailing edge generation module
(13), for the rising edge step signal and trailing edge step signal to receiving carry out with it is non-, using NAND gate logic produce
Reset pulse；
Shaping pulse module (15), is connected to described reset pulse generation module (14), for entering to described reset pulse
Row amplifies and shaping, and will amplify the output signal with the voltage signal after shaping as electrification reset circuit.
2. the electrification reset circuit of a kind of low-power consumption small size according to claim 1, it is characterised in that：The power supply electricity
Pressure time delay module (11) circuit contains the first electric capacity C1, the second electric capacity C2, p-type metal-oxide-semiconductor M1, p-type metal-oxide-semiconductor M2 and p-type metal-oxide-semiconductor
One end of M3, the first electric capacity C1, the source electrode of p-type metal-oxide-semiconductor M2 and power supply are connected with each other；The other end of the first electric capacity C1, p-type MOS
The source electrode of pipe M1 is connected with each other with the grid of p-type metal-oxide-semiconductor M3；The drain electrode of p-type metal-oxide-semiconductor M1, one end of the second electric capacity C2 and ground phase
Connect；The source electrode of the grid, the drain electrode of p-type metal-oxide-semiconductor M2 and p-type metal-oxide-semiconductor M3 of p-type metal-oxide-semiconductor M2 is connected with each other；P-type metal-oxide-semiconductor M1
Grid, the drain electrode of p-type metal-oxide-semiconductor M3, the output end of the other end of the second electric capacity C2 and power supply time delay module (11) be connected with each other.
3. the electrification reset circuit of a kind of low-power consumption small size according to claim 1, it is characterised in that：Described rising
Constitute level sensitive circuit containing first liang of input nand gate NAND1 along generation module (12), by adjust first liang of input with
The device size of not gate NAND1 designs suitable trigging signal；Described rising edge generation module (12) contains the first phase inverter
INV1 constitutes voltage inversion circuit, for producing the step signal of rising edge；First liang of input of input nand gate NAND1
It is connected with power supply；First liang of another input of input nand gate NAND1 is connected with the output end of power supply time delay module (11)；The
The output end of one or two input nand gate NAND1 is connected with the input of the first phase inverter INV1；The output of the first phase inverter INV1
Output end with rising edge generation module (12) is connected.
4. the electrification reset circuit of a kind of low-power consumption small size according to claim 1, it is characterised in that：Described decline
Time delay module is constituted containing p-type metal-oxide-semiconductor M4, N-type metal-oxide-semiconductor M5 and second liang of input nand gate NAND2 along generation module (13), is led to
Cross adjustment p-type metal-oxide-semiconductor M4, N-type metal-oxide-semiconductor M5 and when second liang of device size of input nand gate NAND2 designs suitable time delay
Between；Described trailing edge generation module (13) constitutes voltage inversion circuit containing the second phase inverter INV2, for producing trailing edge
Step signal；The output of the grid, the grid of N-type metal-oxide-semiconductor M5 and power supply time delay module (11) of p-type metal-oxide-semiconductor M4 is connected with each other；
The source electrode of p-type metal-oxide-semiconductor M4, an input and power supply of second liang of input nand gate NAND2 are connected with each other；The leakage of p-type metal-oxide-semiconductor M4
Pole, the drain electrode of N-type metal-oxide-semiconductor M5 and second liang of another input of input nand gate NAND2 are connected with each other；N-type metal-oxide-semiconductor M5's
Source electrode is connected to ground；Second liang of output end of input nand gate NAND2 is connected with the input of the second phase inverter INV2；Second is anti-
The output end of phase device INV2 is connected with the output end of trailing edge generation module (13).
5. the electrification reset circuit of a kind of low-power consumption small size according to claim 1, it is characterised in that：Described reset
Pulses generation module (14), using NAND gate logic, produces the defeated of reseting pulse signal containing the 3rd liang of input nand gate NAND3
Go out；A 3rd liang of input of input nand gate NAND3 is connected with the output of rising edge generation module (12)；3rd liang input with
Another input of not gate NAND3 is connected with the output of trailing edge generation module (13)；3rd liang of input nand gate NAND3's is defeated
Go out end to be connected with the output end of reset pulse generation module (14).
6. the electrification reset circuit of a kind of low-power consumption small size according to claim 1, it is characterised in that：Described pulse
Shaping Module (15) circuit contains the 3rd phase inverter INV3 and the 4th phase inverter INV4, input signal is amplified and shaping,
Output power-on reset signal；The input of the 3rd phase inverter INV3 is connected with the output end of reset pulse generation module (14)；The
The output end of three phase inverter INV3 is connected with the input of the 4th phase inverter INV4；In the output end output of the 4th phase inverter INV4
Reset signal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621123317.5U CN206259915U (en) | 2016-10-14 | 2016-10-14 | A kind of electrification reset circuit of low-power consumption small size |
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| CN201621123317.5U CN206259915U (en) | 2016-10-14 | 2016-10-14 | A kind of electrification reset circuit of low-power consumption small size |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106230411A (en) * | 2016-10-14 | 2016-12-14 | 湘潭芯力特电子科技有限公司 | A kind of low-power consumption undersized electrification reset circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106230411A (en) * | 2016-10-14 | 2016-12-14 | 湘潭芯力特电子科技有限公司 | A kind of low-power consumption undersized electrification reset circuit |
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