CN106712752A - Quenching reset circuit for single photon avalanche diode detector - Google Patents
Quenching reset circuit for single photon avalanche diode detector Download PDFInfo
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- CN106712752A CN106712752A CN201611127824.0A CN201611127824A CN106712752A CN 106712752 A CN106712752 A CN 106712752A CN 201611127824 A CN201611127824 A CN 201611127824A CN 106712752 A CN106712752 A CN 106712752A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/78—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
Abstract
The invention discloses a quenching reset circuit for a single photon avalanche diode detector. The reset circuit comprises three parts such as a quenching circuit, a reset circuit and an avalanche signal output portion, and is characterized in that the quenching circuit is composed of five MOS transistors, and the five MOS transistors form a positive feedback circuit for voltage variations of a node a; the reset circuit is composed of 17 MOS transistors; and the avalanche signal output portion is composed of eight MOS transistors. The advantages are that the quenching reset circuit is high in reliability, and a reset operation is ensured to be performed after avalanche current generated by the SPAD (Single Photon Avalanche Diode) detector is sufficiently quenched because of adoption of a Schmitt trigger with high threshold level. In addition, the waveform quality of avalanche pulses generated by the circuit is high, avalanche signals are converted into narrow pulses through a NOR gate, and then the narrow pulses are shaped by a two-stage inverter and act as final output avalanche pulses, so that the output pulses are enabled to be steeper, and processing of a counting circuit is facilitated.
Description
Technical field
The present invention for single-photon avalanche photodiode detector propose a kind of reliability it is high reset circuit is quenched
And method, belong to single photon detection technical field.
Background technology
SPAD (SinglePhotonAvalanche Diode) is single-photon avalanche photodiode.In photodetection neck
In domain, traditional photomultiplier (PMT) can not be satisfied with the detection under high speed low light condition, tradition imaging skill
Art receives certain limitation in terms of image taking speed and pixel sensitivity, then starts solid state photomultiplier pipe occur, i.e., singly
Photon avalanches diode detector.In recent years, the SPAD of high density, high integration is produced using present standard CMOS process
Detector array turns into the development trend of this single photon avalanche diode detector.
One SPAD pixel cell includes two circuits, and one is that reset circuit is quenched, and another is counting circuit.When
After SPAD is quenched, the bias voltage at its two ends needs to return to initial bias high, waits the arrival of photon next time, recovers
The process of SPAD two ends bias is referred to as resetting.Reset circuit is quenched traditional, due to coming only with common phase inverter
Sensing avalanche current, therefore in reset loop, it is easy to there is such situation：I.e. in the biased electrical at avalanche diode two ends
Pressure is dropped to when below avalanche voltage, and the bias at SPAD two ends is withdrawn into initial bias voltage by the pipe that is just reset, and causes SPAD to detect
Device is not quenched completely.If the long enough that the time delay of delay circuit is not designed, it is easier to produce such result.
Therefore, SPAD reset circuit is quenched in, it is necessary to improve the stability of the process of being quenched.
The content of the invention
For the problem that process easily fails that is quenched of traditional active quenching circuit, the present invention proposes a kind of reliability
High is quenched reset circuit,
Specific technical scheme be it is a kind of reset circuit is quenched for single photon avalanche diode detector, reset electricity
Road includes following 3 parts：
(1) loop is quenched, is made up of 5 metal-oxide-semiconductors, be respectively PMOS MP9, MP13, NMOS tube MN10, MN11, MN15,
MN10 is connected together for MOS diode connection, i.e. grid with drain electrode, and the grid of MP13 and MN15 is connected together, and is directly connected to
To the anode of SPAD, i.e. a nodes, a phase inverter is constituted, directly senses avalanche current, its output connects the grid of MP9 and MN11,
When a nodes are low level, the output m node potentials of phase inverter are high level, and PMOS MP9 disconnects, MN11 conductings, so that will
A nodes are maintained at low level；When a nodes are high level, m node potentials are low level, PMOS MP9 conductings, NMOS tube
MN11 disconnects, and so as to a nodes are maintained at into high level, this 5 metal-oxide-semiconductors constitute a positive feedback to the change of a node voltages
Circuit.
(2) reset loop, is made up of 17 metal-oxide-semiconductors, including a Schmidt trigger, by PMOS MP10,
MP11, MP12, NMOS tube MN12, MN13, MN14 compositions, a delay circuit, by PMOS MP0, MP1, MP2, MP3, MP4,
NMOS tube MN0, MN1, MN2, MN3, MN4 composition, a reset transistor NMOS tube MN9, the input of Schmidt trigger is SPAD spies
The anode of device is surveyed, the change of avalanche current is directly sensed, the output of Schmidt trigger, i.e. p node are directly connected to delay circuit
Input, the change of the output level of Schmidt trigger passes to delay circuit, and delay circuit is made up of phase inverter, signal warp
The grid that delay circuit passes to reset transistor NMOS tube MN9 is crossed, when a node potentials are high level, p node current potential is close by applying
Special trigger is changed into low level, and reset node potentials are changed into high level by delay circuit, then drag down a node potentials, enter
Row resets and operates；When a node potentials are low level, p node current potential is changed into high level, reset sections by Schmidt trigger
Point current potential is changed into low level by delay circuit, and reset transistor MN9 disconnects, and now a node potentials remain low level.
(3) avalanche signal output par, c, is made up of 8 metal-oxide-semiconductors, including a nor gate, by PMOS MP5,
MP6, NMOS tube MN5, MN6 composition, two phase inverters, by PMOS MP7, MP8, NMOS tube MN7, MN8 composition, the two of nor gate
Individual input is respectively the input of above-mentioned phase inverter delay circuit, i.e. p node and output, i.e. reset nodes, the letter of the two nodes
Number by the treatment of nor gate just obtain a pulsewidth be the delay circuit time difference a pulse signal, it is saved than single p
The signal of point or reset nodes is narrower, and burst pulse is that the signal of q nodes is converted into r nodes by the treatment of one-level phase inverter again
Signal, then just obtain final output i.e. out nodes by one-level phase inverter.
Phase inverter in above-mentioned reset loop can be 5,7,9 grades.
Beneficial effects of the present invention：
It is 1. of the invention that reset circuit reliability is quenched is high：Using the Schmidt trigger with high threshold level, it is ensured that
The avalanche current that SPAD detectors are produced fully is quenched just carries out reset operation afterwards.
2. the snowslide impulse waveform quality that circuit of the present invention is produced is high：Avalanche signal is become by narrow arteries and veins by a nor gate
Punching, afterwards two-stage phase inverter using after this burst pulse shaping as final output snowslide pulse so that output pulse it is more steep,
It is easy to the treatment of counting circuit.
Brief description of the drawings
Fig. 1 is the circuit diagram of quenching circuit of the present invention.
Fig. 2 be quenching circuit of the present invention simulation time be 5 μ s result figure.
Fig. 3 is the partial enlarged drawing of Fig. 2 of quenching circuit of the present invention.
Fig. 4 is the corresponding domain of quenching circuit of the present invention.
Specific embodiment
Patent of the present invention is described in further detail below in conjunction with Figure of description.
As shown in figure 1, for the present invention is quenched reset circuit figure.The circuit is by an avalanche diode SPAD, 14 NMOS
Pipe and 16 PMOSs are constituted, and are specifically included：NMOS tube MN0, MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9,
MN10, MN11, MN12, MN13, PMOS MP0, MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, MP11,
MP12、MP13、MP14、MP15.Wherein the negative electrode of SPAD (being k nodes in Fig. 1) connects bias voltage (Vbreak+Vex)；NMOS tube
MN9 is reset transistor, and its grid connects the output (drain electrode of PMOS MP0) of delay circuit, and drain electrode connects the anode (figure of diode SPAD
It is a nodes in 1)；The drain and gate of NMOS tube MN10 connects together, and forms a structure for the MOS diode of small resistor, is
Avalanche current provides a low impedance path；The source electrode of PMOS MP9 meets VDD, and drain electrode connects the grid of MN10；The leakage of NMOS tube MN11
Pole connects the source electrode of MN10, and its grid connects the grid of PMOS MP9；PMOS MP13 and NMOS tube MN15 one Low threshold of composition
Phase inverter.PMOS MP10, MP11, MP12, NMOS tube MN12, MN13, MN14 constitute a Schmidt trigger；NMOS tube
MN0, MN1, MN2, MN3, MN4, PMOS MP0, MP1, MP2, MP3, MP4 constitute a delay circuit being made up of phase inverter,
The input of delay circuit is the grid of NMOS tube MP4, and p node is corresponded in figure, and delay circuit is output as PMOS MP0's
Drain electrode, in Fig. 1 corresponding to reset nodes；NMOS tube MN5, MN6, PMOS MP5, MP6 constitutes a nor gate, NAND gate
Two input nodes be respectively p node and reset nodes；NMOS tube MN7, PMOS MP7 constitute a phase inverter, its input
It is the output (being q nodes in Fig. 1) of nor gate；NMOS tube MN8, PMOS MP8 constitute afterbody phase inverter, and its input is preceding
The output (being r nodes in Fig. 1) of one-level phase inverter, the effect of the two phase inverters is to the snowslide shaping pulse of output.
Single-photon avalanche diode (SPAD) detector is biased in more than breakdown voltage (Vbreak+Vex), is now in
Reform Mode.Wherein Vbreak is breakdown voltage, and Vex is the part that bias voltage exceedes avalanche voltage, commonly referred to overbias.
SPAD detectors under Reform Mode once receive photon (even single photon), and the carrier of photosensitive area will be produced
Raw collision, so as to snowslide phenomenon occur in the presence of highfield.If drop to the bias voltage of SPAD in the short time punctured
Below voltage, avalanche process will terminate, and SPAD detectors are quenched.
As shown in figure 1, circuit includes three parts：Loop (for positive feedback loop) is quenched, reset loop is (for negative-feedback is returned
Road), snowslide pulse output signals process part.In original state, the anode (a nodes in Fig. 1) of SPAD is in 0 current potential, p sections
Point current potential and m node potentials are in high potential, and reset node potentials are in 0 current potential.When SPAD detectors receive the light period of the day from 11 p.m. to 1 a.m,
Avalanche current can be produced, there are a large amount of positive charges to flow to anode (a nodes) from the negative electrode (k nodes) of SPAD, then a node potentials are opened
Begin to rise, when a node potentials rise to the half of supply voltage, the output (m points) of the phase inverter being made up of MP13 and MN15
Begin to be reduced to 0 current potential by supply voltage, i.e. the grid of NMOS tube MN9 and MN11 is reduced to 0 current potential, the grid drop of MN11
It is low so that the channel resistance increase of MN11, now the path of releasing of avalanche current is blocked.Additionally, the grid potential drop of MP9
The low channel resistance for causing MP9 is reduced, and electric current directly flows to its drain electrode from the source electrode of MP9 (connecing supply voltage), promotes a nodes
Current potential is raised rapidly.Then circuit can be completed in a relatively short time the process being quenched.
On reset loop, only when a node potentials exceed the half of supply voltage and reach the upper of schmitt inverter
During threshold value (i.e. the bias voltage of SPAD is reached below avalanche voltage), Schmidt trigger just starts to start, and its output is (in Fig. 1
It is p node) start by the input reduction of high level reduction, i.e. phase inverter delay circuit (hereinafter referred to as delay circuit), due to prolonging
When circuit (5 grades of phase inverters) is constituted by odd number phase inverter, so delay circuit output (in Fig. 1 be reset nodes) is raised,
That is the grid voltage of NMOS tube MN9 (reset transistor) is raised, so that MN9 is turned on, is formed between the anode and ground of diode SPAD
One current path, then a node potentials come back to 0 current potential, and the now output of Schmidt trigger can be raised, by one
Individual delay circuit, the grid of NMOS tube MN9 is changed into low level, and reset transistor MN9 disconnects.Now a node potentials remain 0 current potential,
Wait the arrival of photon signal next time.
It is whole to be quenched after reset circuit sensed avalanche current, by the signal output of avalanche current to counting circuit
Go.The present invention is processed the input and output node that export delay circuit by exporting branch road, and obtains final output.
Output branch road includes 1 nor gate, 2 phase inverters.Q nodes and reset nodes are then obtained as two inputs of nor gate
To a burst pulse, in the shaping by two-stage phase inverter so that the rising and falling time of output pulse is shorter, and waveform is more
It is preferable, it is easy to the treatment of subsequent counter circuit.
For ease of skilled artisan understands that the present invention, there is presently provided a specific implementation example：During the present invention is based on
The international 0.18 μm CMOS technology of core is emulated to the above-mentioned reset circuit that is quenched, and simulation parameter is specific as follows：Supply voltage
It is 3.3V；The avalanche breakdown voltage of the VerilogA models of the SPAD that this emulation is used is 12.2V, and overbias is 2.1V, therefore
Bias voltage is 14.3V；Photon pulse is replaced with voltage pulse, and pulse width is 100ps, and the pulse period is 300ns.Based on
Upper simulation parameter, the simulation result figure that the present invention has carried out the emulation of duration 5us and obtained as shown in Figures 2 and 3.In Fig. 2
Abscissa is simulation time, and 7 ordinates are respectively photonic analogy pulse signal (photon) and 6 electricity of node in circuit
Pressure signal, this 6 voltage signals are followed successively by a nodes, p node, reset nodes, q nodes, r nodes, out nodes.Can from Fig. 2
To see, when no photon pulse arrives, SPAD diodes can also produce snowslide high current, and this is due in SPAD
The dark counting of certain occurrence probability and the factor of afterpulse are added in VerilogA models, such model is more nearly very
The SPAD detectors that real technique is manufactured.Fig. 3 takes the partial enlarged drawing of 419ns to 438ns for the abscissa of Fig. 2, in detail
Describe the course of work that reset circuit is quenched of the invention.From figure 3, it can be seen that of the invention be quenched the dead of reset circuit
Time is 14.2ns, and Schmidt trigger just overturns when a node voltages rise to 2.25V, the biasing at diode two ends
Voltage continues to rise already below 12.05V, afterwards a node voltages, and diode both end voltage continues to decline, far below breakdown potential
Pressure, illustrates that the high current of SPAD detectors is fully quenched.The Schmidt trigger is reduced to 1.1V in a node voltages
When, just overturn.Can be seen that the average delay produced by 5 grades of phase inverter delay circuits is from p node and reset nodes
3.5ns.Within the time of this 3.5ns, cause that a node voltages continue to climb to voltage (SPAD detectors two ends higher enough
Bias voltage be reduced to below bias voltage).P node and reset nodes are two inputs of the OR circuit in output stage
End, the output node of nor gate is q nodes.Only when two input signals of nor gate are simultaneously 0 current potential, output q nodes are
It is high level, the corresponding output q nodes of other input states are all 0 current potential, the 5th row institute of simulation waveform such as Fig. 3 of node q
Show.The signal of q nodes is transferred to r nodes by a phase inverter, and the signal of r nodes is transferred to final defeated by a phase inverter
The signal of egress out, then in analogous diagram, obtains the waveform of r nodes after the waveform upset of q nodes, the waveform of r nodes is turned over
The waveform of out nodes is obtained after turning.So the synchronous waveform of the waveform of out nodes and q nodes changes, but pulse rise and under
The time of drop is shorter, and waveform is more preferable.
Fig. 4 is the layout design that reset circuit is quenched of the invention, including 1 SPAD detector, 14 NMOS tubes
With 16 PMOSs.A diameter of 26 μm of the SPAD detectors, PMOS MP0, MP1, the width of MP2, MP3, MP4 and length point
Wei 350nm and 2 μm；NMOS tube MN0, MN1, the width of MN2, MN3, MN4 and length are respectively 350nm and 1.5 μm；PMOS
The width and length of MP5, MP6 are respectively 1 μm and 300nm；NMOS tube MN5, MN6, the width of MN7, MN8 and length are respectively 1 μ
M and 350nm；The width and length of PMOS MP7, MP8 are respectively 2 μm and 300nm；Width and the length difference of PMOS MP9
It is 2 μm and 300nm；The width and length of NMOS tube MN9 are respectively 3 μm and 350nm；Width and the length difference of NMOS tube MN10
It is 500nm and 1 μm；The width and length of NMOS tube MN11 are respectively 1 μm and 500nm；The width of PMOS MP10, MP11, MP12
Degree and length are respectively 1 μm and 300nm；NMOS tube MN12, MN13, the width of MN14 and length are respectively 400nm and 350nm；
The width and length of PMOS MP13 are respectively 500nm and 350nm；The width and length of NMOS tube MN15 be respectively 3 μm and
350nm；The final design domain that reset circuit is quenched out is as shown in Figure 4.
Claims (2)
1. it is a kind of that reset circuit is quenched for single photon avalanche diode detector, it is characterised in that the reset circuit include with
Lower 3 parts：
(1) loop is quenched, is made up of 5 metal-oxide-semiconductors, be respectively PMOS MP9, MP13, NMOS tube MN10, MN11, MN15, MN10
It is that MOS diode connection, i.e. grid are connected together with drain electrode, the grid of MP13 and MN15 is connected together, and is directly connected to
The anode of SPAD, i.e. a nodes, constitute a phase inverter, directly sense avalanche current, and its output connects the grid of MP9 and MN11, when
When a nodes are low level, the output m node potentials of phase inverter are high level, and PMOS MP9 disconnects, MN11 conductings, so as to by a
Node is maintained at low level；When a nodes are high level, m node potentials are low level, PMOS MP9 conductings, NMOS tube MN11
Disconnect, so as to a nodes are maintained at into high level, this 5 metal-oxide-semiconductors constitute a positive-feedback circuit to the change of a node voltages；
(2) reset loop, is made up of 17 metal-oxide-semiconductors, including a Schmidt trigger, by PMOS MP10, MP11,
MP12, NMOS tube MN12, MN13, MN14 compositions, a delay circuit, by PMOS MP0, MP1, MP2, MP3, MP4, NMOS tube
MN0, MN1, MN2, MN3, MN4 composition, a reset transistor NMOS tube MN9, the input of Schmidt trigger is SPAD detectors
Anode, directly senses the change of avalanche current, and the output of Schmidt trigger, i.e. p node are directly connected to the defeated of delay circuit
Enter, the change of the output level of Schmidt trigger passes to delay circuit, and delay circuit is made up of phase inverter, signal is by prolonging
When circuit pass to the grid of reset transistor NMOS tube MN9, when a node potentials are high level, p node current potential is touched by Schmidt
Hair device is changed into low level, and reset node potentials are changed into high level by delay circuit, then drag down a node potentials, are answered
Bit manipulation；When a node potentials are low level, p node current potential is changed into high level, reset nodes electricity by Schmidt trigger
Position is changed into low level by delay circuit, and reset transistor MN9 disconnects, and now a node potentials remain low level；
(3) avalanche signal output par, c, is made up of 8 metal-oxide-semiconductors, including a nor gate, by PMOS MP5, MP6,
NMOS tube MN5, MN6 composition, two phase inverters, by PMOS MP7, MP8, NMOS tube MN7, MN8 composition, two of nor gate are defeated
Enter the input of respectively above-mentioned phase inverter delay circuit, i.e. p node and output, i.e. reset nodes, the signal warp of the two nodes
The treatment for crossing nor gate just obtains the pulse signal that a pulsewidth is the delay circuit time difference, its than single p node or
The signal of reset nodes is narrower, and burst pulse is that the signal of q nodes is converted into r node signals by the treatment of one-level phase inverter again,
Again final output i.e. out nodes are just obtained by one-level phase inverter.
It is 2. according to claim 1 that reset circuit is quenched for single photon avalanche diode detector, it is characterised in that
Phase inverter in the reset loop can be 5,7,9 grades.
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| CN107425847A (en) * | 2017-07-17 | 2017-12-01 | 南京邮电大学 | A kind of charge transfer type simulation based on rising edge of a pulse triggering counts reading circuit |
| CN109343158A (en) * | 2018-12-10 | 2019-02-15 | 安徽沃特水务科技有限公司 | A kind of anti-rainfall is failed to report and more datagram-style telemetering terminals |
| CN109343157A (en) * | 2018-12-10 | 2019-02-15 | 安徽沃特水务科技有限公司 | A kind of accurate remote rain amount terminal |
| CN110061727A (en) * | 2019-03-26 | 2019-07-26 | 杭州电子科技大学 | / reset circuit and its method is quickly quenched in single photon avalanche diode detector |
| CN110138364A (en) * | 2018-02-09 | 2019-08-16 | 佳能株式会社 | Photoelectric conversion device and camera system |
| CN110274697A (en) * | 2019-06-18 | 2019-09-24 | 西安电子科技大学 | A kind of quick active quenching circuit applied to single-photon avalanche diode |
| CN111294528A (en) * | 2018-11-21 | 2020-06-16 | 佳能株式会社 | Photoelectric conversion device, driving method thereof, imaging system, and moving object |
| CN111999719A (en) * | 2019-05-10 | 2020-11-27 | 中国科学院半导体研究所 | Single photon TOF image sensor for laser radar |
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| CN107425847B (en) * | 2017-07-17 | 2020-07-14 | 南京邮电大学 | Charge transfer type analog counting reading circuit based on pulse rising edge triggering |
| CN107425847A (en) * | 2017-07-17 | 2017-12-01 | 南京邮电大学 | A kind of charge transfer type simulation based on rising edge of a pulse triggering counts reading circuit |
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| CN109343157B (en) * | 2018-12-10 | 2021-06-01 | 安徽沃特水务科技有限公司 | Accurate rainfall telemetering terminal |
| CN109343157A (en) * | 2018-12-10 | 2019-02-15 | 安徽沃特水务科技有限公司 | A kind of accurate remote rain amount terminal |
| CN109343158A (en) * | 2018-12-10 | 2019-02-15 | 安徽沃特水务科技有限公司 | A kind of anti-rainfall is failed to report and more datagram-style telemetering terminals |
| CN110061727A (en) * | 2019-03-26 | 2019-07-26 | 杭州电子科技大学 | / reset circuit and its method is quickly quenched in single photon avalanche diode detector |
| CN111999719A (en) * | 2019-05-10 | 2020-11-27 | 中国科学院半导体研究所 | Single photon TOF image sensor for laser radar |
| CN111999719B (en) * | 2019-05-10 | 2024-03-12 | 中国科学院半导体研究所 | Single photon TOF image sensor for laser radar |
| CN110274697A (en) * | 2019-06-18 | 2019-09-24 | 西安电子科技大学 | A kind of quick active quenching circuit applied to single-photon avalanche diode |
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