CN115574936A

CN115574936A - SPAD quenching circuit based on current comparison

Info

Publication number: CN115574936A
Application number: CN202211108771.3A
Authority: CN
Inventors: 王向展; 周洲; 张中; 张启辉; 宁宁
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2022-09-13
Filing date: 2022-09-13
Publication date: 2023-01-06

Abstract

The invention belongs to the technical field of analog integrated circuits, and particularly relates to a SPAD quenching circuit based on current comparison. The current mirror is used for sensing avalanche current, and then avalanche current signals are detected through current comparison and are output pulse signals after being processed by the inverter; the structure effectively accelerates the response speed of single photon detection and shortens the quenching time, thereby reducing the charge quantity of the single photon avalanche photodiode SPAD; and a delay holding circuit with adjustable time is adopted, so that the probability of generating non-ideal factors such as rear pulse and the like is reduced, the circuit flexibility is increased and the circuit is more reliable according to the characteristics of different single photon avalanche photodiodes SPAD. The quenching and resetting speed of the invention is fast, and the quenching and resetting of the single photon avalanche photodiode can be realized within a few nanoseconds. The problem that the quenching reset time is long due to the low avalanche current response speed of a traditional single-photon detector quenching circuit, and therefore single-photon detection efficiency is low is effectively solved.

Description

SPAD quenching circuit based on current comparison

Technical Field

The invention belongs to the technical field of analog integrated circuits, and particularly relates to a SPAD quenching circuit based on current comparison.

Background

The Single-Photon Avalanche photodiode (SPAD) is widely applied to Single-Photon laser ranging, homeland security and monitoring, quantum encryption systems and fluorescence life detection by virtue of the advantages of long detection distance, high detection sensitivity and the like. The single photon avalanche photodiode realizes the detection of single photon by utilizing the avalanche multiplication effect of a current carrier, works in a Geiger mode, namely works in a very small voltage range which exceeds the breakdown voltage but is not broken down, at the moment, a high electric field is formed by high voltage in the single photon avalanche photodiode SPAD and is positioned in a very sensitive working range, the single photon avalanche photodiode can generate milliampere avalanche current within picosecond level as long as weak optical signals exist, and the response speed is very high. Due to a high electric field, carrier triggering generated by a single photon is a self-sustaining process, multiplication gain is infinite, an avalanche process can be continued all the time, otherwise, the continuous avalanche current can generate excessive power consumption, so that a detector generates heat, a device can be damaged finally, and next detection cannot be carried out.

In addition, the single photon avalanche photodiode SPAD has non-ideal factors such as dark counting, post-pulse effect, dead time, noise and the like in single photon detection, and the factors limit the detection efficiency which can be finally achieved by single photon detection. In order to reduce the influence of non-ideal factors, a quenching circuit is generally required to control the SPAD working voltage of the single photon avalanche photodiode: the single photon avalanche photodiode SPAD reverse bias voltage is rapidly reduced to be lower than avalanche breakdown voltage to quench avalanche current, after quenching is completed, the reverse bias voltage of the single photon avalanche photodiode SPAD is reset to be higher than the avalanche breakdown voltage, a standby state is recovered, and the next detection of avalanche signals is waited, so that the self-sustaining effect influence of the avalanche current is reduced.

The quenching circuit has an important influence on single photon detection, and mainly comprises a passive quenching circuit, an active quenching circuit and a gating quenching circuit. The passive quenching circuit is simple in structure, but the reset time is long, the total dead time is long, the post-pulse effect is obvious, the detection efficiency of the detector is greatly influenced, and therefore a passive quenching mode is rarely adopted in the actual circuit design. The design of the active quenching circuit effectively overcomes the defects of the passive quenching circuit, the required quenching time and the reset time are shorter, the dead time is shorter, and the single photon detection efficiency is effectively improved; however, in the active quenching circuit, the quenching time is mainly determined by the sensitivity of the comparator and the delay time of detection, and if the delay time of the comparator is longer, the quenching time is too long. The gate-controlled quenching circuit can reduce the bias voltage at two ends of a single photon avalanche photodiode SPAD in a short time just after avalanche occurs, output avalanche pulses immediately, and reset to working voltage quickly after pulse duration, but the gate-controlled quenching circuit can only quench photon signals with known arrival time and discontinuity.

In the prior art, a quenching circuit generally adopts voltage induction or current induction mode avalanche current, and realizes the bias state of working voltages at two ends of a single photon avalanche photodiode SPAD through voltage detection; therefore, the response speed is slow, thereby influencing the quenching reset time, increasing the dead time and reducing the detection efficiency of single photons.

Disclosure of Invention

Aiming at the problems or the defects, the invention provides the SPAD quenching circuit based on the current comparison, which aims to solve the problem that the quenching reset time is long due to the slow response speed of the avalanche current of the traditional single-photon detector quenching circuit, so that the single-photon detection efficiency is low.

A SPAD quenching circuit based on current comparison comprises a single photon avalanche photodiode SPAD, a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a first inverter INV1, a delay holding circuit and a current comparator. The first MOS transistor M1, the second MOS transistor, the third MOS transistor and the fourth MOS transistor are all N-type MOS transistors; the fifth MOS tube is a P-type MOS tube;

the first MOS tube M1 is used as a reset tube, the grid electrode of the first MOS tube M1 is connected with the output end of the delay holding circuit, and the drain electrode of the first MOS tube M1 is connected with the anode of the single photon avalanche photodiode SPAD, the drain electrodes of the second MOS tube M2 and the fifth MOS tube M5, and the grid electrodes of the third MOS tube M3 and the fourth MOS tube M4; the source of the first MOS transistor M1 is grounded.

When the first MOS tube M1 receives a reset signal REC output by the delay holding circuit, the first MOS tube is conducted, and the potential at the anode point of the single photon avalanche photodiode SPAD is pulled down to the ground, so that the reverse bias voltage at the two ends of the single photon avalanche photodiode SPAD is greater than the avalanche breakdown voltage, the single photon avalanche photodiode SPAD is restored to a working state, and the next single photon triggering is waited.

The grid electrode of the second MOS tube M2 is interconnected with the grid electrode of the fifth MOS tube M5 and is connected to the output end of the current comparator, and the source electrode of the second MOS tube M2 is connected with the drain electrode of the third MOS tube M3; and the source electrode of the fifth MOS tube M5 is connected with the power supply voltage VDD.

The source electrodes of the third MOS tube M3 and the fourth MOS tube M4 are grounded; the third MOS tube M3 and the fourth MOS tube M4 form a current mirror structure and are used for copying a current Ispad generated by an avalanche branch of the single photon avalanche photodiode SPAD; the drain of the fourth MOS transistor M4 connects the current Ispad with the external avalanche threshold current Iref for a difference and outputs a current signal Iin to the input terminal of the current comparator, where the current comparison is performed.

The input end of the first inverter INV1 is connected with the output end of the current comparator, and the output end of the first inverter INV1 is connected with the input end of the delay holding circuit; the first inverter INV1 inverts the avalanche current pulse signal OUTb as an input signal of the delay holding circuit.

The cathode voltage of the single photon avalanche photodiode SPAD is the avalanche breakdown voltage Vpeak of the single photon avalanche photodiode SPAD plus the power supply voltage VDD, so that the reverse bias voltage of the single photon avalanche photodiode SPAD in the working state is larger than the avalanche breakdown voltage. The avalanche branch current Ispad of the single photon avalanche photodiode SPAD is a current mirror structure mirror current composed of a third MOS tube M3 and a fourth MOS tube M4, and then is compared with an avalanche threshold current Iref through a current comparator to output a logic level 0.

The input of the current comparator is connected with the drain electrode of the fourth MOS transistor M4 and avalanche threshold current Iref input from the outside; and the avalanche branch circuit is used for detecting an avalanche signal, comparing the avalanche branch current Ispad with the avalanche threshold current Iref when the avalanche branch current Ispad of the single photon avalanche photodiode SPAD is generated, and outputting an avalanche current pulse signal OUTb to the gates of the first inverter INV1 and the fifth MOS tube M5.

The delay holding circuit is used for generating a reset signal REC of the single photon avalanche photodiode SPAD quenching circuit, resetting the reverse bias voltage of the single photon avalanche photodiode SPAD to be above the avalanche breakdown voltage, recovering the state to be worked and waiting for the next detection of the avalanche signal.

Before a photon arrives, the single photon avalanche photodiode SPAD is not triggered by a photon, the current in an avalanche branch is extremely small, the avalanche current Ispad copied by a current mirror structure is compared with the avalanche threshold current Iref, the Ispad is not more than Iref, iin is not less than 0, the output signal OUTb of the current comparator is at a high level, the first MOS tube M1 and the fifth MOS tube M5 are cut off, the second MOS tube M2 is conducted to form a low-resistance path, so that the anode single photon potential of the single photon avalanche photodiode SPAD is at a low level, the reverse bias voltage at two ends of the single photon avalanche photodiode SPAD is greater than the avalanche breakdown voltage Vbreak, and the circuit is in a stable state to be detected by the photon.

When photons arrive, the single photon avalanche photodiode SPAD generates an avalanche current Ispad, and the avalanche current Ispad is copied through a current mirror structure and compared with an avalanche threshold current Iref. Ispad is larger than Iref, iin is smaller than 0, the output signal OUTb of the current comparator is low level, the fifth MOS tube M5 is conducted, the second MOS tube M2 is cut off, and the anode potential of the single photon avalanche photodiode SPAD is pulled up to high level, so that the reverse bias voltage at two ends of the single photon avalanche photodiode SPAD is reduced to be lower than avalanche breakdown voltage, the avalanche self-holding effect of the single photon avalanche photodiode SPAD is stopped, and the purpose of quenching is achieved.

Meanwhile, after the avalanche current pulse signal OUTb output by the over-current comparator is inverted through the first inverter INV1, the delay holding circuit delays the time and outputs a reset signal REC, so that the first MOS tube M1 serving as a reset tube is conducted, the potential at the anode point of the single-photon avalanche photodiode SPAD is pulled down to the ground, the reverse bias voltage at the two ends of the single-photon avalanche photodiode SPAD is greater than the avalanche breakdown voltage, the working state is recovered, and the next single-photon triggering is waited.

Further, the delay holding circuit includes a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, and a second inverter INV2; the sixth MOS transistor M6, the seventh MOS transistor M7 and the ninth MOS transistor M9 are all N-type MOS transistors, and the eighth MOS transistor M8 is a P-type MOS transistor.

The source electrode of the sixth MOS transistor M6 and the drain electrode and the source electrode of the ninth MOS transistor M9 are all grounded, and the ninth MOS transistor M9 is used as the MOS capacitor C1.

The drain electrode of the eighth MOS transistor M8 is connected to the source electrode of the seventh MOS transistor M7, the source electrode of the eighth MOS transistor M8 is connected to the power supply voltage, the gate electrode of the eighth MOS transistor M8 is connected to the external control voltage, and the control voltage is used for regulating and controlling the delay time of the delay holding circuit.

The drain electrode of the seventh MOS transistor M7, the drain electrode of the sixth MOS transistor M6 and the gate electrode of the ninth MOS transistor M9 are connected with the input end of the second inverter INV2; the second inverter INV2 inverts the charged or discharged gate voltage of the ninth MOS transistor M9 to generate the reset signal REC, and the output terminal of the reset signal REC is used as the output terminal of the delay holding circuit to output the reset signal REC to the gate of the first MOS transistor M1.

Further, the avalanche threshold current Iref =200uA. The critical value of avalanche current of the single photon avalanche photodiode SPAD in a Geiger mode is 100uA. When the avalanche phenomenon occurs, a large current with a mA level is generated and is far larger than the avalanche threshold current of 100uA; when the quenching operation is completed, the current of the SPAD avalanche branch is less than 100uA, which indicates that the quenching is completed. In order to ensure that the SPAD detects and quenches the avalanche phenomenon after completely entering the geiger mode, the avalanche threshold current Iref is set to be larger than 100uA, but in order to improve the detection rate, the avalanche threshold current Iref is set to be much smaller than the peak current, and the current of 200uA is selected as the avalanche threshold current Iref by comprehensively considering two factors.

Further, the current comparator comprises a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13 and a third inverter INV3; the eleventh MOS transistor M11 and the twelfth MOS transistor M12 are both N-type MOS transistors, and the tenth MOS transistor M10 and the thirteenth MOS transistor M13 are both P-type MOS transistors.

The drain electrode of the eleventh MOS transistor M11 and the source electrode of the thirteenth MOS transistor M13 are connected with a power supply voltage; the drain of the tenth MOS transistor M10 and the source of the twelfth MOS transistor M12 are grounded.

The source of the eleventh MOS transistor M11 is connected to the source of the tenth MOS transistor M10, and is used as the input end of the current comparator, and the input current signal Iin is the difference between the avalanche branch current Ispad copied by the current mirror structure and the avalanche threshold current Iref. The gate of the eleventh MOS transistor M11 is also connected to the input terminal of the third inverter INV3.

The grid electrode of the thirteenth MOS tube M13 is connected with the grid electrode of the twelfth MOS tube M12 and is connected with the input end of the current comparator; the drain of the thirteenth MOS transistor M13 is connected to the drain of the twelfth MOS transistor M12, and is connected to the input end of the third inverter INV3, and the signal Vout of the current comparison result is output to the third inverter INV3.

The third inverter INV3, serving as an output terminal of the current comparator, inverts the received signal Vout to generate the avalanche current signal OUTb, and outputs the avalanche current signal OUTb to the first inverter INV1.

The SPAD quenching circuit based on current comparison specifically comprises the following working procedures:

stage to be tested (part before time t1 in fig. 4): in an initial state, the first MOS tube M1 is cut off, and the single photon avalanche photodiode SPAD is communicated with the second MOS tube M2 and the third MOS tube M3 to form an avalanche branch. The single photon avalanche photodiode SPAD is in a reverse bias state and has no photon triggering, the current in the avalanche branch is extremely small, so the voltage drop of the second MOS tube M2 and the third MOS tube M3 is almost zero, the anode potential of the single photon avalanche photodiode SPAD is at a low level, and the reverse bias of the SPAD is higher than the avalanche breakdown voltage. At this time, the avalanche branch current Ispad and the avalanche threshold current Iref are compared by the current comparator to output a logic level 1.OUTb is at high level, first MOS pipe M1, fifth MOS pipe M5 cut off, and second MOS pipe M2 switches on and constitutes the low resistance path, and the circuit is in the steady state of waiting for photon detection.

Avalanche phase (in fig. 4, the part between times t1-t 2): when photons enter the single photon avalanche photodiode SPAD, avalanche is instantly triggered, the currents in the branches of the single photon avalanche photodiode SPAD, the second MOS tube M2 and the third MOS tube M3 are rapidly increased, the anode potential of the single photon avalanche photodiode SPAD is increased, and the current of the avalanche branch is compared with avalanche threshold current through a current comparator and then outputs a logic level 0 after being mirrored by a current mirror structure consisting of the third MOS tube M3 and the fourth MOS tube M4. OUTb is in low level, the second MOS tube M2 is cut off to form a high-resistance path, and the current mirror of the avalanche branch is cut off, so that the anode potential of the single photon avalanche photodiode SPAD is increased; meanwhile, the fifth MOS tube M5 is conducted, so that the anode potential of the single photon avalanche photodiode SPAD is pulled up to a high level VDD, and the rising of the anode voltage of the single photon avalanche photodiode SPAD is further accelerated. At the moment, the reverse bias voltage at the two ends of the single photon avalanche photodiode SPAD is reduced to be lower than the avalanche breakdown voltage more quickly, the avalanche self-sustaining effect is stopped, the current in the circuit is reduced rapidly, and the purpose of rapid quenching is achieved.

Reset phase (in fig. 4, the part between times t2-t 4): after quenching is finished, the avalanche current pulse signal OUTb outputs a reset signal REC (in fig. 4, time point t 3) through the first inverter INV1 and a delay holding circuit, the first MOS transistor M1 of the reset transistor is turned on, the potential at the anode of the single photon avalanche photodiode SPAD is rapidly pulled down to a low level (in fig. 4, time point t 4), the fourth MOS transistor M4 is turned off, the current comparator outputs a logic level 1, so that the second MOS transistor M2 is turned on, the avalanche branch of the single photon avalanche photodiode SPAD is turned on, the reverse bias voltage of the single photon avalanche photodiode SPAD is greater than the breakdown voltage, the state is reset to be in work again, and next photon triggering is waited.

Further, the delay hold circuit delays the reset signal REC by the quenching time, and waits for complete quenching before resetting. Complete quenching is ensured through a delay holding circuit, so that the phenomenon of pulse after the influence on the imaging precision of a single photon avalanche photodiode SPAD detector is overcome.

In summary, compared with the common resistance sensing quenching circuit, the current mirror is used for sensing the avalanche current, the current comparison is used for detecting the avalanche current signal, and the avalanche current signal is processed by the inverter and then the pulse signal is output. The structure effectively accelerates the response speed of single photon detection and shortens the quenching time, thereby reducing the charge quantity of the single photon avalanche photodiode SPAD. The delay holding circuit with adjustable time is adopted, the probability of generating non-ideal factors such as rear pulse and the like is reduced according to the characteristics of different single photon avalanche photodiodes SPAD, the circuit flexibility is increased, and the circuit is more reliable. The quenching and resetting speed of the invention is fast, and the quenching and resetting of the single photon avalanche photodiode can be realized within a few nanoseconds. The problem that the quenching reset time is long due to the low avalanche current response speed of a traditional single-photon detector quenching circuit, and therefore single-photon detection efficiency is low is effectively solved.

Drawings

FIG. 1 is a circuit diagram of the present invention;

FIG. 2 is a circuit diagram of a delay hold circuit of an embodiment;

FIG. 3 is a circuit diagram of a current comparator of an embodiment;

FIG. 4 is a waveform illustrating the operation of the present invention;

FIG. 5 is a diagram showing simulation results of the embodiment.

Detailed Description

The technical solution of the present invention will be described in detail below with reference to the embodiments and the accompanying drawings.

The invention provides a SPAD quenching circuit based on current comparison, which comprises a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a delay holding circuit and a current comparator as shown in figure 1, wherein the first MOS tube M1, the second MOS tube M2, the third MOS tube M3 and the fourth MOS tube M4 are N-type MOS tubes, the fifth MOS tube M5 is a P-type MOS tube, the drains of the first MOS tube M1, the second MOS tube M2 and the fifth MOS tube M5, the gates of the third MOS tube M3 and the fourth MOS tube M4 are all connected with the anode of a single-photon avalanche photodiode SPAD, the source electrodes of the first MOS tube M1, the third MOS tube M3 and the fourth MOS tube M4 are all grounded GND, the source electrode of the fifth MOS tube M5 is all connected with an external voltage VDD, the source electrode of the second MOS tube M2 is connected with the drain electrode of the third MOS tube, the grid electrode of the second MOS tube M2 is connected with the output end of the current comparator, the input end of the current comparator is connected with the drain electrode of the fourth MOS tube M4, the grid electrode of the first MOS tube M1 is connected with the output end of the delay holding circuit, the signal input end of the delay holding circuit is connected with the output end of the first phase inverter, and the input end of the first phase inverter is connected with the output end of the current comparator.

The current of the single photon avalanche photodiode SPAD is a current mirror image current consisting of a third MOS tube M3 and a fourth MOS tube M4, and then is compared with an avalanche threshold current Iref through a current comparator to output a logic level of 0.

The OUTb is at a low level, the second MOS tube M2 is cut off, and the fifth MOS tube M5 is conducted, so that the potential at the anode point of the single photon avalanche photodiode SPAD is pulled up to a high level, the reverse bias voltage at two ends of the single photon avalanche photodiode SPAD can be reduced to be below the avalanche breakdown voltage more quickly, the avalanche self-sustaining effect of the single photon avalanche photodiode SPAD is stopped, and the purpose of avalanche current quenching is achieved.

Meanwhile, after the avalanche current pulse signal OUTb output by the over-current comparator is inverted through the first inverter INV1, the delay holding circuit delays the time and outputs a reset signal REC, so that the first MOS tube M1 serving as a reset tube is conducted, the potential at the anode point of the single-photon avalanche photodiode SPAD is quickly pulled down to the ground, the reverse bias voltage at the two ends of the single-photon avalanche photodiode SPAD is greater than the avalanche breakdown voltage, the working state is recovered, and the next single-photon triggering is waited.

As shown in fig. 2, the delay holding circuit of the reset signal REC of this embodiment includes a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, and a second inverter INV2; the sixth MOS transistor M6, the seventh MOS transistor M7, and the ninth MOS transistor M9 are N-type MOS transistors, the eighth MOS transistor M8 is a P-type MOS transistor, a drain of the eighth MOS transistor M8 is connected to a source of the seventh MOS transistor, a drain of the seventh MOS transistor M7 and a drain of the sixth MOS transistor M6 are connected to a gate of the ninth MOS transistor M9, a gate of the ninth MOS transistor M9 is connected to an input terminal of the second inverter INV2, and an output terminal of the second inverter INV2 serves as an output terminal of the delay holding unit; the source of the eighth MOS transistor M8 is connected to the power voltage VDD, the source of the sixth MOS transistor M6 and the drain and source of the ninth MOS transistor M9 are all grounded, the gate of the eighth MOS transistor M8 is connected to the external control voltage Vctrl, wherein the ninth MOS transistor M9 is used as the MOS capacitor C1.

With the change adjustment of the control voltage Vctrl, the time delay adjustment can be realized aiming at the characteristics of different SPADs. The range of the control voltage Vctrl is within (0, vdd), and the larger the voltage is, the smaller the drain current of the eighth MOS transistor M8 is, so that the slower the charging speed of the capacitor C1 is, resulting in the longer delay time. In the delay holding circuit, the MOS capacitor C1 formed by the ninth MOS transistor M9 is charged by the drain currents of the seventh MOS transistor M7 and the eighth MOS transistor M8, and since the gate voltage Vctrl of the eighth MOS transistor M8 is adjustable, the charging time of the MOS capacitor C1 is adjustable.

When an avalanche signal is detected, the gate voltage Vcap of the MOS capacitor C1 starts to be slowly charged until the gate voltage Vcap exceeds the threshold voltage of the second inverter INV2, the output of the INV2 is inverted, a reset signal REC is output, the first MOS tube M1 is switched on, the anode potential of the single photon avalanche photodiode SPAD is pulled to the ground through the first MOS tube M1, the fourth MOS tube M4 is switched off, the current comparator outputs a logic level '1', the second MOS tube M2 is switched on, an avalanche branch of the single photon avalanche photodiode SPAD is switched on, the reverse bias voltage at two ends of the single photon avalanche photodiode SPAD is larger than the avalanche breakdown voltage, the reset avalanche of the single photon photodiode SPAD is completed at the moment, the working state is recovered, and the next triggering of a single photon is waited.

The current comparator of the present embodiment compares the branch current with the avalanche threshold current, as shown in fig. 3: the MOS transistor comprises a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, a third inverter INV3 and a fourth inverter INV4; the eleventh MOS transistor M11 and the twelfth MOS transistor M12 are N-type MOS transistors. A tenth MOS transistor M10 and a thirteenth MOS transistor M13 are P-type MOS transistors, a source of the eleventh MOS transistor M11 is connected to a source of the tenth MOS transistor M10 and serves as an input end of the current comparator, a gate of the thirteenth MOS transistor M13 is connected to a gate of the twelfth MOS transistor M12 and is connected to the input end of the current comparator, and a drain of the thirteenth MOS transistor M13 is connected to a drain of the twelfth MOS transistor M12 and is connected to an input end of the third inverter INV3; the drain of the eleventh MOS transistor M11 and the source of the thirteenth MOS transistor M13 are connected to the power voltage VDD, and the drain of the tenth MOS transistor M10 and the source of the twelfth MOS transistor M12 are grounded.

In fig. 3, iin represents the difference between the avalanche branch current Ispad and the avalanche threshold current Iref of the single photon avalanche photodiode SPAD as the input of the current comparator, iin is a current value >0 or <0, the current comparator processes Iin and outputs a binary signal representing the current comparison result Vout, in order to increase the amplitude of the output voltage, the input terminal of the third inverter INV3 is connected with the Vout signal, and the output avalanche current pulse signal OUTb of the third inverter INV3;

the tenth MOS transistor M10 and the eleventh MOS transistor M11 are used as a source follower stage for current-voltage conversion as the input end of the current comparator, and the twelfth MOS transistor M12 and the thirteenth MOS transistor M13 are used as a CMOS complementary amplifier for negative feedback as the output end, and when the input current signal Iin changes, the negative feedback can suppress the change of the input end voltage, so that the current comparator has smaller input and output impedances, and has shorter response time compared with the conventional current comparator based on the cascode current mirror structure.

When a photon arrives, the single photon avalanche photodiode SPAD generates an avalanche current Ispad, and the current is copied through a current mirror and compared with an avalanche threshold current Iref. When Ispad is larger than Iref, iin is smaller than 0, the output signal OUTb of the current comparator is at low level, the fifth MOS tube M5 is conducted, and the second MOS tube M2 is cut off, so that the anode potential of the single photon avalanche photodiode SPAD is pulled up to high level, and the purpose of quenching is achieved.

The working principle of the present invention is explained below with reference to fig. 1 and 4.

1. Stage to be tested (part before time t1 in fig. 4): in an initial state, the first MOS tube M1 is cut off, and the single photon avalanche photodiode SPAD is communicated with the second MOS tube M2 and the third MOS tube M3 to form an avalanche branch. The single photon avalanche photodiode SPAD is in a reverse bias state and has no photon triggering, the current in the avalanche branch is extremely small, so the voltage drop of the second MOS tube M2 and the third MOS tube M3 is almost zero, the anode potential of the single photon avalanche photodiode SPAD is in a low level, and the reverse bias of the SPAD is higher than the avalanche breakdown voltage. At this time, the avalanche branch current Ispad and the avalanche threshold current Iref are compared by the current comparator, and then a logic level "1" is output. OUTb is at high level, the first MOS transistor M1 and the fifth MOS transistor M5 are cut off, the second MOS transistor M2 is conducted to form a low-resistance path, and the circuit is in a stable state for waiting photon detection.

2. Avalanche phase (in fig. 4, the part between times t1-t 2): when photons enter the single photon avalanche photodiode SPAD, avalanche is instantly triggered, the currents in the branches of the single photon avalanche photodiode SPAD and the second MOS tube M2 and the third MOS tube M3 are rapidly increased, the anode potential of the single photon avalanche photodiode SPAD rises, and the current of the avalanche branch is compared with avalanche threshold current through a current comparator after being mirrored by a current mirror consisting of the third MOS tube M3 and the fourth MOS tube M4, and then a logic level '0' is output. OUTb is at low level, the second MOS tube M2 is cut off to form a high-resistance path, and a current mirror of an avalanche branch is cut off, so that the anode potential of a single-photon avalanche photodiode SPAD is increased; meanwhile, the fifth MOS tube M5 is conducted, so that the anode potential of the single photon avalanche photodiode SPAD is pulled up to a high level VDD, and the rising of the anode voltage of the single photon avalanche photodiode SPAD is further accelerated.

At the moment, the reverse bias voltage at the two ends of the single photon avalanche photodiode SPAD is reduced to be lower than the avalanche breakdown voltage more quickly, the avalanche self-sustaining effect is stopped, the current in the circuit is reduced rapidly, and the purpose of rapid quenching is achieved.

3. Reset phase (in fig. 4, the part between times t2-t 4): after quenching is finished, the avalanche current pulse signal OUTb outputs a reset signal REC (in fig. 4, time point t 3) through the first inverter INV1 and a delay holding circuit, the first MOS transistor M1 of the reset transistor is turned on, the potential at the anode of the single photon avalanche photodiode SPAD is rapidly pulled down to a low level (in fig. 4, time point t 4), the fourth MOS transistor M4 is turned off, the current comparator outputs a logic level "1", so that the second MOS transistor M2 is turned on, the avalanche branch of the avalanche single photon photodiode SPAD is turned on, the reverse bias voltage of the single photon avalanche photodiode SPAD is greater than the breakdown voltage, and the avalanche photodiode SPAD is reset to a standby state again to wait for next photon triggering.

Since the post-pulse phenomenon affects the imaging accuracy of the single-photon avalanche photodiode SPAD detector, in order to prevent incomplete quenching, the reset signal REC is delayed to the quenching time by the delay holding circuit, and reset is performed after complete quenching.

The SPAD quenching circuit based on current comparison is used as a dynamic bias circuit of the SPAD, the quenching and resetting speed is high, and the quenching and resetting of the SPAD of the single-photon avalanche photodiode can be realized within a few nanoseconds. The simulation of the quenching effect is shown in fig. 5, wherein vphot represents the analog single-photon signal from top to bottom in fig. 5, and V1 represents the variation graph of the anode voltage, the avalanche current pulse signal OUTb, and the reset signal REC of the single-photon avalanche photodiode, and it can be seen that the time for the reverse bias voltage to reach a value less than the breakdown voltage is about 1.4ns, and the state to be measured is restored to a value greater than the breakdown voltage and 623ps.

Compared with the common resistance induction quenching circuit, the single-photon avalanche photodiode SPAD circuit has the advantages that the avalanche current is induced by the current mirror, the avalanche current signal is detected by current comparison, the pulse signal is output after the avalanche current signal is processed by the inverter, the response speed of single-photon detection is effectively increased, the quenching time is shortened, and the quantity of charges of the single-photon avalanche photodiode SPAD is reduced. And a delay holding circuit with adjustable time is adopted, so that the probability of generating non-ideal factors such as rear pulse and the like is reduced, the circuit flexibility is increased and the circuit is more reliable according to the characteristics of different single photon avalanche photodiodes SPAD. The quenching and resetting speed of the invention is fast, and the quenching and resetting of the single photon avalanche photodiode can be realized within a few nanoseconds. The problem that the quenching reset time is long due to the low avalanche current response speed of a traditional single-photon detector quenching circuit, and therefore single-photon detection efficiency is low is effectively solved. According to the invention, the avalanche current is induced in the quenching process in a current induction mode, and the avalanche current signal is detected through current comparison, so that the response speed of single photon detection is effectively improved, the dead time is reduced, and the single photon detection efficiency is improved.

Claims

1. A SPAD quenching circuit based on current comparison is characterized in that: the single-photon avalanche photodiode comprises a single-photon avalanche photodiode SPAD, a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a first inverter INV1, a delay holding circuit and a current comparator; the first MOS transistor M1, the second MOS transistor, the third MOS transistor and the fourth MOS transistor are all N-type MOS transistors; the fifth MOS tube is a P-type MOS tube;

the first MOS tube M1 is used as a reset tube, the grid electrode of the first MOS tube M1 is connected with the output end of the delay holding circuit, the drain electrode of the first MOS tube M1 is connected with the anode of the single photon avalanche photodiode SPAD, the drain electrodes of the second MOS tube M2 and the fifth MOS tube M5, the grid electrodes of the third MOS tube M3 and the fourth MOS tube M4, and the source electrode of the first MOS tube M1 is grounded;

when the first MOS tube M1 receives a reset signal REC output by the delay holding circuit, the first MOS tube is conducted, and the potential at the anode point of the single photon avalanche photodiode SPAD is pulled down to the ground, so that the reverse bias voltage at the two ends of the single photon avalanche photodiode SPAD is greater than the avalanche breakdown voltage, the single photon avalanche photodiode SPAD is restored to a working state, and the next single photon triggering is waited;

the grid electrode of the second MOS tube M2 is interconnected with the grid electrode of the fifth MOS tube M5 and is connected to the output end of the current comparator, and the source electrode of the second MOS tube M2 is connected with the drain electrode of the third MOS tube M3; the source electrode of the fifth MOS tube M5 is connected with the power supply voltage VDD;

the source electrodes of the third MOS tube M3 and the fourth MOS tube M4 are grounded; the third MOS tube M3 and the fourth MOS tube M4 form a current mirror structure and are used for copying a current Ispad generated by an avalanche branch of the single photon avalanche photodiode SPAD; the drain electrode of the fourth MOS tube M4 connects the copied current Ispad with the external avalanche threshold current Iref to make a difference, and outputs a current signal Iin to the input end of the current comparator;

the input end of the first inverter INV1 is connected with the output end of the current comparator, and the output end of the first inverter INV1 is connected with the input end of the delay holding circuit; the first inverter INV1 inverts the avalanche current pulse signal OUTb as an input signal of the delay holding circuit;

the cathode voltage of the single photon avalanche photodiode SPAD is the sum of the avalanche breakdown voltage Vpeak of the single photon avalanche photodiode SPAD and the power supply voltage VDD, so that the reverse bias voltage of the single photon avalanche photodiode SPAD in the working state is larger than the avalanche breakdown voltage;

the input of the current comparator is connected with the drain electrode of the fourth MOS transistor M4 and avalanche threshold current Iref input from the outside; the avalanche branch circuit is used for detecting an avalanche signal, when an avalanche branch current Ispad of the single photon avalanche photodiode SPAD is generated, the avalanche branch current Ispad is compared with an avalanche threshold current Iref, and an avalanche current pulse signal OUTb is output to the gates of the first inverter INV1 and the fifth MOS tube M5;

the delay holding circuit is used for generating a reset signal REC of the single photon avalanche photodiode SPAD quenching circuit, resetting the reverse bias voltage of the single photon avalanche photodiode SPAD to be above avalanche breakdown voltage, recovering a state to be worked and waiting for the next detection of an avalanche signal;

before photons arrive, the single photon avalanche photodiode SPAD has no photon trigger, at the moment, the avalanche current Ispad is copied through a current mirror structure and is compared with the avalanche threshold current Iref, the Ispad is not more than Iref, iin is not less than 0, the output signal OUTb of the current comparator is at a high level, the first MOS tube M1 and the fifth MOS tube M5 are cut off, the second MOS tube M2 is conducted to form a low-resistance path, so that the anode potential of the single photon avalanche photodiode SPAD is at a low level, the reverse bias voltage at two ends of the single photon avalanche photodiode SPAD is greater than avalanche breakdown voltage Vbreak, and the circuit is in a stable state to be subjected to photon detection;

when photons arrive, the single photon avalanche photodiode SPAD generates avalanche current Ispad, and the avalanche current Ispad is copied through the current mirror structure and compared with avalanche threshold current Iref; ispad is larger than Iref, iin is smaller than 0, the output signal OUTb of the current comparator is low level, the fifth MOS tube M5 is conducted, the second MOS tube M2 is cut off, so that the anode potential of the single photon avalanche photodiode SPAD is pulled up to high level, the reverse bias voltage at two ends of the single photon avalanche photodiode SPAD is reduced to be lower than avalanche breakdown voltage, the avalanche self-holding effect of the single photon avalanche photodiode SPAD is stopped, and the purpose of quenching is achieved;

meanwhile, after an avalanche current pulse signal OUTb output by the over-current comparator is inverted through a first inverter INV1, a delay holding circuit delays time and outputs a reset signal REC, so that a first MOS tube M1 serving as a reset tube is conducted, the potential at the anode point of a single-photon avalanche photodiode SPAD is pulled down to the ground, the reverse bias voltage at the two ends of the single-photon avalanche photodiode SPAD is larger than avalanche breakdown voltage, the working state is recovered, and the next single photon triggering is waited.

2. The SPAD quench circuit based on current comparison of claim 1, wherein:

the delay holding circuit comprises a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, a ninth MOS tube M9 and a second inverter INV2; the sixth MOS transistor M6, the seventh MOS transistor M7 and the ninth MOS transistor M9 are all N-type MOS transistors, and the eighth MOS transistor M8 is a P-type MOS transistor;

the source electrode of the sixth MOS transistor M6 and the drain electrode and the source electrode of the ninth MOS transistor M9 are grounded, and the ninth MOS transistor M9 is used as an MOS capacitor C1;

the drain electrode of the eighth MOS tube M8 is connected with the source electrode of the seventh MOS tube M7, the source electrode of the eighth MOS tube M8 is connected with a power voltage, the grid electrode of the eighth MOS tube M8 is connected with an external control voltage, and the control voltage is used for regulating and controlling the delay time of the delay holding circuit;

3. The SPAD quench circuit based on current comparison of claim 1, wherein: the avalanche threshold current Iref =200uA.

4. The SPAD quench circuit based on current comparison of claim 1, wherein:

the current comparator comprises a tenth MOS tube M10, an eleventh MOS tube M11, a twelfth MOS tube M12, a thirteenth MOS tube M13 and a third inverter INV3; the eleventh MOS transistor M11 and the twelfth MOS transistor M12 are both N-type MOS transistors, and the tenth MOS transistor M10 and the thirteenth MOS transistor M13 are both P-type MOS transistors;

the drain electrode of the eleventh MOS tube M11 and the source electrode of the thirteenth MOS tube M13 are connected with the power voltage, and the drain electrode of the tenth MOS tube M10 and the source electrode of the twelfth MOS tube M12 are grounded;

the source of the eleventh MOS transistor M11 is connected to the source of the tenth MOS transistor M10, and is used as the input end of the current comparator, the input current signal Iin is the difference between the avalanche branch current Ispad copied by the current mirror structure and the avalanche threshold current Iref, and the gate of the eleventh MOS transistor M11 is also connected to the input end of the third inverter INV3;

the grid electrode of the thirteenth MOS tube M13 is connected with the grid electrode of the twelfth MOS tube M12 and is connected with the input end of the current comparator; the drain of the thirteenth MOS transistor M13 is connected to the drain of the twelfth MOS transistor M12, and is connected to the input end of the third inverter INV3, and the signal Vout of the current comparison result is output to the third inverter INV3;

the third inverter INV3, serving as an output terminal of the current comparator, inverts the received signal Vout, generates the avalanche current signal OUTb, and outputs the avalanche current signal OUTb to the first inverter INV1.

5. The SPAD quench circuit based on current comparison of claim 1, wherein the workflow is specifically:

a stage to be detected: in an initial state, the first MOS tube M1 is cut off, and the single-photon avalanche photodiode SPAD is communicated with the second MOS tube M2 and the third MOS tube M3 to form an avalanche branch; the single photon avalanche photodiode SPAD is in a reverse bias state and has no photon trigger, the anode potential of the single photon avalanche photodiode SPAD is in a low level, and the reverse bias voltage of the SPAD is higher than the avalanche breakdown voltage; at this time, the avalanche branch current Ispad and the avalanche threshold current Iref are compared by the current comparator and then output a logic level 1; the avalanche current signal pulse signal OUTb is at a high level, the first MOS transistor M1 and the fifth MOS transistor M5 are cut off, the second MOS transistor M2 is conducted to form a low-resistance path, and the circuit is in a stable state to be subjected to photon detection;

an avalanche stage: when photons enter a single photon avalanche photodiode SPAD, avalanche is instantly triggered, currents in branches of the single photon avalanche photodiode SPAD, a second MOS tube M2 and a third MOS tube M3 are rapidly increased, the anode potential of the single photon avalanche photodiode SPAD rises, and the current of an avalanche branch is compared with avalanche threshold current through a current comparator after being mirrored through a current mirror structure consisting of the third MOS tube M3 and a fourth MOS tube M4 and then outputs a logic level 0; the avalanche current signal pulse signal OUTb is at a low level, the second MOS tube M2 is cut off to form a high-resistance path, and a current mirror image of an avalanche branch is cut off, so that the anode potential of a single-photon avalanche photodiode SPAD is increased; meanwhile, the fifth MOS tube M5 is conducted, so that the anode potential of the single photon avalanche photodiode SPAD is pulled up to a high level VDD, and the rising of the anode voltage of the single photon avalanche photodiode SPAD is further accelerated; at the moment, the reverse bias voltage at two ends of the single photon avalanche photodiode SPAD is reduced to be lower than the avalanche breakdown voltage, the avalanche self-sustaining effect is stopped, the current in the circuit is reduced, and the purpose of quenching is achieved;

a reset stage: after quenching is finished, the avalanche current pulse signal OUTb passes through the first inverter INV1 and the reset signal REC, the first MOS tube M1 of the reset tube is opened, the potential at the anode of the single photon avalanche photodiode SPAD is pulled down to a low level, the fourth MOS tube M4 is cut off, the current comparator outputs a logic level 1, so that the second MOS tube M2 is conducted, the avalanche branch of the single photon avalanche photodiode SPAD is conducted, the reverse bias voltage of the single photon avalanche photodiode SPAD is greater than the breakdown voltage, the work state is reset again, and next photon triggering is waited.

6. The SPAD quench circuit based on current comparison of claim 1, wherein: the delay hold circuit delays the reset signal REC by the quenching time, and resets after waiting for complete quenching.