CN102437836A - Low-power-consumption short pulse generation circuit and low-power-consumption pulse type D trigger - Google Patents
Low-power-consumption short pulse generation circuit and low-power-consumption pulse type D trigger Download PDFInfo
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Abstract
The invention discloses a low-power-consumption short pulse generation circuit and a low-power-consumption pulse type D trigger. The low-power-consumption short pulse generation circuit is characterized by comprising a first P-channel metal oxide semiconductor field effect transistor (PMOSFET), a first N-channel MOSFET (NMOSFET), a first NAND gate and a first phase inverter. The low-power-consumption pulse type D trigger is characterized by comprising the low-power-consumption short pulse generation circuit, an input phase inversion circuit, a clock control complementary MOS (CMOS) logic D latch unit and an output phase inversion circuit. The invention has the advantages that: under the condition of no influence of the performance of the circuit, the quantity of the transistors of the circuit is small; the structure is simpler; and the power consumption of the circuit is effectively reduced.
Description
Technical field
The present invention relates to a kind of short pulse and produce circuit, especially relate to a kind of low-power consumption short pulse and produce circuit and low-power consumption impulse type d type flip flop.
Background technology
In recent decades, portable electric appts is increasingly extensive in the application in fields such as consumer electronics, medical supply and industrial instrumentation, and integrated circuit has obtained develop rapidly as the core in the portable electric appts.In the IC design, the operating rate of chip and area were designer's main factor in the past, and power problems often is left in the basket.Along with the continuous development of semiconductor manufacturing industry, when the integration density of circuit and operating frequency improved gradually, the dynamic power consumption of chip also (was seen document Malay Ranjan Tripathy continuous the increase with the leakage power consumption; " Nano CMOS "; Journal of Scientific Review, vol.1, no.1; Pp.19-23,2009.).The integrated circuit technology characteristic size has got into nanoscale after the epoch, and power problems is serious day by day, becomes the bottleneck that integrated circuit continues development.
At present, short pulse generation circuit engineering is widely used in impulse type trigger and each adhesive integrated circuit.Fig. 1 produces circuit diagram for short pulse.Shinichi Kozu; The short pulse that Masayuki Daito, people such as Yukinori Suglyama have proposed a kind of and door produces circuit, is high level through making two input clock signals with door in a short period of time simultaneously with complementary clock signal; Thereby generation short pulse signal; With a plurality of inverters of gate output terminal cascade,, the quantity of circuit transistor and the power consumption of circuit have also been increased though can obtain enough complementary clock signals of time-delay.As shown in Figure 2; This short pulse produce circuit by a PMOS manage, NMOS pipe, one with and two inverters form; Wherein said and door is made up of a NAND gate and an inverter, and described NAND gate is made up of two PMOS pipes and two NMOS pipes, and described two PMOS pipe and two NMOS manage the transistor that is minimum channel length under the standard technology; But the short pulse that is based on the NAND gate of this structure produces circuit need be through using a plurality of inverters; Produce the short pulse signal of enough pulsewidths, the increase of inverter causes the increase of circuit transistor quantity, thereby causes the increase of circuit power consumption.
Summary of the invention
Technical problem to be solved by this invention provides a kind of under the situation that does not influence circuit performance, and the low-power consumption short pulse that effectively reduces circuit power consumption produces circuit and low-power consumption impulse type d type flip flop.
The present invention solves the problems of the technologies described above the technical scheme that is adopted: a kind of low-power consumption short pulse produces circuit; Comprise PMOS pipe, NMOS pipe, first NAND gate and first inverter; The source electrode of described PMOS pipe is connected with power positive end; The drain electrode three of the drain electrode of first signal input part of described first NAND gate, described PMOS pipe and described NMOS pipe is connected; The secondary signal input of described first NAND gate is connected with the grid of described PMOS pipe; The source ground of described NMOS pipe; The signal input part of the signal output part of described first NAND gate, described first inverter and complementary pulse signal output end three are connected, and the grid and the described pulse signal output end three of the signal output part of described first inverter, described NMOS pipe are connected, and the grid of described PMOS pipe is connected with clock signal.
Described first NAND gate by the 2nd PMOS manage, the 3rd PMOS pipe, the 2nd NMOS pipe and the 3rd NMOS pipe form; The source electrode of the source electrode of described the 2nd PMOS pipe, described the 3rd PMOS pipe all is connected with power positive end; The drain electrode and the described complementary pulse signal output end of the drain electrode of the drain electrode of described the 2nd PMOS pipe, described the 3rd PMOS pipe, described the 2nd NMOS pipe are connected; The source electrode of described the 2nd NMOS pipe is connected with the drain electrode of described the 3rd NMOS pipe; The source ground of described the 3rd NMOS pipe; The grid of the grid of described the 3rd PMOS pipe, described the 3rd NMOS pipe is first signal input part of described first NAND gate; The drain electrode of the drain electrode of the grid of the grid of described the 3rd PMOS pipe, described the 3rd NMOS pipe, described PMOS pipe and described NMOS pipe is connected; The grid of the grid of described the 2nd PMOS pipe, described the 2nd NMOS pipe is the secondary signal input of described first NAND gate; The grid of the grid of the grid of described the 2nd PMOS pipe, described the 2nd NMOS pipe and described PMOS pipe all is connected with clock signal, and the channel length that channel length that the channel length of described the 2nd PMOS pipe, the channel length of described the 3rd PMOS pipe, described the 2nd NMOS manage and described the 3rd NMOS manage is 1.15～1.4 times of minimum channel length under the standard technology.
A kind of low-power consumption impulse type d type flip flop; Comprise that the low-power consumption short pulse produces circuit, input inversion circuit, clock CMOS logic D-latch unit and output negative circuit; The complementary pulse signal output end that described low-power consumption short pulse produces circuit is connected with the complementary pulse signal input terminal of described clock CMOS logic D-latch unit; The pulse signal output end that described low-power consumption short pulse produces circuit is connected with the pulse signal input terminal of described clock CMOS logic D-latch unit; The signal output part of described input inversion circuit is connected with the reset signal input of described clock CMOS logic D-latch unit, and the signal output part of described clock CMOS logic D-latch unit is connected with the signal input part of described output negative circuit.
Described low-power consumption short pulse produces circuit and comprises PMOS pipe, NMOS pipe, first NAND gate and first inverter; The source electrode of described PMOS pipe is connected with power positive end; The drain electrode three of the drain electrode of first signal input part of described first NAND gate, described PMOS pipe and described NMOS pipe is connected; The secondary signal input of described first NAND gate is connected with the grid of described PMOS pipe; The source ground of described NMOS pipe; The complementary pulse signal output end three that the signal input part of the signal output part of described first NAND gate, described first inverter and described low-power consumption short pulse produce circuit is connected; The pulse signal output end three that the grid of the signal output part of described first inverter, described NMOS pipe and described low-power consumption short pulse produce circuit is connected, and the grid of described PMOS pipe is connected with clock signal.
Described first NAND gate by the 2nd PMOS manage, the 3rd PMOS pipe, the 2nd NMOS pipe and the 3rd NMOS pipe form; The source electrode of the source electrode of described the 2nd PMOS pipe, described the 3rd PMOS pipe all is connected with power positive end; The complementary pulse signal output end that the drain electrode of the drain electrode of the drain electrode of described the 2nd PMOS pipe, described the 3rd PMOS pipe, described the 2nd NMOS pipe and described low-power consumption short pulse produce circuit is connected; The source electrode of described the 2nd NMOS pipe is connected with the drain electrode of described the 3rd NMOS pipe; The source ground of described the 3rd NMOS pipe; The grid of the grid of described the 3rd PMOS pipe, described the 3rd NMOS pipe is first signal input part of described first NAND gate; The drain electrode of the drain electrode of the grid of the grid of described the 3rd PMOS pipe, described the 3rd NMOS pipe, described PMOS pipe and described NMOS pipe is connected; The grid of the grid of described the 2nd PMOS pipe, described the 2nd NMOS pipe is the secondary signal input of described first NAND gate; The grid of the grid of the grid of described the 2nd PMOS pipe, described the 2nd NMOS pipe and described PMOS pipe all is connected with clock signal, and the channel length that channel length that the channel length of described the 2nd PMOS pipe, the channel length of described the 3rd PMOS pipe, described the 2nd NMOS manage and described the 3rd NMOS manage is 1.15～1.4 times of minimum channel length under the standard technology.
Described input inversion circuit comprises second inverter; The signal output part of described second inverter is the signal output part of described input inversion circuit; The signal output part of described second inverter is connected with the reset signal input of described clock CMOS logic D-latch unit, and the signal input part of described second inverter is connected with reset signal.
Described clock CMOS logic D-latch unit comprises input clock inverter module, the first inclusive NAND door and feedback clock inverter module; Described input clock inverter module comprises the 4th PMOS pipe, the 5th PMOS pipe, the 4th NMOS pipe and the 5th NMOS pipe; The described first inclusive NAND door comprise first or the door and second NAND gate; Described feedback clock inverter module comprises the 6th PMOS pipe, the 7th PMOS pipe, the 6th NMOS pipe and the 7th NMOS pipe; Described first or the door first signal input part be the reset signal input of described clock CMOS logic D-latch unit; Described first or the door first signal input part be connected with the signal output part of described input inversion circuit; The drain electrode of the drain electrode of the drain electrode of the drain electrode of described the 5th PMOS pipe, described the 7th PMOS pipe, described the 4th NMOS pipe, described the 6th NMOS pipe all with described first or the secondary signal input be connected; Described first or the door signal output part be connected with first signal input part of described second NAND gate; The secondary signal input of described second NAND gate is connected with asserts signal; The signal output part of described second NAND gate is the signal output part of described clock CMOS logic D-latch unit; The signal output part of described second NAND gate is connected with the signal input part of described output negative circuit; The signal output part of described second NAND gate is connected with the grid of described the 6th PMOS pipe and the grid three of described the 7th NMOS pipe; The source electrode of described the 4th PMOS pipe all is connected with power positive end with the source electrode of described the 6th PMOS pipe; The grid of the grid of described the 4th PMOS pipe, described the 5th NMOS pipe all is connected with input data signal; The drain electrode of described the 4th PMOS pipe is connected with the source electrode that described the 5th PMOS manages, and the grid of the grid of described the 5th PMOS pipe, described the 6th NMOS pipe is the complementary pulse signal input terminal of described clock CMOS logic D-latch unit, and the grid of the grid of described the 5th PMOS pipe, described the 6th NMOS pipe all is connected with the complementary pulse signal output end of described low-power consumption short pulse generation circuit; The grid of the grid of described the 4th NMOS pipe, described the 7th PMOS pipe is the pulse signal input terminal of described clock CMOS logic D-latch unit; The grid of the grid of described the 4th NMOS pipe, described the 7th PMOS pipe all is connected with the pulse signal output end of described low-power consumption short pulse generation circuit, and the source electrode of described the 4th NMOS pipe is connected with the drain electrode of described the 5th NMOS pipe, and the drain electrode of described the 6th PMOS pipe is connected with the source electrode of described the 7th PMOS pipe; The source electrode of described the 6th NMOS pipe is connected with the drain electrode of described the 7th NMOS pipe, the source grounding of the source electrode of described the 5th NMOS pipe and described the 7th NMOS pipe.
Described output negative circuit comprises the 3rd inverter, the 4th inverter and the 5th inverter; The signal input part of the signal input part of described the 3rd inverter, described the 5th inverter is connected with the signal input part three of described output negative circuit; The signal output part of described the 3rd inverter is connected with the signal input part of described the 4th inverter; The signal output part of described the 4th inverter is connected with first signal output part, and the signal output part of described the 5th inverter is connected with the secondary signal output.
Compared with prior art, the invention has the advantages that under the situation that does not influence circuit performance, the number of transistors of circuit is few, structure is simpler, has reduced circuit power consumption effectively.
Description of drawings
Fig. 1 short pulse produces circuit diagram;
The short pulse that Fig. 2 is traditional produces circuit structure diagram;
Fig. 3 asynchronous set, the d type flip flop circuit diagram resets;
Fig. 4 traditional based on clock CMOS (C
2MOS) asynchronous set that triggers of logic rising edge, d type flip flop standard cell DFFSRXL circuit structure diagram resets;
Fig. 5 short pulse of the present invention produces circuit structure diagram;
Fig. 6 short pulse of the present invention produces NAND gate structure chart in the circuit;
Fig. 7 impulse type d type flip flop of the present invention circuit structure diagram;
Fig. 8 impulse type d type flip flop of the present invention circuit is based on SMIC130nm standard technology simulation waveform figure;
Fig. 9 impulse type d type flip flop of the present invention circuit is based on PTM 90nm standard technology simulation waveform figure;
Figure 10 impulse type d type flip flop of the present invention circuit is based on PTM 45nm standard technology simulation waveform figure.
Embodiment
Embodiment describes in further detail the present invention below in conjunction with accompanying drawing.
Embodiment one: like Fig. 5 and shown in Figure 6, a kind of low-power consumption short pulse produces circuit, comprises that PMOS pipe P1, a NMOS manage N1, the first NAND gate U1 and the first inverter I1, source electrode and the power positive end V of PMOS pipe P1
DDBe connected; The drain electrode three of the drain electrode of first signal input part of the first NAND gate U1, PMOS pipe P1 and NMOS pipe N1 is connected; The secondary signal input of the first NAND gate U1 is connected with the grid of PMOS pipe P1; The source ground of the one NMOS pipe N1; The signal input part of the signal output part of the first NAND gate U1, the first inverter I1 and complementary pulse signal output end xb three are connected, and grid and the pulse signal output end x three of the signal output part of the first inverter I1, NMOS pipe N1 are connected, and the grid of PMOS pipe P1 is connected with clock signal clk; The first NAND gate U1 is made up of the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the 2nd NMOS pipe N2 and the 3rd NMOS pipe N3, the source electrode that the source electrode of the 2nd PMOS pipe P2, the 3rd PMOS manage P3 all with power positive end V
DDBe connected; Drain electrode and the complementary pulse signal output end xb of the drain electrode of the drain electrode of the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the 2nd NMOS pipe N2 are connected; The source electrode of the 2nd NMOS pipe N2 is connected with the drain electrode of the 3rd NMOS pipe N3; The source ground of the 3rd NMOS pipe N3; The grid of the grid of the 3rd PMOS pipe P3, the 3rd NMOS pipe N3 is first signal input part of the first NAND gate U1; The drain electrode of the drain electrode of the grid of the grid of the 3rd PMOS pipe P3, the 3rd NMOS pipe N3, PMOS pipe P1 and NMOS pipe N1 is connected; The grid of the grid of the 2nd PMOS pipe P2, the 2nd NMOS pipe N2 is the secondary signal input of the first NAND gate U1; The grid of the grid of the grid of the 2nd PMOS pipe P2, the 2nd NMOS pipe N2 and PMOS pipe P1 all is connected with clock signal clk; The substrate of the substrate of the substrate of the one PMOS pipe P1, the 2nd PMOS pipe P2 and the 3rd PMOS pipe P3 all meets power positive end VDD, the substrate of the substrate of NMOS pipe N1, the 2nd NMOS pipe N2 and the equal ground connection of substrate of the 3rd NMOS pipe N3, and the channel length of the channel length of the channel length of the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the channel length of the 2nd NMOS pipe N2 and the 3rd NMOS pipe N3 is 119 times of minimum channel length under the SMIC130nm standard technology.
Embodiment two: other parts are identical with embodiment one, and its difference is: the channel length of the channel length of the channel length of the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the channel length of the 2nd NMOS pipe N2 and the 3rd NMOS pipe N3 is 1.3 times of minimum channel length under the PTM90nm standard technology.
Embodiment three: other parts are identical with embodiment one, and its difference is: the channel length of the channel length of the channel length of the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the channel length of the 2nd NMOS pipe N2 and the 3rd NMOS pipe N3 is 1.4 times of minimum channel length under the PTM45nm standard technology.
The operation principle that low-power consumption short pulse of the present invention produces circuit is following:
When clock signal clk=0, PMOS pipe P1 opens, and PMOS pipe P1 drain charge is to high level, and first NAND gate U1 output signal xb=1 exports signal x=0 through the first inverter I1, and NMOS pipe N1 closes.
When clock signal clk=1, PMOS pipe P1 closes, and PMOS pipe P1 drain electrode is unsettled; Because previous moment the one PMOS pipe P1 drain charge is to high level; First NAND gate U1 output signal xb=0, through the first inverter I1 anti-phase, output signal x=1; The one NMOS pipe N1 opens, and PMOS pipe P1 drain electrode is discharged to low level.First NAND gate U1 output signal xb=1, through the first inverter I1 anti-phase, output signal x=0 has so just realized short pulse signal.
Low-power consumption short pulse of the present invention produces circuit: at first, circuit structure is simple, and the inside circuit node discharges and recharges less, compares with traditional short pulse generation circuit and can reduce total power consumption effectively; Secondly; Traditional short pulse produces in the circuit; Adopt the method that increases the inverter number to produce the enough big short pulse signal of pulsewidth, transistor gate capacitance increases and increases along with channel length, so the channel length modulation technology can cause the increase of circuit delay; The transistor that the short pulse that the present invention proposes produces the first NAND gate U1 in the circuit adopts the channel length modulation technology, compares with traditional circuit and can reduce by 4 transistorized quantity; At last, the short pulse signal pulsewidth increases along with the increase of the transistor channel length of the first NAND gate U1 is linear, has the adjustable characteristics of pulsewidth.
For short pulse more proposed by the invention produces circuit produces circuit with respect to traditional short pulse performance characteristics; Adopt SMIC 130nm, PTM 90nm and PTM 45nm standard technology, wherein the minimum channel length of PMOS pipe and NMOS pipe is respectively 130nm, 90nm and 50nm under SMIC 130nm, PTM 90nm and the PTM 45nm technological standards.Use circuit simulation tools HSPICE that two kinds of circuit structures have been carried out the emulation comparative analysis.Wherein, rising edge 50% overturn point that the pulse duration of short pulse generation circuit is defined as pulse signal x waveform is to trailing edge 50% overturn point, and time-delay is defined as rising edge 50% overturn point of rising edge 50% overturn point of clock signal clk to pulse signal x.
Be respectively low-power consumption short pulse of the present invention shown in table 1, table 2 and the table 3 and produce the performance of circuit under SMIC130nm, PTM90nm and PTM45nm standard technology relatively; Supply voltage is respectively 1.2V, 1.1V and 1.1V in the corresponding electrical circuits emulation; Clock signal clk is 100MHz, 50% duty ratio square-wave signal.
The performance of short pulse generation circuit relatively under the table 1SMIC130nm standard technology
In the table 1: minimum channel length is 130nm, and channel length of the present invention is 155nm, and multiple is 155/130=1.19 times.
The performance of short pulse generation circuit relatively under the table 2PTM 90nm standard technology
In the table 2: minimum channel length is 90nm, and channel length of the present invention is 117nm, and multiple is 117/90=1.3 times.
The performance of short pulse generation circuit relatively under the table 3PTM 45nm standard technology
In the table 3: minimum channel length is 50nm, and channel length of the present invention is 70nm, and multiple is 70/50=1.4 times.
From table 1, calculate and to know; Produce circuit with traditional short pulse and compare, the short pulse generation circuit of proposition under 130nm technology, has saved total power consumption and time-delay is respectively 12.30% and 13.03%, from table 2, calculates and can know; Producing circuit with traditional short pulse compares; The short pulse generation circuit that proposes under 90nm technology, has saved total power consumption and time-delay is respectively 11.89% and 0.88%, from table 3, calculates and can know, produces circuit with traditional short pulse and compares; The short pulse generation circuit that proposes under 45nm technology, has saved total power consumption and time-delay is respectively 13.71% and 0.732%, on power consumption and performance, has greater advantage.
Embodiment four: like Fig. 6 and shown in Figure 7; A kind of low-power consumption impulse type d type flip flop; Comprise that the low-power consumption short pulse produces circuit 1, input inversion circuit 2, clock CMOS logic D-latch unit 3 and output negative circuit 4; The complementary pulse signal output end xb that the low-power consumption short pulse produces circuit 1 is connected with the complementary pulse signal input terminal Xb of clock CMOS logic D-latch unit 3; The pulse signal output end x that the low-power consumption short pulse produces circuit 1 is connected with the pulse signal input terminal X of clock CMOS logic D-latch unit 3; The signal output part of input inversion circuit 2 is connected with the reset signal input R of clock CMOS logic D-latch unit 3, and the signal output part out1 of clock CMOS logic D-latch unit 3 is connected with the signal input part in1 of output negative circuit 4.
The low-power consumption short pulse produces circuit 1 and comprises that PMOS pipe P1, a NMOS manage N1, the first NAND gate U1 and the first inverter I1, source electrode and the power positive end V of PMOS pipe P1
DDBe connected; The drain electrode three of the drain electrode of first signal input part of the first NAND gate U1, PMOS pipe P1 and NMOS pipe N1 is connected; The secondary signal input of the first NAND gate U1 is connected with the grid of PMOS pipe P1; The source ground of the one NMOS pipe N1; The complementary pulse signal output end xb three that the signal input part of the signal output part of the first NAND gate U1, the first inverter I1 and low-power consumption short pulse produce circuit 1 is connected; The pulse signal output end x three that the grid of the signal output part of the first inverter I1, NMOS pipe N1 and low-power consumption short pulse produce circuit 1 is connected, and the grid of PMOS pipe P1 is connected with clock signal clk.
The first NAND gate U1 is made up of the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the 2nd NMOS pipe N2 and the 3rd NMOS pipe N3, the source electrode that the source electrode of the 2nd PMOS pipe P2, the 3rd PMOS manage P3 all with power positive end V
DDBe connected; The complementary pulse signal output end xb that the drain electrode of the drain electrode of the drain electrode of the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the 2nd NMOS pipe N2 and low-power consumption short pulse produce circuit 1 is connected; The source electrode of the 2nd NMOS pipe N2 is connected with the drain electrode of the 3rd NMOS pipe N3; The source ground of the 3rd NMOS pipe N3; The grid of the grid of the 3rd PMOS pipe P3, the 3rd NMOS pipe N3 is first signal input part of the first NAND gate U1; The drain electrode of the drain electrode of the grid of the grid of the 3rd PMOS pipe P3, the 3rd NMOS pipe N3, PMOS pipe P1 and NMOS pipe N1 is connected; The grid of the grid of the 2nd PMOS pipe P2, the 2nd NMOS pipe N2 is the secondary signal input of the first NAND gate U1; The grid of the grid of the grid of the 2nd PMOS pipe P2, the 2nd NMOS pipe N2 and PMOS pipe P1 all is connected with clock signal clk, and the channel length that the channel length of the channel length of the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the channel length that the 2nd NMOS manages N2 and the 3rd NMOS manage N3 is 1.19 times of minimum channel length under the 130nm standard technology.
Input inversion circuit 2 comprises the second inverter I2; The signal output part of the second inverter I2 is the signal output part of input inversion circuit 2; The signal output part of the second inverter I2 is connected with the reset signal input R of clock CMOS logic D-latch unit 3, and the signal input part of the second inverter I2 is connected with reset signal rn.
Clock CMOS logic D-latch unit 3 comprises input clock inverter module, the first inclusive NAND door OAI1 and feedback clock inverter module; Input clock inverter module comprises the 4th PMOS pipe P4, the 5th PMOS pipe P5, the 4th NMOS pipe N4 and the 5th NMOS pipe N5; The first inclusive NAND door OAI1 comprises first or door O1 and the second NAND gate U2; Feedback clock inverter module comprises the 6th PMOS pipe P6, the 7th PMOS pipe P7, the 6th NMOS pipe N6 and the 7th NMOS pipe N7; First or the door O1 first signal input part be the reset signal input R of clock CMOS logic D-latch unit 3; First or the door O1 first signal input part be connected with the signal output part of input inversion circuit 2; The drain electrode of the drain electrode of the drain electrode of the drain electrode of the 5th PMOS pipe P5, the 7th PMOS pipe P7, the 4th NMOS pipe N4, the 6th NMOS pipe N6 all is connected with first or the secondary signal input of an O1; First or the door O1 signal output part be connected with first signal input part of the second NAND gate U2; The secondary signal input of the second NAND gate U2 is connected with asserts signal sn, and the signal output part of the second NAND gate U2 is the signal output part out1 of clock CMOS logic D-latch unit 3, and the signal output part of the second NAND gate U2 is connected with the signal input part in1 of output negative circuit 4; The grid three of the grid of the signal output part of the second NAND gate U2 and the 6th PMOS pipe P6 and the 7th NMOS pipe N7 is connected, the source electrode that the source electrode of the 4th PMOS pipe P4 and the 6th PMOS manage P6 all with power positive end V
DDBe connected; The grid of the grid of the 4th PMOS pipe P4, the 5th NMOS pipe N5 all is connected with input data signal D; The drain electrode of the 4th PMOS pipe P4 is connected with the source electrode of the 5th PMOS pipe P5; The grid of the grid of the 5th PMOS pipe P5, the 6th NMOS pipe N6 is the complementary pulse signal input terminal Xb of clock CMOS logic D-latch unit 3; The grid of the grid of the 5th PMOS pipe P5, the 6th NMOS pipe N6 all is connected with the complementary pulse signal output end xb of low-power consumption short pulse generation circuit 1; The grid of the grid of the 4th NMOS pipe N4, the 7th PMOS pipe P7 is the pulse signal input terminal X of clock CMOS logic D-latch unit 3; The grid of the grid of the 4th NMOS pipe N4, the 7th PMOS pipe P7 all is connected with the pulse signal output end x of low-power consumption short pulse generation circuit 1, and the source electrode of the 4th NMOS pipe N4 is connected with the drain electrode of the 5th NMOS pipe N5, and the drain electrode of the 6th PMOS pipe P6 is connected with the source electrode of the 7th PMOS pipe P7; The source electrode of the 6th NMOS pipe N6 is connected with the drain electrode of the 7th NMOS pipe N7, the source grounding of the source electrode of the 5th NMOS pipe N5 and the 7th NMOS pipe N7.
Output negative circuit 4 comprises the 3rd inverter I3, the 4th inverter I4 and the 5th inverter I5; The signal input part of the signal input part of the 3rd inverter I3, the 5th inverter I5 is connected with the signal input part in1 three of output negative circuit 4; The signal output part of the 3rd inverter I3 is connected with the signal input part of the 4th inverter I4; The signal output part of the 4th inverter I4 is connected with the first signal output part Q; The signal output part of the 5th inverter I5 is connected with secondary signal output Qb; The substrate of the substrate of the substrate of the substrate of the substrate of the substrate of the substrate of the one PMOS pipe P1, the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the 4th PMOS pipe P4, the 5th PMOS pipe P5, the 6th PMOS pipe P6 and the 7th PMOS pipe P7 all meets power positive end VDD, the substrate of the substrate of the substrate of NMOS pipe N1, the 2nd NMOS pipe N2, the substrate of the 3rd NMOS pipe N3, the 4th NMOS pipe N4, the substrate of the 5th NMOS pipe N5, the substrate of the 6th NMOS pipe N6 and the equal ground connection of substrate of the 7th NMOS pipe N7.
Embodiment five: other parts are identical with embodiment four, and its difference is: the channel length of the channel length of the channel length of the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the channel length of the 2nd NMOS pipe N2 and the 3rd NMOS pipe N3 is 1.3 times of minimum channel length under the PTM 90nm standard technology.
Embodiment six: other parts are identical with embodiment four, and its difference is: the channel length of the channel length of the channel length of the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the channel length of the 2nd NMOS pipe N2 and the 3rd NMOS pipe N3 is 1.4 times of minimum channel length under the PTM 45nm standard technology.
The operation principle of low-power consumption impulse type d type flip flop circuit of the present invention is following:
When asserts signal sn=0; Input data signal D, reset signal rn and clock signal clk do not influence the output signal, and the output signal of the first inclusive NAND door OAI1 is a high level, through the 3rd inverter I3 and the 4th inverter I4; Output signal Q charges to high level, realizes the dataset function.
When asserts signal sn=1, reset signal rn=0; Input data signal D and clock signal clk do not influence the output signal, and first inclusive NAND door OAI1 output signal is a low level, through the 3rd inverter I3 and the 4th inverter I4; Output signal Q charges to low level, realizes the data reset function.
When asserts signal sn=1, reset signal rn=1, the first inclusive NAND door OAI1 is equivalent to inverter.When x=0, xb=1; The 4th PMOS pipe P4, the 5th NMOS pipe N5 close; Input clock inverter is equivalent to and ends, and input data signal D is equivalent to shielding outside, and the 7th PMOS pipe P7, the 6th NMOS pipe N6 open; Feedback clock inverter is equivalent to inverter, and the output signal passes through cross coupling inverter to realizing data static latch function.When x=1, xb=0; The 7th PMOS pipe P7, the 6th NMOS pipe N6 close; Feedback clock inverter is equivalent to and ends; The 4th PMOS pipe P4, the 5th NMOS pipe N5 open, and input clock inverter is equivalent to inverter, and input data signal D passes to output signal Q through four inverters and realizes data assignment function.
The asynchronous set that the present invention proposes, the advantage of reset pulse type d type flip flop are: at first, circuit structure is simple, and the inside circuit node discharges and recharges less, compares with traditional asynchronous set, restoration type d type flip flop and can reduce power consumption effectively; Secondly, asynchronous set of the present invention, reset pulse type d type flip flop adopt the short pulse that proposes to produce circuit, compare with conventional trigger device circuit and can reduce by 4 transistorized quantity.
For asynchronous set more proposed by the invention, reset pulse type d type flip flop performance characteristics with respect to traditional asynchronous set, the d type flip flop that resets; We adopt SMIC 130nm, PTM 90nm and PTM 45nm standard technology; Wherein, the minimum channel length of PMOS pipe and NMOS pipe is respectively 130nm, 90nm and 50nm under SMIC 130nm, PTM 90nm and the PTM 45nm standard technology.Use circuit simulation tools HSPICE that two kinds of circuit structures have been carried out the emulation comparative analysis.
Be respectively low-power consumption impulse type d type flip flop of the present invention shown in table 4, table 5 and the table 6, following performance with traditional d type flip flop based on SMIC 130nm, 90nm and 45nm standard technology compares.
Under the table 4SMIC 130nm standard technology, the performance of the present invention and traditional d type flip flop relatively
Under the table 5PTM 90nm standard technology, the performance of the present invention and traditional d type flip flop relatively
Under the table 6PTM 45nm standard technology, the performance of the present invention and traditional d type flip flop relatively
From table 4, calculate and can know, based on SMIC 130nm standard technology, the power consumption of d type flip flop of the present invention is 1.8074uW, compares with traditional d type flip flop, and total power consumption reduces 2.09%; From table 5, calculate and can know, based on the PTM90nm standard technology, the power consumption of d type flip flop of the present invention is 1.8085uW, compares with traditional d type flip flop, and total power consumption reduces 0.844%; From table 6, calculate and can know, based on PTM 45nm standard technology, the power consumption of d type flip flop of the present invention is 0.8541uW, compares with traditional d type flip flop, and total power consumption reduces 1.83%.
Simulation waveform is respectively like Fig. 8, Fig. 9 and shown in Figure 10, and the table of comparisons 7 results show that the function of low-power consumption impulse type d type flip flop of the present invention is correct.
The state transition table of asynchronous set, the d type flip flop that resets is as shown in table 7.
Table 7 asynchronous set, the d type flip flop state transition table resets
Claims (8)
1. a low-power consumption short pulse produces circuit; It is characterized in that: comprise PMOS pipe, NMOS pipe, first NAND gate and first inverter; The source electrode of described PMOS pipe is connected with power positive end; The drain electrode three of the drain electrode of first signal input part of described first NAND gate, described PMOS pipe and described NMOS pipe is connected; The secondary signal input of described first NAND gate is connected with the grid of described PMOS pipe; The source ground of described NMOS pipe; The signal input part of the signal output part of described first NAND gate, described first inverter and complementary pulse signal output end three are connected, and the grid and the described pulse signal output end three of the signal output part of described first inverter, described NMOS pipe are connected, and the grid of described PMOS pipe is connected with clock signal.
2. a kind of low-power consumption short pulse according to claim 1 produces circuit; It is characterized in that: described first NAND gate by the 2nd PMOS manage, the 3rd PMOS pipe, the 2nd NMOS pipe and the 3rd NMOS pipe form; The source electrode of the source electrode of described the 2nd PMOS pipe, described the 3rd PMOS pipe all is connected with power positive end; The drain electrode and the described complementary pulse signal output end of the drain electrode of the drain electrode of described the 2nd PMOS pipe, described the 3rd PMOS pipe, described the 2nd NMOS pipe are connected; The source electrode of described the 2nd NMOS pipe is connected with the drain electrode of described the 3rd NMOS pipe; The source ground of described the 3rd NMOS pipe; The grid of the grid of described the 3rd PMOS pipe, described the 3rd NMOS pipe is first signal input part of described first NAND gate; The drain electrode of the drain electrode of the grid of the grid of described the 3rd PMOS pipe, described the 3rd NMOS pipe, described PMOS pipe and described NMOS pipe is connected; The grid of the grid of described the 2nd PMOS pipe, described the 2nd NMOS pipe is the secondary signal input of described first NAND gate; The grid of the grid of the grid of described the 2nd PMOS pipe, described the 2nd NMOS pipe and described PMOS pipe all is connected with clock signal, and the channel length that channel length that the channel length of described the 2nd PMOS pipe, the channel length of described the 3rd PMOS pipe, described the 2nd NMOS manage and described the 3rd NMOS manage is 1.15～1.4 times of minimum channel length under the standard technology.
3. low-power consumption impulse type d type flip flop; It is characterized in that: comprise that the low-power consumption short pulse produces circuit, input inversion circuit, clock CMOS logic D-latch unit and output negative circuit; The complementary pulse signal output end that described low-power consumption short pulse produces circuit is connected with the complementary pulse signal input terminal of described clock CMOS logic D-latch unit; The pulse signal output end that described low-power consumption short pulse produces circuit is connected with the pulse signal input terminal of described clock CMOS logic D-latch unit; The signal output part of described input inversion circuit is connected with the reset signal input of described clock CMOS logic D-latch unit, and the signal output part of described clock CMOS logic D-latch unit is connected with the signal input part of described output negative circuit.
4. a kind of low-power consumption impulse type d type flip flop according to claim 3; It is characterized in that: described low-power consumption short pulse produces circuit and comprises PMOS pipe, NMOS pipe, first NAND gate and first inverter; The source electrode of described PMOS pipe is connected with power positive end; The drain electrode three of the drain electrode of first signal input part of described first NAND gate, described PMOS pipe and described NMOS pipe is connected; The secondary signal input of described first NAND gate is connected with the grid of described PMOS pipe; The source ground of described NMOS pipe; The complementary pulse signal output end three that the signal input part of the signal output part of described first NAND gate, described first inverter and described low-power consumption short pulse produce circuit is connected; The pulse signal output end three that the grid of the signal output part of described first inverter, described NMOS pipe and described low-power consumption short pulse produce circuit is connected, and the grid of described PMOS pipe is connected with clock signal.
5. a kind of low-power consumption impulse type d type flip flop according to claim 4; It is characterized in that: described first NAND gate by the 2nd PMOS manage, the 3rd PMOS pipe, the 2nd NMOS pipe and the 3rd NMOS pipe form; The source electrode of the source electrode of described the 2nd PMOS pipe, described the 3rd PMOS pipe all is connected with power positive end; The complementary pulse signal output end that the drain electrode of the drain electrode of the drain electrode of described the 2nd PMOS pipe, described the 3rd PMOS pipe, described the 2nd NMOS pipe and described low-power consumption short pulse produce circuit is connected; The source electrode of described the 2nd NMOS pipe is connected with the drain electrode of described the 3rd NMOS pipe; The source ground of described the 3rd NMOS pipe; The grid of the grid of described the 3rd PMOS pipe, described the 3rd NMOS pipe is first signal input part of described first NAND gate; The drain electrode of the drain electrode of the grid of the grid of described the 3rd PMOS pipe, described the 3rd NMOS pipe, described PMOS pipe and described NMOS pipe is connected; The grid of the grid of described the 2nd PMOS pipe, described the 2nd NMOS pipe is the secondary signal input of described first NAND gate; The grid of the grid of the grid of described the 2nd PMOS pipe, described the 2nd NMOS pipe and described PMOS pipe all is connected with clock signal, and the channel length that channel length that the channel length of described the 2nd PMOS pipe, the channel length of described the 3rd PMOS pipe, described the 2nd NMOS manage and described the 3rd NMOS manage is 1.15～1.4 times of minimum channel length under the standard technology.
6. a kind of low-power consumption impulse type d type flip flop according to claim 3; It is characterized in that: described input inversion circuit comprises second inverter; The signal output part of described second inverter is the signal output part of described input inversion circuit; The signal output part of described second inverter is connected with the reset signal input of described clock CMOS logic D-latch unit, and the signal input part of described second inverter is connected with reset signal.
7. a kind of low-power consumption impulse type d type flip flop according to claim 3; It is characterized in that: described clock CMOS logic D-latch unit comprises input clock inverter module, the first inclusive NAND door and feedback clock inverter module; Described input clock inverter module comprises the 4th PMOS pipe, the 5th PMOS pipe, the 4th NMOS pipe and the 5th NMOS pipe; The described first inclusive NAND door comprise first or the door and second NAND gate; Described feedback clock inverter module comprises the 6th PMOS pipe, the 7th PMOS pipe, the 6th NMOS pipe and the 7th NMOS pipe; Described first or the door first signal input part be the reset signal input of described clock CMOS logic D-latch unit; Described first or the door first signal input part be connected with the signal output part of described input inversion circuit; The drain electrode of the drain electrode of the drain electrode of the drain electrode of described the 5th PMOS pipe, described the 7th PMOS pipe, described the 4th NMOS pipe, described the 6th NMOS pipe all with described first or the secondary signal input be connected; Described first or the door signal output part be connected with first signal input part of described second NAND gate; The secondary signal input of described second NAND gate is connected with asserts signal; The signal output part of described second NAND gate is the signal output part of described clock CMOS logic D-latch unit; The signal output part of described second NAND gate is connected with the signal input part of described output negative circuit; The signal output part of described second NAND gate is connected with the grid of described the 6th PMOS pipe and the grid three of described the 7th NMOS pipe; The source electrode of described the 4th PMOS pipe all is connected with power positive end with the source electrode of described the 6th PMOS pipe, and the grid of the grid of described the 4th PMOS pipe, described the 5th NMOS pipe all is connected with input data signal, and the drain electrode of described the 4th PMOS pipe is connected with the source electrode of described the 5th PMOS pipe; The grid of the grid of described the 5th PMOS pipe, described the 6th NMOS pipe is the complementary pulse signal input terminal of described clock CMOS logic D-latch unit; The grid of the grid of described the 5th PMOS pipe, described the 6th NMOS pipe all is connected with the complementary pulse signal output end of described low-power consumption short pulse generation circuit, and the grid of the grid of described the 4th NMOS pipe, described the 7th PMOS pipe is the pulse signal input terminal of described clock CMOS logic D-latch unit, and the grid of the grid of described the 4th NMOS pipe, described the 7th PMOS pipe all is connected with the pulse signal output end of described low-power consumption short pulse generation circuit; The source electrode of described the 4th NMOS pipe is connected with the drain electrode of described the 5th NMOS pipe; The drain electrode of described the 6th PMOS pipe is connected with the source electrode of described the 7th PMOS pipe, and the source electrode of described the 6th NMOS pipe is connected with the drain electrode of described the 7th NMOS pipe, the source grounding of the source electrode of described the 5th NMOS pipe and described the 7th NMOS pipe.
8. a kind of low-power consumption impulse type d type flip flop according to claim 3; It is characterized in that: described output negative circuit comprises the 3rd inverter, the 4th inverter and the 5th inverter; The signal input part of the signal input part of described the 3rd inverter, described the 5th inverter is connected with the signal input part three of described output negative circuit; The signal output part of described the 3rd inverter is connected with the signal input part of described the 4th inverter; The signal output part of described the 4th inverter is connected with first signal output part, and the signal output part of described the 5th inverter is connected with the secondary signal output.
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