CN104333370A - Quaternary-binary clock based QBC20 circuit - Google Patents

Abstract

The invention discloses a circuit for converting a QC (quaternary clock) into a BC (binary clock) 20. The circuit comprises three NMOS (N-channel metal oxide semiconductor) transistors with thresholds being 0.5, a NMOS transistor with a threshold being 1.5, two NMOS transistors with thresholds being 2.5, two PMOS (P-channel metal oxide semiconductor) transistors with thresholds being -0.5 and two PMOS transistors with thresholds being -1.5. The circuit has the advantages that the conversion circuit converts QC signals into BC20 signals which are easy to recognize and use without loss of useful information of the QC, so that the QC signals can be used for driving a digital circuit based on the BC20 signals, and compatibility between the QC and the BC20 is realized; the conversion circuit converts the QC signals difficult to recognize into the BC20 signals easy to recognize, so that a QC recognition circuit can be formed by the conversion circuit and a simple BC20 recognition circuit, complexity of a QC application circuit can be lowered, and popularization and application of the QC are facilitated.

Description

Based on the QBC20 circuit of four two-value clocks

Technical field the present invention relates to a kind of cmos circuit four value clocks (Quaternary Clock, QC) being converted to two-value clock (Binary Clock, BC).

Background technology digital circuitry comprises Clock Subsystem, and Clock Subsystem is divided into clock distributing network and trigger two parts ^[1].The Clock Subsystem of prior art is two-value Clock Subsystem.And multi-valued signal has the advantages that to contain much information ^[2-6], such as, four value clock signal QC have six saltus steps (edge) in one-period ^[6], and traditional two-value clock BC only has twice saltus step in one-period.Due to three times that the former edge number in one-period is the latter, so digital circuit uses four value clocks to be conducive to reduction system power dissipation ^[6].In addition, the multi-valued signal such as four value signals is more suitable for the novel nano electronic device design digital circuitry many-valued with the next generation than binary signal ^[6,7].Such as, the novel field effect transistor QDG-QDCFET of reported first in 2012 ^[8]be more suitable for for Design and implementation four-valued logic owing to having four operating states ^[7].Therefore, four value clocks also design digital circuitry by being more suitable for many-valued nano electron device.Based on the advantage of four value clocks, document [4-6] has been had to carry out certain application study to four value clocks at present.Be worth in research four in the process of clock application, occurred following two problems: one, with the compatibling problem of two-value clock; Two, how to identify efficiently and utilize four value clocks, making the application circuit simple question as far as possible of four value clocks.At present, the sequential parts such as the latch in existing digital circuit, trigger nearly all design based on two-value clock, but not four value clocks.There will be use four like this and be worth the digital system of clock and the digital system problem that clock signal is incompatible when carrying out synchrodata and exchanging using two-value clock.The difficult point solving this problem is: should be fully used in six edges of four value clocks, can drive again and use the digital system of two-value clock to carry out work.Do not solve this problem, four value clocks are just difficult to obtain deeply and apply widely, and the advantages such as its low-power consumption are also difficult to manifest.In addition, because four value clocks have four level values and six kinds of hopping edges, so detection and Identification four are worth clock will be difficult to traditional two-value clock.How making four value clocks be easy to identify and use, make its identification and utilization circuit simple as far as possible, is the Second Problem of four value clock application.

List of references:

[1]Kim C.，Kang S.M.，A low-swing clock double-edge triggered flip-flop[J].IEEE Journal of Solid-State Circuits，2002，37(5)：648-652.

[2]Wu X.，Prosser F.Design of ternary CMOS circuits based on transmission runction theory[J]，International Journal of Electronics，1988，65(5)：891-905.

[3]Prosser F.，Wu X.，Chen X.，CMOS Ternary Flip-Flops&Their Applications[J].IEE Proceedings on Computer&Digital Techniques，1988，135(5)：266-272.

[4] Xia Yinshui, Wu Xunwei, many-valued clock and block form many bats multiple value flip-flop [J], electronic letters, vol, 1997,25 (8): 52-54.

[5]Xia Y.S.，Wang L.Y.，Almaini A.E.A.，A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock[J]，Journal of Computer Science and Technology，2005，20(2)：237-242.

[6]Lang Y.-F.，Shen J.-Z.，A general structure of all-edges-triggered flip-flop based on multivalued clock[J]，International Journal of Electronics，2013，100(12)：1637-1645.

[7]Supriya Karmakar，Design of quaternary logic circuit using quantum dot gate-quantum dot channel FET(QDG-QDCFET)[J]，International Journal of Electronics，2014，101(10)：1427-1442.

[8]Jain，F.，Karmakar，S.，Chan，P.-Y.，Suarez，E.，Gogna，M.，Chandy，J.，&Heller，E.Quantum Dot Channel(QDC)Field-Effect Transistors(FETs)using II-VI barrier layers[J].Journal of Electronic Materials，2012，41(10)，2775-2784.

Summary of the invention is for produced problem in above-mentioned four value clock QC application, task of the present invention is exactly be worth under namely clock QC advantage make full use of the prerequisite of four value clocks, six saltus steps in maintenance four, solve the compatibling problem between four value clock QC and two-value clock BC, and the indiscernible problem of four value clocks.

For completing invention task, a kind of cmos circuit four value clock QC being converted to two-value clock BC of the invention.This circuit is keeping the two kinds of hopping edges under the constant prerequisite of clock edge number, six kinds of hopping edges of four value clock QC being converted to two-value clock BC.

The technical scheme that the present invention takes is: first, carries out classification sum up in conjunction with the level logic value of research papers to four value clock QC; Then, keeping, under the prerequisite that the edge number of clock is constant, four kinds of level logic values of four value clock QC being converted to two kinds of level logic values; Finally, realize according to transmission voltage switching theorem metal-oxide-semiconductor the circuit four value clock QC being converted to two-value clock BC.Two-value clock BC mono-aspect that this circuit exports can be used for the digital circuit driving tradition based on two-value clock, solves the compatibling problem of four value clock QC; On the other hand, the two-value clock BC of output only has two level values, just can identify with a level threshold, solves the indiscernible problem of four value clock QC.

The above-mentioned circuit four value clock QC being converted to two-value clock BC comprises following technical characteristic:

The input signal of A, this circuit is four value clock QC, and its level logic value is 0,1,2 and 3, and the switch sequence of four value clocks is 0 → 1 → 2 → 3 → 2 → 1 → 0;

The output signal of B, this circuit is a two-value clock BC, and its level logic value is 0 and 1, and the switch sequence of two-value clock is 2 → 0 → 2;

C, when four value clock QC input 0 or 2, two-value clock BC output level logical value 2;

D, when four value clock QC input 1 or 3, two-value clock BC output level logical value 0.

The four value clock QC that the circuit with above-mentioned technical characteristic can be 0 → 1 → 2 → 3 → 2 → 1 → 0 switch sequence are converted to the two-value clock BC that switch sequence is 2 → 0 → 2.As can be seen from the input/output signal of this circuit, in certain hour section, the edge number of two kinds of clocks is identical, and the two-value clock BC exported is easy to identify than four value clock QC of input.Therefore, the present invention adopts the technical scheme comprising above-mentioned technical characteristic can complete this invention task.

According to above-mentioned technical characteristic and transmission voltage switching theorem ^[2,3], can obtain the switching stage function expression of above-mentioned circuit for switching between two clocks, shown in (1), its input and output signal is respectively four value clock QC and two-value clock BC.

BC＝2*(QC ^0.5+ ^1.5QC·QC ^2.5)#0*( ^0.5QC·QC ^1.5+ ^2.5QC). (1)

For being easy to realize formula (1) with metal-oxide-semiconductor, it is carried out to the expression formula conversion of switching stage.Switching stage function expression after conversion is such as formula shown in (2).

$\mathrm{BC}=2*({\mathrm{QC}}^{0.5}+\stackrel{\‾}{\mathrm{QC}\left(1.5\right)}_{0.5}\·\stackrel{\‾}{\mathrm{QC}\left(2.5\right)}_{0.5})\#0*\left(\mathrm{QC}\·\stackrel{\‾}{\mathrm{QC}\left(1.5\right)}_{05}+\mathrm{QC}_{2.5}_{0.5}\right)---\left(2\right)$

Known according to formula (2), need the PMOS using the NMOS tube of three thresholds 0.5, the NMOS tube of a threshold 1.5, the NMOS tube of two thresholds 2.5, the PMOS of two thresholds-0.5 and two thresholds-1.5.Can form with these 10 metal-oxide-semiconductors the circuit that four value clocks are converted to two-value clock, its input termination four is worth clock QC, exports at output the two-value clock BC that the cycle is 2 → 0 → 2.Because this circuit employs 10 metal-oxide-semiconductors altogether, so circuit of the present invention is simple.

Six kinds of edges of four value clock QC can be converted to two kinds of edges of two-value clock BC by this circuit for switching between two clocks, and the edge number of two kinds of clocks is identical within the identical time period.So just take full advantage of six edges of four value clock QC thus maintain the advantage of four value clocks, the digital circuit using two-value clock can be driven again.This makes the compatibling problem of four value clock QC and two-value clock BC be resolved; And only having two level owing to changing the two-value clock BC exported, four level being worth clock QC than identification four are easy, and circuit of therefore this invention is changed by clock and also solved the indiscernible problem of four value clock QC.

It can be seen from the above, and the circuit for switching between two clocks of invention not only solves the compatibling problem of four value clock QC and two-value clock BC but also solves the indiscernible problem of four value clock QC.Like this, four value clocks of low-power consumption advantage can be used to drive digital circuit based on two-value clock, thus reduce system power dissipation; In addition, that this circuit for switching between two clocks invented exports is two-value clock BC easy to identify, can reduce the complexity that application four is worth clock circuit like this, and then be conducive to applying of four value clocks.

Accompanying drawing illustrates and is described in further detail the present invention below in conjunction with the drawings and specific embodiments.

The CMOS line map that Fig. 1 is input, output signal is respectively the circuit for switching between two clocks of four value clock QC and two-value clock BC.

Fig. 2 is the voltage transient waveforms figure of four value clock QC and two-value clock BC in circuit shown in Fig. 1.

Embodiment is according to formula (2), the switching stage that can obtain the circuit for switching between two clocks of this invention realizes, its line map as shown in Figure 1, this circuit employs the PMOS of the NMOS tube of three thresholds 0.5, the NMOS tube of a threshold 1.5, the NMOS tube of two thresholds 2.5, the PMOS of two thresholds-0.5 and two thresholds-1.5, totally 10 metal-oxide-semiconductors.Its operation principle is: access four value clocks at input (QC): 0 → 1 → 2 → 3 → 2 → 1 → 0, just exports two-value clock: 2 → 0 → 2 at output (BC).The two-value clock BC utilizing the present invention can obtain level logic value easily to meet invention technical characteristic.If connect thereafter threshold 1.5 4 value inverter, the two-value clock that the cycle is 0 → 3 → 0 so can be obtained.Therefore, circuit for switching between two clocks structure of the present invention is simple, easy to use.

For verifying this circuit invented, with HSPICE software, it is simulated below.The technique that simulation adopts is TSMC 180nnm CMOS, and output loading is 30fF.The magnitude of voltage of four level logic values 0,1,2 and 3 correspondence of four value clocks is respectively 0V, 1.67V, 3.33V and 5.0V; The magnitude of voltage of two level logic values 0 and 2 correspondence of two-value clock is respectively 0V and 3.33V.As shown in Figure 2, wherein QC and BC is respectively four value clocks of invention circuit input and the two-value clock of output to the voltage transient waveforms of simulation gained.The analog result of Fig. 2 shows, the four value clocks that the present invention can be 0 → 1 → 2 → 3 → 2 → 1 → 0 in the cycle are converted to the two-value clock that the cycle is 2 → 0 → 2, achieve the technical characteristic proposed in summary of the invention.

Sum up: the circuit for switching between two clocks of this invention has correct function, six saltus steps of four value clocks all can be converted to the saltus step of two-value clock, the number of transitions of two kinds of clocks is remained unchanged, solves the two problems run in four value clock application, complete invention task.The present invention only employs 10 metal-oxide-semiconductors, and circuit is simple; And HSPICE software simulation result shows, circuit working of the present invention is reliable and stable.Last it is noted that the present invention is applicable to need four value clocks to be converted to two-value clock and must exports the clock transformation applications occasion of 2 and the palpus output 0 when four value clocks input 1 or 3 when four value clocks inputs 0 or 2.

Claims (2)

1. four value clocks are converted to the cmos circuit of two-value clock by one kind, it has four value input end of clock (QC) and a two-value output terminal of clock (BC), and the feature of this circuit is: it comprises the NMOS tube (N1 of three thresholds 0.5, N2 and N3), the NMOS tube (N6) of a threshold 1.5, the NMOS tube (N4 and N5) of two thresholds 2.5, the PMOS (P2 and P3) of two thresholds-0.5 and the PMOS (P1 and P4) of two thresholds-1.5, described metal-oxide-semiconductor P1, N2, N4, P3, N5, the grid of P4 and N6 connects with circuit input end (QC), and the source electrode of metal-oxide-semiconductor P3 and P4 connects with the voltage source of level logic value 3, N3, N4, the source electrode of N5 and N6 connects with power supply ground, and the source electrode of N1 and P1 connects with the voltage source of level logic value 2, and the drain electrode of P3 and N5 connects with the grid of N1, the source electrode of N2 connects with the drain electrode of N3, the drain electrode of N1 connects with the source electrode of P2, and the drain electrode of P4 and N6 connects with the grid of P2 and N3, P1, P2, the drain electrode of N2 and N4 connects as the output (BC) of circuit, its function is the two-value clock output that the four value clocks being 0 → 1 → 2 → 3 → 2 → 1 → 0 level logic value switch sequence in one-period are converted to that level logic value switch sequence in one-period is 2 → 0 → 2.

2. the circuit of four value clock conversion two-value clocks according to claim 1, it is characterized in that: in a cmos circuit, four value clock level logical values 0 and 2 can be converted to two-value clock level logical value 2 and four value clock level logical values 1 and 3 can be converted to two-value clock level logical value 0; Its contactor level expression formula is

$\mathrm{BC}=2*(\mathrm{QC}_{0.5}+{\stackrel{\‾}{\mathrm{QC}\left(1.5\right)}}^{05}\·\stackrel{\‾}{\mathrm{QC}\left(2.5\right)}_{0.5})\#0*(\mathrm{QC}_{0.5}\·\stackrel{\‾}{\mathrm{QC}\left(1.5\right)}_{0.5}+\mathrm{QC}_{2.5}).$