CN104333370A - Quaternary-binary clock based QBC20 circuit - Google Patents

Abstract

The present invention creates a circuit for converting QC into BC20, which consists of three NMOS transistors with a threshold of 0.5, one NMOS transistor with a threshold of 1.5, two NMOS transistors with a threshold of 2.5, two PMOS transistors with a threshold of -0.5, and two The value of the present invention is that the conversion circuit converts the QC signal into a BC20 signal that is easy to identify and use under the premise of ensuring that the QC useful information is not lost; in this way, the QC signal can be used to drive The digital circuit based on the BC20 signal, on the other hand, solves the compatibility problem between QC and BC20; in addition, because the conversion circuit converts the QC that is difficult to identify into the easily identifiable BC20, the conversion circuit and the simple BC20 can be used to identify Circuits are used to form the identification circuit of QC, which can reduce the complexity of the QC application circuit, and then help the popularization and application of QC.

Description

QBC20 circuit based on four binary clocks

Technical Field The present invention relates to a CMOS circuit that converts a Quaternary Clock (QC) into a Binary Clock (BC).

Background technology The digital circuit system includes a clock subsystem, and the clock subsystem is divided into two parts: a clock distribution network and a flip-flop ^[1] . The prior art clock subsystem is a binary clock subsystem. The multi-valued signal has the characteristics of large amount of information ^[2-6] . For example, the four-valued clock signal QC has six jumps (edges) in one cycle ^[6] , while the traditional binary clock BC has six jumps (edges) in one cycle. Only two transitions. Because the former has three times the number of edges in one cycle than the latter, the use of four-valued clocks in digital circuits is beneficial to reduce system power consumption ^[6] . In addition, multi-valued signals such as four-valued signals are more suitable for designing digital circuit systems with the next generation of multi-valued new nano-electronic devices than binary signals ^[6,7] . For example, the new field effect transistor QDG-QDCFET ^[8] first reported in 2012 is more suitable for designing and implementing four-valued logic circuits ^[7] because of its four working states. Therefore, the four-valued clock will also be more suitable for designing digital circuit systems with multi-valued nanoelectronic devices. Based on the advantages of four-valued clocks, there are literatures [4-6] that have carried out certain application research on four-valued clocks. In the process of researching the application of four-valued clocks, the following two problems have emerged: 1. Compatibility with binary clocks; 2. How to efficiently identify and use four-valued clocks to make the application circuit of four-valued clocks as simple as possible question. At present, the timing components such as latches and flip-flops in existing digital circuits are almost all designed based on binary clocks instead of four-valued clocks. In this way, there will be a problem that the clock signals of the digital system using the four-valued clock and the digital system using the binary clock are incompatible when exchanging synchronous data. The difficulty in solving this problem is that the six edges of the four-value clock must be fully utilized, and the digital system using the two-value clock must be driven to work. If this problem is not solved, it will be difficult for the four-valued clock to be applied deeply and widely, and its advantages such as low power consumption will also be difficult to show. In addition, since the four-value clock has four level values and six transition edges, it is more difficult to detect and identify the four-value clock than the traditional two-value clock. How to make the four-value clock easy to identify and use, and make its identification and application circuit as simple as possible is the second problem in the application of the four-value clock.

references:

[1] Kim C., Kang S.M., A low-swing clock double-edge triggered flip-flop[J]. IEEE Journal of Solid-State Circuits, 2002, 37(5): 648-652.

[2] Wu X., Prosser F.Design of ternary CMOS circuits based on transmissionrunction theory[J], International Journal of Electronics, 1988, 65(5): 891-905.

[3] Prosser F., Wu X., Chen X., CMOS Ternary Flip-Flops & Their Applications [J]. IEE Proceedings on Computer & Digital Techniques, 1988, 135(5): 266-272.

[4] Xia Yinshui, Wu Xunwei, Multi-valued clock and parallel multi-shot multi-valued flip-flop [J], Electronic Journal, 1997, 25(8): 52-54.

[5] Xia Y.S., Wang L.Y., Almaini A.E.A., A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock[J], Journal of Computer Science and Technology, 2005, 20(2): 237-242.

[6] Lang Y.-F., Shen J.-Z., A general structure of all-edges-triggered flip-flop basedon multivalued clock[J], International Journal of Electronics, 2013, 100(12): 1637- 1645.

[7] Supriya Karmakar, Design of quaternary logic circuit using quantum dotgate-quantum dot channel FET (QDG-QDCFET) [J], International Journal of Electronics, 2014, 101(10): 1427-1442.

[8] Jain, F., Karmakar, S., Chan, P.-Y., Suarez, E., Gogna, M., Chandy, J., & Heller, E. Quantum Dot Channel (QDC) Field-Effect Transistors (FETs) using II-VIbarrier layers[J]. Journal of Electronic Materials, 2012, 41(10), 2775-2784.

SUMMARY OF THE INVENTION In view of the above-mentioned problems in the application of the four-valued clock QC, the task of the present invention is to solve the problems between the four-valued clock QC and the binary clock on the premise of maintaining the advantages of the four-valued clock QC, that is, making full use of the six jumps of the four-valued clock. The problem of compatibility between BCs and the difficulty of identifying four-valued clocks.

In order to accomplish the inventive task, the present invention creates a CMOS circuit that converts the four-valued clock QC into the binary clock BC. The circuit converts the six transition edges of the four-value clock QC into two transition edges of the binary clock BC under the premise of keeping the number of clock edges unchanged.

The technical solution adopted by the present invention is: first, classify and summarize the level logic values of the four-valued clock QC in combination with relevant research documents; then, under the premise of keeping the number of edges of the clock unchanged, combine The level logic value is converted into two level logic values; finally, according to the transmission voltage switch theory, the circuit for converting the four-valued clock QC into the binary clock BC is implemented with a MOS tube. On the one hand, the binary clock BC output by this circuit can be used to drive the traditional digital circuit based on the binary clock, which solves the compatibility problem of the quaternary clock QC; on the other hand, the output binary clock BC has only two level values, which can be One level threshold can be identified, which solves the problem of difficult identification of four-valued clock QC.

The above-mentioned circuit that converts the four-valued clock QC into the binary clock BC includes the following technical features:

A. The input signal of the circuit is a four-valued clock QC, whose level logic values are 0, 1, 2 and 3, and the switching sequence of the four-valued clock is 0→1→2→3→2→1→0;

B. The output signal of the circuit is a binary clock BC, whose level logic values are 0 and 1, and the switching sequence of the binary clock is 2→0→2;

C. When the four-valued clock QC inputs 0 or 2, the binary clock BC outputs a logical value of 2;

D. When the four-valued clock QC inputs 1 or 3, the binary clock BC outputs a level logic value of 0.

The circuit with the above technical features can convert the four-valued clock QC whose switching sequence is 0→1→2→3→2→1→0 into the binary clock BC whose switching sequence is 2→0→2. It can be seen from the input and output signals of the circuit that within a certain period of time, the number of edges of the two clocks is the same, and the output binary clock BC is easier to identify than the input quaternary clock QC. Therefore, the present invention can accomplish the task of this invention by adopting the technical solution including the above-mentioned technical features.

According to the above technical characteristics and transmission voltage switching theory ^[2,3] , the switch-level function expression of the above clock conversion circuit can be obtained, as shown in formula (1), its input and output signals are four-valued clock QC and binary Value clock BC.

BC＝2*(QC ^0.5 + ^1.5 QC·QC ^2.5 )#0*( ^0.5 QC·QC ^1.5 + ^2.5 QC). (1)

In order to realize formula (1) easily with MOS tube, carry on the expression transformation of switching level to it. The transformed switch-level function expression is shown in formula (2).

$\mathrm{<span\; class="notranslate">\; BC</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; *</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; QC</span>}}^{\mathrm{<span\; class="notranslate">\; 0.5</span>}}<span\; class="notranslate">\; +</span>\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{\mathrm{<span\; class="notranslate">\; QC</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1.5</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 0.5</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{\mathrm{<span\; class="notranslate">\; QC</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2.5</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 0.5</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \#</span>\mathrm{<span\; class="notranslate">\; 0</span>}<span\; class="notranslate">\; *</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; QC</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{\mathrm{<span\; class="notranslate">\; QC</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1.5</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 05</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; QC</span>}_{\mathrm{<span\; class="notranslate">\; 2.5</span>}}_{\mathrm{<span\; class="notranslate">\; 0.5</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

According to formula (2), it can be seen that three NMOS transistors with a threshold of 0.5, one NMOS transistor with a threshold of 1.5, two NMOS transistors with a threshold of 2.5, two PMOS transistors with a threshold of -0.5, and two PMOS transistors with a threshold of -1.5 are required. . These 10 MOS transistors can be used to form a circuit for converting a four-valued clock into a binary clock. Its input terminal is connected to a four-valued clock QC, and a binary clock BC with a period of 2→0→2 is output at the output terminal. Since the circuit uses 10 MOS tubes in total, the circuit of the present invention is simple.

The clock conversion circuit can convert the six edges of the four-valued clock QC into two kinds of edges of the binary clock BC, and the number of edges of the two clocks is the same in the same time period. In this way, the six edges of the four-valued clock QC are fully utilized to maintain the advantages of the four-valued clock, and can drive digital circuits using binary clocks. This solves the problem of compatibility between the four-value clock QC and the binary clock BC; and because the converted output binary clock BC has only two levels, it is easier than identifying the four levels of the four-value clock QC, so this invention The circuit of the present invention also solves the problem of difficult identification of the four-valued clock QC through clock conversion.

It can be seen from the above that the inventive clock conversion circuit not only solves the problem of compatibility between the four-valued clock QC and the binary clock BC, but also solves the problem of difficult identification of the four-valued clock QC. In this way, a four-valued clock with low power consumption can be used to drive a digital circuit based on a binary clock, thereby reducing system power consumption; in addition, the clock conversion circuit of this invention outputs an easily identifiable binary clock BC, so that The complexity of applying the four-valued clock circuit can be reduced, thereby facilitating popularization and application of the four-valued clock.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

Fig. 1 is a CMOS circuit diagram of a clock conversion circuit whose input and output signals are respectively a four-valued clock QC and a binary clock BC.

FIG. 2 is a voltage transient waveform diagram of the four-valued clock QC and the binary clock BC in the circuit shown in FIG. 1 .

Specific embodiments According to formula (2), the switch-level implementation of the clock conversion circuit of this invention can be obtained. Its circuit diagram is shown in Figure 1. The circuit uses three NMOS transistors with a threshold of 0.5 and one NMOS transistor with a threshold of 1.5. , two NMOS transistors with a threshold of 2.5, two PMOS transistors with a threshold of -0.5, and two PMOS transistors with a threshold of -1.5, a total of 10 MOS transistors. Its working principle is: a four-valued clock is connected to the input terminal (QC): 0→1→2→3→2→1→0, and a binary clock is output at the output terminal (BC): 2→0→2. The invention can easily obtain the binary clock BC whose level logic value conforms to the technical features of the invention. If it is followed by a threshold 1.5 four-value inverter, then a binary clock with a period of 0→3→0 can be obtained. Therefore, the clock conversion circuit of the present invention is simple in structure and easy to use.

In order to verify the circuit of this invention, it is simulated with HSPICE software below. The process used in the simulation is TSMC 180nnm CMOS, and the output load is 30fF. The voltage values corresponding to the four level logic values 0, 1, 2 and 3 of the four-valued clock are 0V, 1.67V, 3.33V and 5.0V respectively; the voltages corresponding to the two level logic values 0 and 2 of the binary clock The values are 0V and 3.33V, respectively. The simulated voltage transient waveform is shown in Figure 2, where QC and BC are the four-valued clock input and the binary clock output by the inventive circuit, respectively. The simulation result of Fig. 2 shows that the present invention can convert the four-valued clock whose period is 0→1→2→3→2→1→0 into a binary clock whose period is 2→0→2, realizing the realization in the content of the invention Proposed technical characteristics.

Summary: The clock conversion circuit invented this time has the correct function. It can convert the six jumps of the four-valued clock into the jumps of the binary clock, so that the number of jumps of the two clocks remains unchanged, and solves the problem of the four-valued clock. The two problems encountered in the application have completed the invention task. The present invention only uses 10 MOS tubes, and the circuit is simple; and the HSPICE software simulation result shows that the circuit of the present invention works stably and reliably. Finally, it should be pointed out that the present invention is suitable for clock conversion applications that need to convert a four-valued clock into a binary clock and output 2 when the four-valued clock inputs 0 or 2, and output 0 when the four-valued clock inputs 1 or 3 occasion.

Claims (2)

1. four value clocks are converted to the cmos circuit of two-value clock by one kind, it has four value input end of clock (QC) and a two-value output terminal of clock (BC), and the feature of this circuit is: it comprises the NMOS tube (N1 of three thresholds 0.5, N2 and N3), the NMOS tube (N6) of a threshold 1.5, the NMOS tube (N4 and N5) of two thresholds 2.5, the PMOS (P2 and P3) of two thresholds-0.5 and the PMOS (P1 and P4) of two thresholds-1.5, described metal-oxide-semiconductor P1, N2, N4, P3, N5, the grid of P4 and N6 connects with circuit input end (QC), and the source electrode of metal-oxide-semiconductor P3 and P4 connects with the voltage source of level logic value 3, N3, N4, the source electrode of N5 and N6 connects with power supply ground, and the source electrode of N1 and P1 connects with the voltage source of level logic value 2, and the drain electrode of P3 and N5 connects with the grid of N1, the source electrode of N2 connects with the drain electrode of N3, the drain electrode of N1 connects with the source electrode of P2, and the drain electrode of P4 and N6 connects with the grid of P2 and N3, P1, P2, the drain electrode of N2 and N4 connects as the output (BC) of circuit, its function is the two-value clock output that the four value clocks being 0 → 1 → 2 → 3 → 2 → 1 → 0 level logic value switch sequence in one-period are converted to that level logic value switch sequence in one-period is 2 → 0 → 2.

2. the circuit of four value clock conversion two-value clocks according to claim 1, it is characterized in that: in a cmos circuit, four value clock level logical values 0 and 2 can be converted to two-value clock level logical value 2 and four value clock level logical values 1 and 3 can be converted to two-value clock level logical value 0; Its contactor level expression formula is

$\mathrm{BC}=2*(\mathrm{QC}_{0.5}+{\stackrel{\&OverBar;}{\mathrm{QC}\left(1.5\right)}}^{05}\&CenterDot;\stackrel{\&OverBar;}{\mathrm{QC}\left(2.5\right)}_{0.5})\#0*(\mathrm{QC}_{0.5}\&CenterDot;\stackrel{\&OverBar;}{\mathrm{QC}\left(1.5\right)}_{0.5}+\mathrm{QC}_{2.5}).$