CN104467805B - A kind of QC BC03 change-over circuit - Google Patents
A kind of QC BC03 change-over circuit Download PDFInfo
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- CN104467805B CN104467805B CN201410648014.4A CN201410648014A CN104467805B CN 104467805 B CN104467805 B CN 104467805B CN 201410648014 A CN201410648014 A CN 201410648014A CN 104467805 B CN104467805 B CN 104467805B
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Abstract
A kind of circuit for QC being converted to BC03 of the invention, the circuit is made up of the PMOS of the NMOS tube of three thresholds 0.5, the NMOS tube of threshold 1.5, the NMOS tube of threshold 2.5, the PMOS of three thresholds 0.5, the PMOS of threshold 1.5 and a threshold 2.5；Value of the invention is that：The change-over circuit is converted to QC signals traditional BC signals on the premise of ensuring that QC useful informations are not lost；QC signals can so be used and use the digital circuits of BC signals to drive, so as to solve the compatibling problem between QC and digital circuit based on BC；In addition, because the change-over circuit changes the big QC of identification difficulty for BC easy to identify, so QC identification circuit can be constituted using the change-over circuit and simple BC identification circuits, the complexity of QC application circuits can be so reduced, and then contribute to QC popularization and application.
Description
Four value clocks (Quaternary Clock, QC) are converted to two-value clock by technical field the present invention relates to one kind
The cmos circuit of (Binary Clock, BC).
Background technology digital circuitry include Clock Subsystem, and Clock Subsystem be divided into clock distributing network with
Trigger two parts[1].The Clock Subsystem of prior art is two-value Clock Subsystem.And multi-valued signal have contain much information[2-6]
The characteristics of, for example, four value clock signal QC have six saltus steps (edge) within a clock cycle, and traditional two-value clock BC
There was only saltus step twice in a cycle.Because the former the edge number within a clock cycle is three times of the latter, so number
Word circuit advantageously reduces system power dissipation using four value clocks as clock signal[6].In addition, the multi-valued signal ratio such as four value signals
Binary signal is more suitable for the novel nano electronic device design digital circuitry for having multiple working conditions with the next generation[6,7]。
For example, the new FET QDG-QDCFET reported first for 2012[8]Due to being more suitable for design with four working conditions
With realize four-valued logic[7].Therefore, four value clocks also set the nano electron device for being more suitable for and having multiple working conditions
Count digital circuitry.Based on the advantage of four value clocks, there is document [4-6] that four value clocks have been carried out with certain answer at present
With research.During research is using four value clocks, following two problems are occurred in that：First, with the number using two-value clock BC
The compatibling problem of word circuit system；2nd, how simply and effectively to recognize and make the application circuit of four value clocks using four value clocks
Simple question as far as possible.At present, the sequential part such as latch, trigger in existing digital circuit is almost all based on two-value
Clock BC and design, rather than four value clock QC.So occur the digital display circuit using four value clocks with using two-value clock
Digital display circuit the problem of clock signal is incompatible both when synchronizing data exchange.The difficult point for solving the problem is：
Four value clock QC six edges should be fully used, and can drive carry out work using two-value clock BC digital display circuit again
Make.The problem is not solved, and four value clock QC are just difficult to be goed deep into and be widely applied, and the advantage such as its low-power consumption is also difficult to show
It is existing.Further, since four value clock QC have four level values and six kinds of hopping edges, so detection and four value clocks of identification will be difficult to pass
The two-value clock BC of system.How to make four value clock QC readily identified and use, make its identification and application circuit as simple as possible, be
The Second Problem of four value clock QC applications.
Bibliography：
[1] Kim C., Kang S.M., A low-swing clock double-edge triggered flip-flop
[J] .IEEE Journal of Solid-State Circuits, 2002,37 (5)：648-652.
[2] Wu X., Prosser F.Design of ternary CMOS circuits based on
Transmission function theory [J], International Journal of Electronics, 1988,65
(5)：891-905.
[3] Prosser F., Wu X., Chen X., CMOS Ternary Flip-Flops ＆ Their
Applications [J] .IEE Proceedings on Computer ＆ Digital Techniques, 1988,135 (5)：
266-272.
[4] multiple value flip-flop [J], electronic letters, vol, 1997,25 are clapped Xia Yinshui, Wu Xunwei, multivalue clock and block form more
(8)：52-54.
[5] Xia Y.S., Wang L.Y., Almaini A.E.A., A Novel Multiple-Valued CMOS
Flip-Flop Employing Multiple-Valued Clock [J], Journal of Computer Science and
Technology, 2005,20 (2)：237-242.
[6] Lang Y.-F., Shen J.-Z., A general structure of all-edges-triggered
Flip-flop based on multivalued clock [J], International Journal of Electronics,
2013,100 (12)：1637-1645.
[7] Supriya Karmakar, Design of quaternary logic circuit using quantum
Dot gate-quantum dot channel FET (QDG-QDCFET) [J], International Journal of
Electronics, 2014,101 (10)：1427-1442.
[8] Jain, F., Karmakar, S., Chan, P.-Y., Suarez, E., Gogna, M., Chandy, J., ＆
Heller, E.Quantum Dot Channel (QDC) Field-Effect Transistors (FETs) using II-VI
Barrier layers [J] .Journal of Electronic Materials, 2012,41 (10), 2775-2784.
The content of the invention is for produced problem in above-mentioned four value clock QC applications, and task of the invention is exactly to keep four
Value clock QC advantages are on the premise of making full use of four value clocks, six saltus steps, to solve four value clock QC and two-value clock BC's
Compatibling problem, and the four value indiscernible problems of clock.
To complete invention task, a kind of CMOS that four value clock QC are converted to two-value clock BC of the invention is electric
Road.Four value clock QC six kinds of hopping edges are converted to two-value clock BC by the circuit on the premise of keeping clock edge number constant
Two kinds of hopping edges.
The present invention is adopted the technical scheme that：First, with reference to level logic value of the research papers to four value clock QC
Carry out classification summary；Then, on the premise of the edge number of holding clock is constant, four value clock QC four kinds of level logic values
Be converted to two kinds of level logic values；Finally, four value clock QC are converted to two according to theoretical realized with metal-oxide-semiconductor of transmission voltage switch
It is worth clock BC circuit.On the one hand the two-value clock BC of the circuit output can be used for numeral electricity of the driving tradition based on two-value clock
Road, solves four value clock QC compatibling problem；On the other hand, the two-value clock BC of output only has two level values, with one
Level threshold can just be recognized, solve the four indiscernible problems of value clock QC.
The above-mentioned circuit that four value clock QC are converted to two-value clock BC includes following technical characteristic：
A, the input signal of the circuit are one four value clock QC, and its level logic value is 0,1,2 and 3, four value clocks
Switch sequence is 0 → 1 → 2 → 3 → 2 → 1 → 0；
B, the output signal of the circuit are a two-value clock BC, and its level logic value is 0 and 3, the switching of two-value clock
Order is 0 → 3 → 0；
C, when four value clock QC input 0 or 2, two-value clock BC output levels logical value 0；
D, when four value clock QC input 1 or 3, two-value clock BC output levels logical value 3.
Circuit with above-mentioned technical characteristic can turn switch sequence for 0 → 1 → 2 → 3 → 2 → 1 → 0 four value clock QC
It is changed to the two-value clock BC that switch sequence is 0 → 3 → 0.It is can be seen that from the input/output signal of the circuit in certain period of time
Interior, the edge number of two kinds of clocks is identical, and the two-value clock BC of output is more readily identified than four value clock QC of input.Therefore,
The present invention can complete this invention task using the technical scheme comprising above-mentioned technical characteristic.
It is theoretical according to the technical characteristic of invention and transmission voltage switch[2,3], opening for above-mentioned circuit for switching between two clocks can be obtained
Level function expression is closed, as shown in formula (1), its input and output signal is respectively four value clock QC and two-value clock BC.
BC=0* (QC0.5+1.5QC·QC2.5)#3*(2.5QC+0.5QC·QC1.5). (1)
To be easy to realize formula (1) with metal-oxide-semiconductor, the expression formula conversion of switching stage is carried out to it.Switching stage function after conversion
Shown in expression formula such as formula (2).
Understood according to formula (2), it is necessary to use two four value phase inverters：One PMOS and threshold 0.5 by threshold -2.5
The value phase inverter of threshold 0.5 4, another threshold 2.5 being made up of the PMOS of threshold -0.5 and the NMOS tube of threshold 2.5 of NMOS tube composition
Four value phase inverters.In addition, also to use the NMOS tube of two thresholds 0.5, the NMOS tube of threshold 1.5, the PMOS of two thresholds -0.5
The PMOS of pipe and a threshold -1.5.The circuit that four value clocks are converted to two-value clock is may make up with this 10 metal-oxide-semiconductors, it is inputted
Termination four is worth clock QC, in output end output two-value clock BC.Because the circuit has used 10 metal-oxide-semiconductors altogether, so of the invention
Circuit it is simple.
The circuit for switching between two clocks can be converted to four value clock QC six kinds of edges two-value clock BC two kinds of edges, and
The edge number of two kinds of clocks is identical in the identical period.Thus take full advantage of four value clock QC six edges from
And the advantage of four value clocks is maintained, and the digital circuit using two-value clock can be driven.When this makes four value clock QC with two-value
Clock BC compatibling problem is resolved；And because the two-value clock BC of conversion output only has two level, when being worth than identification four
Clock QC four level are easy, therefore by clock conversion also to solve four value clock QC indiscernible for circuit of this invention
Problem.
From the above, it is seen that the circuit for switching between two clocks of invention had both solved four value clock QC and two-value clock BC's
Compatibling problem solves the four indiscernible problems of value clock QC again.So, can be used has four value clocks of low-power consumption advantage to drive
The dynamic digital circuit based on two-value clock, so as to reduce system power dissipation；In addition, the circuit for switching between two clocks output of this invention is
Two-value clock BC easy to identify, can so reduce the complexity using four value clock circuits, and then be conducive to pushing away for four value clocks
Wide application.
Brief description of the drawings is described in further detail to the present invention with reference to the accompanying drawings and detailed description.
Fig. 1 be input, output signal be respectively four value clock QC and two-value clock BC circuit for switching between two clocks CMOS lines
Lu Tu.
Fig. 2 is the voltage transient waveforms figure of four value clock QC and two-value clock BC in circuit shown in Fig. 1.
Embodiment is according to formula (2), and the switching stage that can obtain the circuit for switching between two clocks of this invention is realized, its
Line map as shown in figure 1, the circuit used two four value phase inverters of threshold 0.5 and 2.5, the NMOS tube of two thresholds 0.5, one
The PMOS of the NMOS tube of threshold 1.5, the PMOS of two thresholds -0.5 and a threshold -1.5, totally 10 metal-oxide-semiconductors.Its operation principle
For：It is worth clock in input (QC) access four：0 → 1 → 2 → 3 → 2 → 1 → 0, just export two-value clock in output end (BC)：0
→3→0.The two-value clock BC that level logic value meets inventive technique feature can be obtained easily using the present invention.Therefore, this hair
Bright circuit for switching between two clocks is simple in construction, easy to use.
To verify the circuit for switching between two clocks of this invention, it is simulated with HSPICE softwares below.Used during simulation
TSMC 180nm CMOS technology parameter, output loading is 30fF.The four level logic values 0,1,2 and 3 correspondences of four value clocks
Magnitude of voltage be respectively 0V, 1.67V, 3.33V and 5.0V；The corresponding magnitude of voltage point of two level logic values 0 and 3 of two-value clock
Wei not 0V and 5.0V.Voltage transient waveforms obtained by simulation are as shown in Fig. 2 wherein QC and BC are respectively circuit for switching between two clocks input
Four value clocks and output two-value clock.Fig. 2 analog result shows, the present invention can be 0 → 1 → 2 → 3 switch sequence →
2 → 1 → 0 four value clocks are converted to the two-value clock that switch sequence is 0 → 3 → 0, realize the skill proposed in the content of the invention
Art feature.
Summarize：The circuit for switching between two clocks of this invention has correct function, can all turn six saltus steps of four value clocks
The saltus step of two-value clock is changed to, the number of transitions of two kinds of clocks is kept constant, solves two run into the application of four value clocks
Problem, completes invention task.The present invention has only used 10 metal-oxide-semiconductors, and circuit is simple；And HSPICE software analog result tables
Bright, circuit of the invention is stable and reliable in work.Finally it is noted that the present invention is applicable to four value clocks being converted to two
Value clock and it must export 0 when four value clocks input 0 or 2 and 3 clock conversion must be exported when four value clocks input 1 or 3 and is answered
Use occasion.
Claims (1)
1. a kind of cmos circuit that four value clocks are converted to two-value clock, it has a four value input end of clock QC and one two
It is worth output terminal of clock BC, the function of the cmos circuit is that four value clock level logical values 0 and 2 are converted to two-value clock level
Logical value 0 and four value clock level logical values 1 and 3 are converted to two-value clock level logical value 3, i.e., level in a cycle
Logical value switch sequence is converted to level logic value switching time in a cycle for 0 → 1 → 2 → 3 → 2 → 1 → 0 four value clocks
Sequence exports for 0 → 3 → 0 two-value clock；
The cmos circuit that four value clocks are converted into two-value clock is characterised by：It includes the NMOS tube of a threshold 2.5
N1, NMOS tube N2, N4 and N5 of three thresholds 0.5, the NMOS tube N3 of threshold 1.5, PMOS P1, P2 of three thresholds -0.5 and
P4, the PMOS P3 of threshold -1.5 and the PMOS P5 of a threshold -2.5；Described metal-oxide-semiconductor P1, N1, P3, N3, P5 and N5 grid
Pole connects with circuit input end QC, and metal-oxide-semiconductor P1, P2, P3 and P5 source electrode connect with the signal source of level logic value 3, P1 and N1
Drain electrode connect with P2 and N2 grid, N1, N3, N4 and N5 source electrode connects with ground, and P2, N2, P4 and N4 drain electrode connects work
Source electrode for the output end BC, N2 of circuit connects with N3 drain electrode, and P3 drain electrode connects with P4 source electrode, P5 and N5 drain electrode with
P4 and N4 grid connects.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410648014.4A CN104467805B (en) | 2014-11-14 | 2014-11-14 | A kind of QC BC03 change-over circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410648014.4A CN104467805B (en) | 2014-11-14 | 2014-11-14 | A kind of QC BC03 change-over circuit |
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| Publication Number | Publication Date |
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| CN104467805A CN104467805A (en) | 2015-03-25 |
| CN104467805B true CN104467805B (en) | 2017-08-01 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104050305A (en) * | 2013-07-03 | 2014-09-17 | 浙江工商大学 | TC (Ternary Clock)-BC (Binary Clock) conversion circuit unit |
| CN104052434A (en) * | 2013-07-03 | 2014-09-17 | 浙江工商大学 | Clock conversion circuit |
| US8847625B2 (en) * | 2012-02-16 | 2014-09-30 | Southern Methodist University | Single clock distribution network for multi-phase clock integrated circuits |
-
2014
- 2014-11-14 CN CN201410648014.4A patent/CN104467805B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8847625B2 (en) * | 2012-02-16 | 2014-09-30 | Southern Methodist University | Single clock distribution network for multi-phase clock integrated circuits |
| CN104050305A (en) * | 2013-07-03 | 2014-09-17 | 浙江工商大学 | TC (Ternary Clock)-BC (Binary Clock) conversion circuit unit |
| CN104052434A (en) * | 2013-07-03 | 2014-09-17 | 浙江工商大学 | Clock conversion circuit |
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| CN104467805A (en) | 2015-03-25 |
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