CN104467758B - A kind of QB31 circuit unit - Google Patents
A kind of QB31 circuit unit Download PDFInfo
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- CN104467758B CN104467758B CN201410648063.8A CN201410648063A CN104467758B CN 104467758 B CN104467758 B CN 104467758B CN 201410648063 A CN201410648063 A CN 201410648063A CN 104467758 B CN104467758 B CN 104467758B
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Abstract
A kind of QB31 circuit unit of the invention, the circuit unit can produce BC31 signals with QC signals, and the circuit unit is made up of the PMOS of the NMOS tube of two thresholds 1.5, the NMOS tube of two thresholds 0.5, the PMOS of three thresholds 0.5, the PMOS of threshold 1.5 and two thresholds 2.5；Value of the invention is that：The circuit unit can produce BC31 signals that are readily identified and using on the premise of ensuring that signal useful information is not lost with QC signals；It on the one hand can so use QC signals to go to drive the circuit system based on BC31 signals, on the other hand also solve the compatibling problem between QC signals and BC31 signals；In addition, because the circuit unit has produced BC31 signals easy to identify with indiscernible QC signals, so the identification circuit of QC signals can be constituted using the circuit module of the circuit unit and identification BC31 signals, the complexity of QC signal application circuits can be so reduced, so as to contribute to the popularization and application of QC signals.
Description
Four value clocks (Quaternary Clock, QC) are converted to two-value clock by technical field the present invention relates to one kind
The cmos circuit of (Binary Clock, BC).
Background technology digital circuitry include Clock Subsystem, and Clock Subsystem be divided into clock distributing network with
Trigger two parts[1].The Clock Subsystem of prior art is two-value Clock Subsystem.And multi-valued signal has what is contained much information
Feature[2-6], for example, four value clock signal QC have six saltus steps (edge) in a cycle[6], and traditional two-value clock BC
There was only saltus step twice in a cycle.Because the former the edge number in a cycle is three times of the latter, so numeral electricity
Road advantageously reduces system power dissipation using four value clocks[6].In addition, the multi-valued signal such as four value signals than binary signal be more suitable for
The novel nano electronic device design digital circuitry of multivalue of future generation[6,7].For example, the New Type Field effect reported first for 2012
Should pipe QDG-QDCFET[8]Due to being particularly suited for designing and realizing four-valued logic with four working conditions[7].Cause
This, four value clocks will also be more suitable for designing digital circuitry with the nano electron device of multivalue.Based on the advantage of four value clocks,
There is document [4-6] to carry out certain application study to four value clocks at present.During research four is worth clock application,
Occur in that following two problems：First, with the compatibling problem of two-value clock；2nd, how efficiently to recognize and using four value clocks, make
The application circuit simple question as far as possible of four value clocks.At present, prelude during latch, trigger in existing digital circuit etc.
Part is almost all based on two-value clock and designed, rather than four value clocks.The digital display circuit using four value clocks so occurs
The problem of clock signal is incompatible both when synchronizing data exchange with the digital display circuit using two-value clock.This is solved to ask
The difficult point of topic is：Six edges of four value clocks should be fully used, and the numeral using two-value clock can be driven again
System is operated.The problem is not solved, and four value clocks are just difficult to be goed deep into and be widely applied, the advantage such as its low-power consumption
It is difficult to show.Further, since four value clocks have four level values and six kinds of hopping edges, so detection and identification four, which are worth clock, wants hardly possible
In traditional two-value clock.How to make four value clocks readily identified and use, make its identification and application circuit as simple as possible, be
The Second Problem of four value clock applications.
Bibliography：
[1] Kim C., Kang S.M., A low-swing clock double-edge triggered flip-flop
[J] .IEEE Journal of Solid-State Circuits, 2002,37 (5)：648-652.
[2] Wu X., Prosser F.Design of ternary CMOS circuits based on
Transmission function theory [J], International Journal of Electronics, 1988,65
(5)：891-905.
[3] Prosser F., Wu X., Chen X., CMOS Ternary Flip-Flops ＆ Their
Applications [J] .IEE Proceedings on Computer ＆ Digital Techniques, 1988,135 (5)：
266-272.
[4] multiple value flip-flop [J], electronic letters, vol, 1997,25 are clapped Xia Yinshui, Wu Xunwei, multivalue clock and block form more
(8)：52-54.
[5] Xia Y.S., Wang L.Y., Almaini A.E.A., A Novel Multiple-Valued CMOS
Flip-Flop Employing Multiple-Valued Clock [J], Journal of Computer Science and
Technology, 2005,20 (2)：237-242.
[6] Lang Y.-F., Shen J.-Z., A general structure of all-edges-triggered
Flip-flop based on multivalued clock [J], International Journal of Electronics,
2013,100 (12)：1637-1645.
[7] Supriya Karmakar, Design of quaternary logic circuit using quantum
Dot gate-quantum dot channel FET (QDG-QDCFET) [J], International Journal of
Electronics, 2014,101 (10)：1427-1442.
[8] Jain, F., Karmakar, S., Chan, P.-Y., Suarez, E., Gogna, M., Chandy, J., ＆
Heller, E.Quantum Dot Channel (QDC) Field-Effect Transistors (FETs) using II-
VIbarrier layers [J] .Journal of Electronic Materials, 2012,41 (10), 2775-2784.
The content of the invention is for produced problem in above-mentioned four value clock QC applications, and task of the invention is exactly to keep four
Value clock QC advantages are on the premise of making full use of four value clocks, six saltus steps, to solve between four value clock QC and two-value clock BC
Compatibling problem, and four value the indiscernible problems of clock.
To complete invention task, a kind of CMOS that four value clock QC are converted to two-value clock BC of the invention is electric
Road.Four value clock QC six kinds of hopping edges are converted to two-value clock BC by the circuit on the premise of keeping clock edge number constant
Two kinds of hopping edges.
The present invention is adopted the technical scheme that：First, with reference to level logic value of the research papers to four value clock QC
Carry out classification summary；Then, on the premise of the edge number of holding clock is constant, four value clock QC four kinds of level logic values
Be converted to two kinds of level logic values；Finally, four value clock QC are converted to two according to theoretical realized with metal-oxide-semiconductor of transmission voltage switch
It is worth clock BC circuit.On the one hand the two-value clock BC of the circuit output can be used for numeral electricity of the driving tradition based on two-value clock
Road, solves four value clock QC compatibling problem；On the other hand, the two-value clock BC of output only has two level values, with one
Level threshold can just be recognized, solve the four indiscernible problems of value clock QC.
The above-mentioned circuit that four value clock QC are converted to two-value clock BC includes following technical characteristic：
A, the input signal of the circuit are one four value clock QC, and its level logic value is 0,1,2 and 3, four value clocks
Switch sequence is 0 → 1 → 2 → 3 → 2 → 1 → 0；
B, the output signal of the circuit are a two-value clock BC, and its level logic value is 3 and 1, the switching of two-value clock
Order is 3 → 1 → 3；
C, when four value clock QC input 0 or 2, two-value clock BC output levels logical value 3；
D, when four value clock QC input 1 or 3, two-value clock BC output levels logical value 1.
Circuit with above-mentioned technical characteristic can turn switch sequence for 0 → 1 → 2 → 3 → 2 → 1 → 0 four value clock QC
It is changed to the two-value clock BC that switch sequence is 3 → 1 → 3.It is can be seen that from the input/output signal of the circuit in certain period of time
Interior, the edge number of two kinds of clocks is identical, and the two-value clock BC of output is more readily identified than four value clock QC of input.Therefore,
The present invention can complete this invention task using the technical scheme comprising above-mentioned technical characteristic.
It is theoretical according to above-mentioned technical characteristic and transmission voltage switch[2,3], opening for above-mentioned circuit for switching between two clocks can be obtained
Level function expression is closed, as shown in formula (1), its input and output signal is respectively four value clock QC and two-value clock BC.
BC=3* (QC0.5+1.5QC·QC2.5)#1*(0.5QC·QC1.5+2.5QC). (1)
To be easy to realize formula (1) with metal-oxide-semiconductor, the expression formula conversion of switching stage is carried out to it.Switching stage function after conversion
Shown in expression formula such as formula (2).
Understood according to formula (2), it is necessary to use the NMOS tube of two thresholds 1.5, the NMOS tube of two thresholds 0.5, three thresholds -0.5
PMOS, the PMOS of the PMOS of threshold -1.5 and two thresholds -2.5.Four value clocks are may make up with this 10 metal-oxide-semiconductors to turn
The circuit of two-value clock is changed to, it inputs termination four and is worth clock QC, in output end output two-value clock BC.Because the circuit makes altogether
With 10 metal-oxide-semiconductors, so the circuit of the present invention is simple.
The circuit for switching between two clocks can be converted to four value clock QC six kinds of edges two-value clock BC two kinds of edges, and
The edge number of two kinds of clocks is identical in the identical period.Thus take full advantage of four value clock QC six edges from
And the advantage of four value clocks is maintained, and the digital circuit using two-value clock can be driven.When this makes four value clock QC with two-value
Clock BC compatibling problem is resolved；And because the two-value clock BC of conversion output only has two level, when being worth than identification four
Clock QC four level are easy, therefore by clock conversion also to solve four value clock QC indiscernible for circuit of this invention
Problem.
From the above, it is seen that the circuit for switching between two clocks of invention had both solved four value clock QC and two-value clock BC's
Compatibling problem solves the four indiscernible problems of value clock QC again.So, can be used has four value clocks of low-power consumption advantage to drive
The dynamic digital circuit based on two-value clock, so as to reduce system power dissipation；In addition, the circuit for switching between two clocks output of this invention is
Two-value clock BC easy to identify, can so reduce the complexity using four value clock circuits, and then be conducive to pushing away for four value clocks
Wide application.
Brief description of the drawings is described in further detail to the present invention with reference to the accompanying drawings and detailed description.
Fig. 1 be input, output signal be respectively four value clock QC and two-value clock BC circuit for switching between two clocks CMOS lines
Lu Tu.
Fig. 2 is the voltage transient waveforms figure of four value clock QC and two-value clock BC in circuit shown in Fig. 1.
Embodiment is according to formula (2), and the switching stage that can obtain the circuit for switching between two clocks of this invention is realized, its
Line map is as shown in figure 1, the circuit has used the NMOS tube of two thresholds 1.5, the NMOS tube of two thresholds 0.5, three thresholds -0.5
The PMOS of PMOS, the PMOS of threshold -1.5 and two thresholds -2.5, totally 10 metal-oxide-semiconductors.Its operation principle is：In input
(QC) access four is held to be worth clock：0 → 1 → 2 → 3 → 2 → 1 → 0, just export two-value clock in output end (BC)：3→1→3.Profit
The two-value clock BC that level logic value meets inventive technique feature can be obtained easily with the present invention.If it is followed by threshold 1.5 4
It is worth phase inverter, then the two-value clock that the cycle is 0 → 3 → 0 can be obtained.Therefore, circuit for switching between two clocks structure of the invention letter
It is single, it is easy to use.
To verify the circuit of this invention, it is simulated with HSPICE softwares below.Simulate the technique that uses for
TSMC 180nm CMOS, output loading is 30fF.The corresponding magnitude of voltage in four level logic values 0,1,2 and 3 point of four value clocks
Wei not 0V, 1.67V, 3.33V and 5.0V；The corresponding magnitude of voltage of two level logic values 1 and 3 of two-value clock is respectively 1.67V
And 5.0V.Voltage transient waveforms obtained by simulation are as shown in Fig. 2 wherein QC and BC are respectively four value clocks of invention circuit input
With the two-value clock of output.Fig. 2 analog result shows that the present invention can be four values that the cycle is 0 → 1 → 2 → 3 → 2 → 1 → 0
Clock is converted to the two-value clock that the cycle is 3 → 1 → 3, realizes the technical characteristic proposed in the content of the invention.
Summarize：The circuit for switching between two clocks of this invention has correct function, can all turn six saltus steps of four value clocks
The saltus step of two-value clock is changed to, the number of transitions of two kinds of clocks is kept constant, solves two run into the application of four value clocks
Problem, completes invention task.The present invention has only used 10 metal-oxide-semiconductors, and circuit is simple；And HSPICE software analog result tables
Bright, circuit of the invention is stable and reliable in work.Finally it is noted that the present invention is applicable to four value clocks being converted to two
Value clock and it must export 3 when four value clocks input 0 or 2 and 1 clock conversion must be exported when four value clocks input 1 or 3 and is answered
Use occasion.
Claims (1)
1. a kind of cmos circuit that four value clocks are converted to two-value clock, the cmos circuit has a four value input end of clock
Four value clock level logical values 0 and 2 can be converted to two-value clock by QC and two-value output terminal of clock BC, the cmos circuit
Level logic value 3 and four value clock level logical values 1 and 3 can be converted to two-value clock level logical value 1；I.e. described CMOS electricity
The four value clocks that level logic value switch sequence in a cycle is 0 → 1 → 2 → 3 → 2 → 1 → 0 can be converted to a week by road
Level logic value switch sequence is 3 → 1 → 3 two-value clock in phase；
The cmos circuit is characterised by：It includes the NMOS tube N2 of NMOS tube N1 and N4 of two thresholds 1.5, two thresholds 0.5
With the PMOS P2 of N3, the PMOS P1 of threshold -1.5, PMOS P3, P4 and P5 of three thresholds -0.5 and two thresholds -2.5 and
P6, described P1, P2, P3, P6, N1, N2 and N4 grid connect with circuit input end QC, described P1, P2, P3 and P6 source electrode with
The voltage source of level logic value 3 connects, and N1 and N2 source electrode connect with power supply, N4 and P5 source electrode and level logic value 1
Voltage source connects, and P1 and N1 drain electrode connect with P4 and N3 grid, and P2 and N2 drain electrode connect with P5 grid, P3 drain electrode
Connect with P4 source electrode, N3 source electrode connects with P5 drain electrode, the output end that P4, N3, P6 and N4 drain electrode connects as circuit
BC。
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|---|---|---|---|
| CN201410648063.8A CN104467758B (en) | 2014-11-14 | 2014-11-14 | A kind of QB31 circuit unit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410648063.8A CN104467758B (en) | 2014-11-14 | 2014-11-14 | A kind of QB31 circuit unit |
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| CN104467758A CN104467758A (en) | 2015-03-25 |
| CN104467758B true CN104467758B (en) | 2017-09-26 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7755391B2 (en) * | 2006-01-31 | 2010-07-13 | Japan Advanced Institute Of Science And Technology | Three-valued logic function circuit |
| CN102624380A (en) * | 2012-04-13 | 2012-08-01 | 南通大学 | Three-position reversible ternary-binary logic converter |
| CN104052434A (en) * | 2013-07-03 | 2014-09-17 | 浙江工商大学 | Clock conversion circuit |
-
2014
- 2014-11-14 CN CN201410648063.8A patent/CN104467758B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7755391B2 (en) * | 2006-01-31 | 2010-07-13 | Japan Advanced Institute Of Science And Technology | Three-valued logic function circuit |
| CN102624380A (en) * | 2012-04-13 | 2012-08-01 | 南通大学 | Three-position reversible ternary-binary logic converter |
| CN104052434A (en) * | 2013-07-03 | 2014-09-17 | 浙江工商大学 | Clock conversion circuit |
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| CN104467758A (en) | 2015-03-25 |
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Effective date of registration: 20170817 Address after: 310018 No. 508, No. 2, Hangzhou economic and Technological Development Zone, Zhejiang Applicant after: Zhejiang University of Water Resources and Electric Power Address before: Hangzhou City, Zhejiang Province, Xihu District staff road 310012 No. 149 Applicant before: Zhejiang Gongshang University |
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Granted publication date: 20170926 Termination date: 20181114 |