CN104639112A - QCG (quaternary clock generator) circuit consisting of TFFs (T flip-flops) - Google Patents

Abstract

The invention relates to a design problem of a QCG (quaternary clock generator) circuit consisting of TFFs (T flip-flops). A QC (quaternary clock) has the greater information amount, so the QC is applied to the relevant research literature, and shows certain advantages. In the prior art, QC signals are generated only through simulation software emulation, and no simple and practical integrated circuit capable of generate QC signals exists at home and abroad. The invention relates to a QC signal generating circuit, i.e., a QCG circuit based on TFFs. The QCG circuit mainly consists of a gate circuit, two kinds of TFFs and an MOS (metal oxide semiconductor) tube. The problem that the integrated circuit cannot generate QC signals in the prior art is solved by the QCG circuit consisting of the TFFs, so that the QC signals can be practically applied. Simulation shows that the function of the QCG circuit consisting of the TFFs is correct, and in addition, the circuit analysis shows that the circuit structure is simple, the performance is high, and in addition, the practical application to the circuit is easy.

Description

With the QCG circuit of TFF composition

Technical field the present invention relates to a kind of four value clocks (Quaternary Clock is called for short QCLK or QC) be made up of gate circuit, two kinds of T triggers (TFF) and metal-oxide-semiconductor and produces circuit.

Background technology has abundant amount of information due to four value clock QCLK, it has six kinds of hopping edges in a clock cycle, much more than traditional two-value clock of the kind of its hopping edge and quantity, so have the features such as structure is simple and low in energy consumption based on the trigger of four value clocks ^[1].

From prior art, document [1] proposes six edge triggered flip flops based on four value clock QCLK, and document [2,3] also utilizes the multiple value flip-flop that four value Clock Designs are relevant.As can be seen from relevant Research Literature, four value clock QCLK have obtained practicable application and have shown its superiority in digital circuit.But the four value clocks used in above-mentioned document have a common feature, the four value clocks be namely used to are all produce with simulation software simulation, but not are produced by the integrated circuit of reality.Investigation finds, there is no Research Literature at present and mention that generation four is worth the method for clock QCLK and relevant circuit, also namely, one simple and four of practicality value clock generators (Quaternary Clock Generator is called for short QCG) are also a vacancy at present.And clock is most important signal in digital system, the effect in sequence circuit controls and coordinate whole digital system normally to work.Two-value clock signal can be produced by quartz crystal multivibrator, and four value clocks can only be produced by simulation software simulation at present.Restriction four is worth the practical application of clock by this, also will be difficult to obtain practicality in document [1-3] based on the trigger of four value clocks.

For solving the problem do not had at present in four these practical applications of value clock generator QCG, the two-value clock that the present invention utilizes quartz oscillator or phase-locked loop etc. to produce is as input signal, and application transport voltage switch is theoretical ^[4,5]invent the QCG circuit of a kind of generation four value clocks from switching stage etc. knowledge, the QCG circuit of invention wants that circuit is simple, working stability is efficient and practical, to solve the problem not having four value clock generator QCG circuit at present.

List of references:

[1]Lang，Y.-F.，Shen，J.-Z..A general structure of all-edges-triggered flip-flop based on multivalued clock，International Journal of Electronics，2013，100，(12)，pp.1637-1645.

[2] Xia Yinshui, Wu Xunwei, many-valued clock and block form many bats multiple value flip-flop, electronic letters, vol, 1997,25, (8), pp.52-54.

[3]XiaY.S.，Wang L.Y.，Almaini A.E.A.，A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock，Journal of Computer Science and Technology，2005，20，(2)，pp.237-242.

[4]Wu，X.，Prosser，F..Design of ternary CMOS circuits based on transmission function theory，International Journal of Electronics，1988，65，(5)，pp.891-905.

[5]Prosser，F.，Wu，X.，Chen，X.CMOS Ternary Flip-Flops & Their Applications.IEE Proceedings on Computer & Digital Techniques，1988，135，(5)，pp.266-272.

Summary of the invention is for the problem that can not produce four value clocks at present with simple integrated circuit, namely the problem of QCG circuit is not had, content of the present invention creates the QCG circuit that one can produce the four value clock QCLK used in document [1] exactly, and the QCG circuit of invention is wanted, and structure is simple, efficient work, and its input/output signal will meet following four requirements:

1) the QCG circuit invented has two input signals: two-value clock CLK and inverted signal thereof their logical value values be 0,3} and duty ratio is 50%, namely the time ratio of low and high level is 1: 1;

2) the QCG circuit invented has an output signal: four value clock QCLK, and its level logic value value is { 0,1,2,3}, within a clock cycle, the output order of its level logic value is 0 → 1 → 2 → 3 → 2 → 1 → 0, and the duration of each output level is equal;

3) frequency ratio of four value clock QCLK of the two-value clock CLK inputted and output is 3: 1;

4) four value clock QCLK need meet the requirement about clock signal, and the four value clock QCLK that namely QCG circuit produces should have high frequency and range stability;

Accompanying drawing illustrates and is described in further detail the present invention below in conjunction with the drawings and specific embodiments.

Fig. 1 is the line map of the QCG circuit that the present invention TFF forms.

Fig. 2 is two-value clock CLK, signal Q ₀and Q ₁time-sequential voltage waveform schematic diagram.

Fig. 3 be input in circuit shown in Fig. 1 two-value clock CLK, trigger FF0 output signal Q ₀with the output signal Q of FF1 ₁with the voltage transient waveforms figure of the four value clock QCLK exported.

Embodiment the present invention utilizes logical value to switch to the two-value clock CLK of 0 → 3 → 0 to produce the four value clock QCLK that logical value sequence is 0 → 1 → 2 → 3 → 2 → 1 → 0.According to the switch law of clock signal logic value ^[1], the logical value 3 of the present invention's two-value clock CLK controls the logical value 1 and 3 that generation four is worth clock QCLK; And control by the logical value 0 of two-value clock CLK the logical value 0 and 2 that generation four is worth clock QCLK.Because the logical value switch sequence of four value clock QCLK is 0 → 1 → 2 → 3 → 2 → 1 → 0, thus as CLK=3 four be worth clock QCLK generation unit will output logic value 1,3 and 1 in turn successively; As CLK=0, it then will output logic value 2,0 and 2 successively in turn.For this reason, two auxiliary control signal Q are also needed ₀and Q ₁realize thisly exporting in turn, use Q ₀3 and 0 output controlling four value clocked logic values 3 and 1 respectively; Use Q ₁3 and 0 output controlling four value clocked logic values 2 and 0 respectively.Q ₀and Q ₁low level should be respectively 2: 1 and 1: 2 with the ratio of the duration of high level, i.e. Q ₀and Q ₁duty ratio be respectively 33.3% and 66.7%.Like this, at two-value clock CLK and signal Q ₀and Q ₁control under just can produce the four value clock QCLK that logical value sequence is 0 → 1 → 2 → 3 → 2 → 1 → 0.The present invention T trigger carries out frequency division to obtain signal Q to two-value clock CLK ₀and Q ₁.Consider that the effective edge of two-value clock CLK in side circuit is along the output signal Q with trigger ₀and Q ₁between have clock output delay, this postpone by export four value clock waveforms in produce burr, be cancellation burr, output signal Q ₀and Q ₁should respectively in trailing edge and the rising edge place change state of two-value clock CLK.In summary, signal Q ₀and Q ₁it is the three frequency division signal of two-value clock CLK.Two-value clock CLK and signal Q ₀and Q ₁timing waveform schematic diagram as shown in Figure 2.

For obtaining Q by two-value clock CLK ₀and Q ₁two signals, the present invention adopts two two inputs or door (G1 and G2), the T trigger (FF0) of a trailing edge triggering and the T trigger (FF1) of a rising edge triggering to form the three frequency division circuit of two-value clock CLK.Described T trigger FF0 and FF1 exports the three frequency division output signal Q changing state at CLK falling edge and rising edge place respectively ₀and Q ₁, signal with q respectively ₀and Q ₁inverted signal.In the present invention, the connection situation of described three frequency division circuit is as shown in the left circuit in Fig. 1, and its circuit design specifically describes and is: signal Q ₀and Q ₁two inputs of access or door G1, the output access signal T of G1 ₀, output signal with two inputs of access or door G2, the output access signal T of G2 ₁; This that is, the input signal expression formula of described T trigger FF0 and FF1 is respectively T ₀=Q ₀+ Q ₁with the clock signal of described trigger FF0 and FF1 is the two-value clock CLK of input.Like this, trigger FF0 is responsive to the trailing edge of CLK, and it outputs signal Q ₀be the three frequency division signal of two-value clock CLK and Q ₀low level be 2: 1 with the ratio of the duration of high level; Trigger FF1 is responsive to the rising edge of CLK, and it outputs signal Q ₁also be two-value clock CLK three frequency division signal and Q ₁low level and the Duration Ratio of high level be 1: 2.Signal Q ₀and Q ₁generation four required for the present invention is exactly worth the control signal of clock QCLK.There is the control signal producing four value clock QCLK, according to the transmission voltage switching theorem in summary of the invention and document [4,5], listed four value clock QCLK and two-value clock CLK, signal with switching stage function expression:

$\mathrm{QCLK}=3*({\stackrel{\‾}{\mathrm{CLK}}}^{0.5}\·{{\stackrel{\‾}{Q}}_0}^{0.5})\#2*({\mathrm{CLK}}^{0.5}\·{{\stackrel{\‾}{Q}}_1}^{0.5})\#1*{(}^{0.5}\mathrm{CLK}{\·}^{0.5}\stackrel{\‾}{Q_0})\#0*{(}^{0.5}\stackrel{\‾}{\mathrm{CLK}}{\·}^{0.5}\stackrel{\‾}{Q_1}).$

For realizing described QCLK function expression, the circuit that the present invention adopts four PMOS (P1, P2, P3 and P4) and four NMOS tube (N1, N2, N3 and N4) to form generation four to be worth clock QCLK, namely produces the metal-oxide-semiconductor network of four value clocks.The connection situation of this partial circuit is as shown in the right circuit in Fig. 1, its circuit design specifically describes as follows: source electrode and the drain electrode of described PMOS P1 connect with the signal source of level logic value 3 and the source electrode of described PMOS P2 respectively, source electrode and the drain electrode of described PMOS P3 connect with the signal source of level logic value 2 and the source electrode of described PMOS P4 respectively, source electrode and the drain electrode of described NMOS tube N1 connect with the signal source of level logic value 1 and the source electrode of described NMOS tube N2 respectively, the source electrode of described NMOS tube N3 and drain electrode respectively with power supply connect with the source electrode of described NMOS tube N4, described metal-oxide-semiconductor P2, P4, the drain electrode of N2 and N4 connects as the output of four value clock QCLK, described metal-oxide-semiconductor P1, P2, P3, P4, N1, N2, the grid of N3 and N4 respectively with signal cLK, cLK, with being connected, under the control of these signals, is the four value periodic signals i.e. four value clock QCLK of 0 → 1 → 2 → 3 → 2 → 1 → 0 in circuit output end output level logical value switch sequence.

Known in sum, giving the input of the circuit shown in Fig. 1 two-value clock CLK and its inverted signal just can obtain the four value clock QCLK that logical value switches to 0 → 1 → 2 → 3 → 2 → 1 → 0 at the output QCLK place of this circuit.Therefore, the circuit shown in Fig. 1 is the QCG circuit that the present invention TFF forms.For the QCG circuit of checking invention, with HSPICE software, it is simulated below.Adopt the CMOS technology parameter of TSMC 180nm during simulation, output loading is 30fF.The magnitude of voltage of two level logic values 0 and 3 correspondence of two-value clock CLK is respectively 0V and 3.3V; The magnitude of voltage of four level logic values 0,1,2 and 3 correspondence of four value clock QCLK is respectively 0V, 1.1V, 2.2V and 3.3V.The voltage transient waveforms of the QCG breadboardin gained of described TFF composition as shown in Figure 3, wherein CLK, Q ₀, Q ₁the four value clock waveforms that the signal exported with the signal that QCLK is respectively two-value clock, FF0 exports, FF1 and QCG circuit of the present invention export.The analog result of Fig. 3 shows, namely the present invention has correct logic function with the QCG circuit of TFF composition.

Sum up: because the present invention only employs two T triggers, two gate circuits and eight metal-oxide-semiconductors, and can manufacture by CMOS technology conventional at present, so the present invention is namely simple with the QCG circuit structure of TFF composition.By analysis, the QCG circuit energy self-starting of described TFF composition, and the level value of four value clocks is the metal-oxide-semiconductor output formation of voltage source through conducting, therefore working stability of the present invention is efficient.In a word, with the QCG circuit of TFF composition, there is correct logic function, solve the problem not having actual integrated circuit to produce four value clocks at present.Filled up the blank of four value clock generator QCG, this illustrates that the present invention has novelty, creativeness and practicality, meets the regulation that Patent Law is granted patent.

Claims (1)

1. with a QCG circuit for TFF composition, by two-value clock CLK and the inverted signal thereof of input produce the four value clock QCLK that sequence is 0 → 1 → 2 → 3 → 2 → 1 → 0, it comprise two two inputs or door (G1 and G2), the T trigger (FF1) that T trigger (FF0) that trailing edge triggers, rising edge trigger, four PMOS (P1, P2, P3 and P4) and four NMOS tube (N1, N2, N3 and N4), first, with described T trigger FF0 and FF1, three frequency division is carried out to two-value clock CLK, obtain the three frequency division output signal Q changing state at CLK falling edge and rising edge place respectively ₀and Q ₁, their duty ratio is respectively 33.3% and 66.7%, signal with q respectively ₀and Q ₁inverted signal, then, the metal-oxide-semiconductor network of clock is worth with the generation four of described eight metal-oxide-semiconductors composition, its circuit is that the source electrode of described PMOS P1 connects with the signal source of logical value 3 and the source electrode of described PMOS P2 respectively with drain electrode, source electrode and the drain electrode of described PMOS P3 connect with the signal source of logical value 2 and the source electrode of described PMOS P4 respectively, source electrode and the drain electrode of described NMOS tube N1 connect with the signal source of logical value 1 and the source electrode of described NMOS tube N2 respectively, the source electrode of described NMOS tube N3 and drain electrode respectively with power supply connect with the source electrode of described NMOS tube N4, described metal-oxide-semiconductor P2, P4, the drain electrode of N2 and N4 links together as the output of four value clock QCLK, finally, with CLK, with control described metal-oxide-semiconductor network and produce four value clock QCLK,

The QCG circuit of described TFF composition, is characterized in that: the input signal expression formula of described T trigger FF0 and FF1 is respectively T ₀=Q ₀+ Q ₁with described two expression formulas are embodied as signal Q on circuit ₀and Q ₁two inputs of access or door G1, the output access signal T of G1 ₀, output signal with two inputs of access or door G2, the output access signal T of G2 ₁; The signal controlling described metal-oxide-semiconductor network specifically connects for signal cLK, cLK, with connect with the grid of described metal-oxide-semiconductor P1, P2, P3, P4, N1, N2, N3 and N4 respectively.