CN104639110A - QCG (quaternary clock generator) unit consisting of RSFF (reset set flip-flop) - Google Patents

QCG (quaternary clock generator) unit consisting of RSFF (reset set flip-flop) Download PDF

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CN104639110A
CN104639110A CN201510096472.6A CN201510096472A CN104639110A CN 104639110 A CN104639110 A CN 104639110A CN 201510096472 A CN201510096472 A CN 201510096472A CN 104639110 A CN104639110 A CN 104639110A
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value
signal
flop
qcg
set flip
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CN104639110B (en
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不公告发明人
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Zhejiang University of Water Resources and Electric Power
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Zhejiang Gongshang University
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/038Multistable circuits

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Abstract

The invention relates to the circuit design problem of a QCG (quaternary clock generator) unit consisting of an RSFF (reset set flip-flop). A QC (quaternary clock) has the great information amount, so the QC is applied to relevant research literatures and shows certain advantages. In the prior art, QC signals are only generated through simulation software through emulation, and no simple and practical integrated circuit capable of generating QC signals exists at home and abroad. The invention provides a circuit, i.e., a QCG unit using the RSFF and a MOS (metal oxide semiconductor) tube to generate QC signals. The QCG unit consisting of the RSFF solves the problem that the QC signals cannot be generated by the integrated circuit in the prior art, so that the QC signals can be practically applied. Simulation shows that the function of the QCG unit consisting of the RSFF is correct, and in addition, the circuit analysis shows that the circuit structure is simple, the performance is high, and in addition, the practical application to circuits is easy.

Description

A kind of QCG unit be made up of RSFF
Technical field the present invention relates to the circuit unit that a kind of generation four be made up of rest-set flip-flop (RSFF) and the metal-oxide-semiconductor of two kinds of triggering edge is worth clock (Quaternary Clock is called for short QCLK or QC).
Background technology has abundant amount of information due to four value clock QCLK, it has six kinds of hopping edges in a clock cycle, much more than traditional two-value clock of the kind of its hopping edge and quantity, so have the features such as structure is simple and low in energy consumption based on the trigger of four value clocks [1].
From prior art, document [1] proposes six edge triggered flip flops based on four value clock QCLK, and document [2,3] also utilizes the multiple value flip-flop that four value Clock Designs are relevant.As can be seen from relevant Research Literature, four value clock QCLK have obtained practicable application and have shown its superiority in digital circuit.But the four value clocks used in above-mentioned document have a common feature, the four value clocks be namely used to are all produce with simulation software simulation, but not are generated by the integrated circuit of reality.Investigation finds, there is no Research Literature at present and mention that generation four is worth the method for clock QCLK and relevant circuit, also namely, one simple and four of practicality value clock generators (Quaternary Clock Generator is called for short QCG) are also a vacancy at present.And clock is most important signal in digital system, the effect in sequence circuit controls and coordinate whole digital system normally to work.Two-value clock signal can be produced by quartz crystal multivibrator, and four value clocks can only be produced by simulation software simulation at present.Restriction four is worth the practical application of clock by this, also will be difficult to obtain practicality in document [1-3] based on the trigger of four value clocks.
For solving the problem in this practical application, namely do not have four value clock generator QCG at present, the two-value clock that the present invention utilizes quartz oscillator or phase-locked loop etc. to produce is as input signal, and application transport voltage switch is theoretical [4,5]invent the QCG unit of a kind of generation four value clocks from switching stage etc. knowledge, in the hope of invention circuit simply, stability and high efficiency and practicality, to solve the problem not having QCG integrated circuit unit at present.
List of references:
[1]Lang,Y.-F.,Shen,J.-Z..A general structure of all-edges-triggered flip-flop based on multivalued clock,International Journal of Electronics,2013,100,(12),pp.1637-1645.
[2] Xia Yinshui, Wu Xunwei, many-valued clock and block form many bats multiple value flip-flop, electronic letters, vol, 1997,25, (8), pp.52-54.
[3]Xia Y.S.,Wang L.Y.,Almaini A.E.A.,A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock,Journal of Computer Science and Technology,2005,20,(2),pp.237-242.
[4]Wu,X.,Prosser,F..Design of ternary CMOS circuits based on transmission function theory,International Journal of Electronics,1988,65,(5),pp.891-905.
[5]Prosser,F.,Wu,X.,Chen,X.CMOS Ternary Flip-Flops&Their Applications.IEE Proceedings on Computer&Digital Techniques,1988,135,(5),pp.266-272.
Summary of the invention is for the problem that can not generate four value clocks at present with simple integrated circuit, namely the problem of QCG circuit unit is not had, content of the present invention creates the QCG circuit unit that one can produce the four value clock QCLK used in document [1] exactly, and the QCG circuit unit of invention is wanted, and circuit structure is simple, efficient work, and its input/output signal will meet following four requirements:
1) circuit unit invented has two input signals: two-value clock CLK and inverted signal thereof their logical value values be 0,3} and duty ratio is 50%, namely the time ratio of low and high level is 1: 1;
2) circuit unit invented has an output signal: four value clock QCLK, and its level logic value value is { 0,1,2,3}, within a clock cycle, the output order of its level logic value is 0 → 1 → 2 → 3 → 2 → 1 → 0, and the duration of each output level is equal;
3) frequency ratio of four value clock QCLK of the two-value clock CLK inputted and output is 3: 1;
4) four value clock QCLK should have high frequency and range stability, meet associated clock requirement;
Accompanying drawing illustrates and is described in further detail the present invention below in conjunction with the drawings and specific embodiments.
Fig. 1 is the line map of a kind of QCG unit be made up of RSFF of the present invention.
Fig. 2 is two-value clock CLK, signal Q 0and Q 1time-sequential voltage waveform schematic diagram.
Fig. 3 be input in circuit shown in Fig. 1 two-value clock CLK, trigger FF0 output signal Q 0with the output signal Q of FF1 1with the voltage transient waveforms figure of the four value clock QCLK exported.
Embodiment the present invention utilizes logical value to switch to the two-value clock CLK of 0 → 3 → 0 to produce the four value clock QCLK that logical value sequence is 0 → 1 → 2 → 3 → 2 → 1 → 0.According to the corresponding relation of two-value clock CLK and four value clock, the logical value 0 of the present invention's two-value clock CLK controls the logical value 1 and 3 that generation four is worth clock QCLK; And control by the logical value 3 of two-value clock CLK the logical value 0 and 2 that generation four is worth clock QCLK.Because the logical value switch sequence of four value clock QCLK is 0 → 1 → 2 → 3 → 2 → 1 → 0, thus as CLK=0 four be worth clock QCLK generation unit will output logic value 1,3 and 1 in turn successively; As CLK=3, it then will output logic value 2,0 and 2 successively in turn.For this reason, two auxiliary control signal Q are also needed 0and Q 1realize thisly exporting in turn, use Q 00 and 3 outputs controlling four value clocked logic values 3 and 1 respectively; Use Q 13 and 0 output controlling four value clocked logic values 2 and 0 respectively.Q 0and Q 1low level should be respectively 1: 2 and 1: 2 with the ratio of the duration of high level, i.e. Q 0and Q 1duty ratio be all 66.7%.Like this, at two-value clock CLK and signal Q 0and Q 1control under just can produce the four value clock QCLK that logical value sequence is 0 → 1 → 2 → 3 → 2 → 1 → 0.The present invention's rest-set flip-flop carries out frequency division to obtain signal Q to two-value clock CLK 0and Q 1.Consider that the effective edge of two-value clock CLK in side circuit is along the output signal Q with trigger 0and Q 1between have clock output delay, this postpone by export four value clock waveforms in produce burr, be cancellation burr, output signal Q 0and Q 1should respectively in rising edge and the falling edge change state of two-value clock CLK.Learn in sum, signal Q 0and Q 1it is the three frequency division signal of two-value clock CLK.Two-value clock CLK and signal Q 0and Q 1waveform schematic diagram and sequential relationship between them as shown in Figure 2.
For obtaining Q by two-value clock CLK 0and Q 1two signals, the rest-set flip-flop (FF0) that the present invention adopts two to input to trigger with door (G1), rising edge and the rest-set flip-flop (FF1) that trailing edge triggers form the three frequency division circuit of two-value clock CLK.Described rest-set flip-flop FF0 and FF1 exports the three frequency division output signal Q changing state at CLK rising edge place and falling edge respectively 0and Q 1, signal with q respectively 0and Q 1inverted signal.In the present invention, the connection situation of described three frequency division circuit is as shown in the left circuit in Fig. 1, and its circuit design specifically describes and is: signal Q 0and Q 1two inputs of access and door G1, the output of G1 accesses the input R of described rest-set flip-flop FF0 0with the input R of FF1 1, the input S of described rest-set flip-flop FF0 0with the S of FF1 1connect respectively with this that is, the expression formula of two input signals of described rest-set flip-flop FF0 is R 0=Q 0q 1, the expression formula of two input signals of described rest-set flip-flop FF1 is R 1=Q 0q 1, the clock signal of described trigger FF0 and FF1 is the two-value clock CLK of input.Like this, trigger FF0 is responsive to the rising edge of CLK, and it outputs signal Q 0be the three frequency division signal of two-value clock CLK and Q 0low level be 1: 2 with the ratio of the duration of high level; Trigger FF1 is responsive to the trailing edge of CLK, and it outputs signal Q 1also be two-value clock CLK three frequency division signal and Q 1low level and the Duration Ratio of high level be 1: 2.Signal Q 0and Q 1generation four required for the present invention is exactly worth the control signal of clock QCLK.There is the control signal producing four value clock QCLK, according to summary of the invention and transmission voltage switching theorem [4,5], list four value clock QCLK and two-value clock CLK, q 0with switching stage function expression:
QCLK = 3 * ( CLK 0.5 · Q 0 0.5 ) # 2 * ( CLK ‾ 0.5 · Q 1 ‾ 0.5 ) # 1 * ( CLK ‾ 0.5 · Q 0 0.5 ) # 0 * ( CLK 0.5 · Q ‾ 1 0.5 ) .
For realizing described QCLK function expression, the circuit that the present invention adopts four PMOS (P1, P2, P3 and P4) and four NMOS tube (N1, N2, N3 and N4) to form generation four to be worth clock QCLK, namely produces the metal-oxide-semiconductor network of four value clocks.The connection situation of this partial circuit is as shown in the right circuit in Fig. 1, its circuit design specifically describes as follows: source electrode and the drain electrode of described PMOS P1 connect with the signal source of level logic value 3 and the source electrode of described PMOS P2 respectively, source electrode and the drain electrode of described PMOS P3 connect with the signal source of level logic value 2 and the source electrode of described PMOS P4 respectively, source electrode and the drain electrode of described NMOS tube N1 connect with the signal source of level logic value 1 and the source electrode of described NMOS tube N2 respectively, the source electrode of described NMOS tube N3 and drain electrode respectively with power supply connect with the source electrode of described NMOS tube N4, described metal-oxide-semiconductor P2, P4, the drain electrode of N2 and N4 connects as the output of four value clock QCLK, described metal-oxide-semiconductor P1, P2, P3, P4, N1, N2, the grid of N3 and N4 respectively with signal CLK, Q 0, q 0, CLK and being connected, under the control of these signals, is the four value periodic signals i.e. four value clock QCLK of 0 → 1 → 2 → 3 → 2 → 1 → 0 in circuit output end output level logical value switch sequence.
Known in sum, giving the input of the circuit shown in Fig. 1 two-value clock CLK and its inverted signal just can obtain the four value clock QCLK that logical value switches to 0 → 1 → 2 → 3 → 2 → 1 → 0 at the output QCLK place of this circuit.Therefore, the circuit shown in Fig. 1 is and realizes circuit unit of the present invention---a kind of QCG unit be made up of RSFF.For the QCG unit that namely checking the present invention is made up of RSFF, with HSPICE software, it is simulated below.Adopt the CMOS technology parameter of TSMC 180nm during simulation, output loading is 30fF.The magnitude of voltage of two level logic values 0 and 3 correspondence of two-value clock CLK is respectively 0V and 3.3V; The magnitude of voltage of four level logic values 0,1,2 and 3 correspondence of four value clock QCLK is respectively 0V, 1.1V, 2.2V and 3.3V.The voltage transient waveforms of described a kind of QCG unit simulation gained be made up of RSFF as shown in Figure 3, wherein CLK, Q 0, Q 1the four value clock waveforms that the signal exported with the signal that QCLK is respectively two-value clock, FF0 exports, FF1 and QCG unit export.The analog result of Fig. 3 shows, the present invention and a kind of QCG Elementary Function be made up of RSFF correct.
Sum up: because the present invention only employs one and door, two rest-set flip-flops and eight metal-oxide-semiconductors, and can manufacture, so a kind of QCG element circuit be made up of RSFF of invention is simple by CMOS technology conventional at present.By analysis, described a kind of QCG unit be made up of RSFF is the circuit of an energy self-starting, and four level values of four value clocks are the metal-oxide-semiconductor output formation through conducting of four voltage sources, and therefore working stability of the present invention is efficient.In a word, the invention solves the problem not having actual integrated circuit to produce four value clocks at present.Fill up the blank producing four value clock circuits, which illustrated the present invention and there is novelty, creativeness and practicality, meet the regulation that Patent Law is granted patent.

Claims (1)

1. the QCG unit be made up of RSFF, by two-value clock CLK and the inverted signal thereof of input produce the four value clock QCLK that sequence is 0 → 1 → 2 → 3 → 2 → 1 → 0, it comprise rest-set flip-flop (FF0) that one two input triggers with door (G1), rising edge, the rest-set flip-flop (FF1) that trailing edge triggers, four PMOS (P1, P2, P3 and P4) and four NMOS tube (N1, N2, N3 and N4), first, with described rest-set flip-flop FF0 and FF1, three frequency division is carried out to two-value clock CLK, obtain the three frequency division output signal Q changing state at CLK rising edge place and falling edge respectively 0and Q 1, their duty ratio is all 66.7%, signal with q respectively 0and Q 1inverted signal, then, the metal-oxide-semiconductor network of clock is worth with the generation four of described eight metal-oxide-semiconductors composition, its circuit is that the source electrode of described PMOS P1 connects with the signal source of logical value 3 and the source electrode of described PMOS P2 respectively with drain electrode, source electrode and the drain electrode of described PMOS P3 connect with the signal source of logical value 2 and the source electrode of described PMOS P4 respectively, source electrode and the drain electrode of described NMOS tube N1 connect with the signal source of logical value 1 and the source electrode of described NMOS tube N2 respectively, the source electrode of described NMOS tube N3 and drain electrode respectively with power supply connect with the source electrode of described NMOS tube N4, described metal-oxide-semiconductor P2, P4, the drain electrode of N2 and N4 links together as the output of four value clock QCLK, finally, with CLK, q 0with control described metal-oxide-semiconductor network and produce four value clock QCLK,
The feature of described a kind of QCG unit be made up of RSFF is: the expression formula of two input signals of described rest-set flip-flop FF0 is R 0=Q 0q 1, the expression formula of two input signals of described rest-set flip-flop FF1 is R 1=Q 0q 1, described four expression formulas are embodied as signal Q 0and Q 1two inputs of access and door G1, the output of G1 accesses the input R of described rest-set flip-flop FF0 0with the input R of FF1 1, the input S of described rest-set flip-flop FF0 0with the S of FF1 1connect respectively with the signal controlling described metal-oxide-semiconductor network specifically connects for signal CLK, Q 0, q 0, CLK and connect with the grid of described metal-oxide-semiconductor P1, P2, P3, P4, N1, N2, N3 and N4 respectively.
CN201510096472.6A 2015-03-04 2015-03-04 A kind of QCG units being made up of RSFF Expired - Fee Related CN104639110B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102916687A (en) * 2012-09-27 2013-02-06 浙江工商大学 Ternary clock generator based on CMOS (complementary metal oxide semiconductor) technology
WO2013157195A1 (en) * 2012-04-19 2013-10-24 パナソニック株式会社 Multilevel-signal transmission system
CN104333356A (en) * 2014-11-14 2015-02-04 浙江工商大学 QB02 circuit unit for quaternary clock and binary clock conversion

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013157195A1 (en) * 2012-04-19 2013-10-24 パナソニック株式会社 Multilevel-signal transmission system
CN102916687A (en) * 2012-09-27 2013-02-06 浙江工商大学 Ternary clock generator based on CMOS (complementary metal oxide semiconductor) technology
CN104333356A (en) * 2014-11-14 2015-02-04 浙江工商大学 QB02 circuit unit for quaternary clock and binary clock conversion

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
YAN-FENG LANG等: "Design of ternary clock generator", 《ELECTRONICS LETTERS》 *
张炳德等: "四值时钟竞争型变沿触发器的研究", 《武汉水利电力大学学报》 *
郎燕峰: "多值低功耗双边沿触发器的简化设计", 《杭州电子科技大学学报》 *

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