CN104639111B - QCG circuit units based on JKFF - Google Patents
QCG circuit units based on JKFF Download PDFInfo
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- CN104639111B CN104639111B CN201510096485.3A CN201510096485A CN104639111B CN 104639111 B CN104639111 B CN 104639111B CN 201510096485 A CN201510096485 A CN 201510096485A CN 104639111 B CN104639111 B CN 104639111B
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Abstract
The present invention relates to a kind of circuit design problem of the QCG circuit units based on JKFF.Because QC has larger information content, it has been applied in research papers and has shown certain advantage.And QC signals can only be emulated by simulation softward and generated at present, both at home and abroad also without simple and the integrated circuit of practicality can produce QC signals.Here a kind of QC signal generating circuit units based on JKFF, i.e. QCG circuit units are invented, it is mainly made up of two kinds of JKFF and metal-oxide-semiconductor.The present invention is that the QCG circuit units based on JKFF solve the problems, such as that QC signals can not be produced by integrated circuit at present so that QC signals can carry out practical application.Simulation shows that the QCG circuit unit functions based on JKFF are correct；In addition, the circuit unit to invention shows after analyzing, circuit structure of the invention is simple, and performance is high, and is easy to carry out practical application in circuit.
Description
The present invention relates to a kind of production being made up of two kinds of JK flip-flops (JKFF) for triggering edge and metal-oxide-semiconductor for technical field
The circuit unit of raw four value clock (Quaternary Clock, abbreviation QCLK or QC).
For background technology because four value clock QCLK have abundant information content, it has six kinds of jumps in a clock cycle
Become edge, the type and quantity of its hopping edge are all more much more than traditional two-value clock, so the trigger based on four value clocks
There is the features such as simple in construction and low in energy consumption[1]。
In terms of prior art, document [1] proposes six edge triggered flip flops based on four value clock QCLK, document [2,3]
The multiple value flip-flop of correlation is devised using four value clocks.As can be seen that four value clock QCLK exist from the Research Literature of correlation
Practicable application is had been obtained in digital circuit and shows its superiority.However, used in above-mentioned document four
Value clock have one it is common the characteristics of, that is, the four value clocks that are used all are to be simulated to produce with simulation software, rather than by reality
Integrated circuit generates.Investigation is found, there is no Research Literature to refer to four value clock QCLK of generation method and correlation at present
Circuit, that is, simple and practical four value clock generator (Quaternary Clock Generator, referred to as
QCG) also it is at present a vacancy.And clock is most important signal in digital display circuit, the effect in sequence circuit be control and
Coordinate whole digital display circuit normally to work.Two-value clock signal can be produced by quartz crystal multivibrator, and four value clocks
It can only be simulated and produced by simulation software at present.This will limit the practical application of four value clocks, be worth in document [1-3] based on four
The trigger of clock will also be difficult to obtain practicality.
To solve the problems, such as in this practical application, i.e., utilize quartz currently without four value clock generator QCG, the present invention
Two-value clock caused by crystal oscillator or phaselocked loop etc. is known as input signal, application transport voltage switch theory [4,5] etc.
Know from switching stage to invent a kind of QCG circuit units for producing four value clocks, in the hope of invention circuit simply, stability and high efficiency and reality
With to solve the problems, such as currently without QCG integrated circuit units.
Bibliography：
[1] Lang, Y.-F., Shen, J.-Z..A general structure of all-eJKges-triggereJK
Flip-flop baseJK on multivalueJK clock, International Journal of Electronics,
2013,100, (12), pp.1637-1645.
[2] Xia Yinshui, Wu Xunwei, multivalue clock and block form clap multiple value flip-flop more, electronic letters, vol, and 1997,25, (8),
pp.52-54.
[3] Xia Y.S., Wang L.Y., Almaini A.E.A., A Novel Multiple-ValueJK CMOS
Flip-Flop Employing Multiple-ValueJK Clock, Journal of Computer Science anJK
Technology, 2005,20, (2), pp.237-242.
[4] Wu, X., Prosser, F..JKesign of ternary CMOS circuits baseJK on
Transmission function theory, International Journal of Electronics, 1988,65,
(5), pp.891-905.
[5] Prosser, F., Wu, X., Chen, X.CMOS Ternary Flip-Flops＆Their
Applications.IEE ProceeJKings on Computer＆JKigital Techniques, 1988,135, (5),
pp.266-272.
The problem of content of the invention with simple integrated circuit for that can not generate four value clocks at present, i.e., no QCG electricity
The problem of road unit, present disclosure are exactly to create one kind to produce the four value clock QCLK used in document [1] QCG electricity
Road unit, and invent QCG circuit units want circuit structure simply, efficient work, and its input/output signal to meet it is following
Four requirements：
1) circuit unit of invention has two input signals：Two-value clock CLK and its inverted signalTheir logical values
Value is { 0,3 } and dutycycle is 50%, i.e., the time ratio of low and high level is 1: 1；
2) circuit unit of invention has an output signal：Four value clock QCLK, its level logic value value for 0,1,
2,3 }, the output order of its level logic value is 0 → 1 → 2 → 3 → 2 → 1 → 0 within a clock cycle, each output level
Duration it is equal；
3) the two-value clock CLK of input and four value clock QCLK of output frequency ratio are 3: 1；
4) four value clock QCLK should have high frequency and range stability, meet associated clock requirement；
Brief description of the drawings is described in further detail to the present invention with reference to the accompanying drawings and detailed description.
Fig. 1 is the line map of the QCG circuit units of the invention based on JKFF.
Fig. 2 is two-value clock CLK, signal Q0And Q1Time-sequential voltage waveform diagram.
Fig. 3 is two-value clock CLK, the trigger FF0 output signal Q inputted in circuit shown in Fig. 10With FF1 output
Signal Q1With four value clock QCLK of output voltage transient waveforms figure.
The embodiment present invention switches to 0 → 3 → 0 two-value clock CLK to produce logical value using logical value
The four value clock QCLK that sequence is 0 → 1 → 2 → 3 → 2 → 1 → 0.It is worth the corresponding relation of clock according to two-value clock CLK and four,
The present invention controls four value clock QCLK of generation logical value 1 and 3 with two-value clock CLK logical value 0；And with two-value clock
CLK logical value 3 produces four value clock QCLK logical value 0 and 2 to control.Due to four value clock QCLK logical value switching time
Sequence is 0 → 1 → 2 → 3 → 2 → 1 → 0, so four value clock QCLK generation units will export logic in turn successively as CLK=0
Value 1,3 and 1；As CLK=3, it will then be sequentially output logical value 2,0 and 2 in turn.Therefore, also need two auxiliary control signal Q0
And Q1Come realize it is this export in turn, use Q03 and 0 output for controlling four value clocked logic values 3 and 1 respectively；Use Q10 and 3
The output of the value clocked logic of control four value 2 and 0 respectively.Q0And Q1Low level and the ratio between duration of high level should be respectively 2
: 1 and 2: 1, i.e. Q0And Q1Dutycycle all be 33.3%.So, in two-value clock CLK and signal Q0And Q1Control under just
The four value clock QCLK that logic value sequence is 0 → 1 → 2 → 3 → 2 → 1 → 0 can be produced.When present invention JK flip-flop is to two-value
Clock CLK is divided to obtain signal Q0And Q1.In view of two-value clock CLK effective edge edge and trigger in actual circuit
Output signal Q0And Q1Between have clock output delay, this delay will produce burr in four value clock waveforms of output, to disappear
Deburring, output signal Q0And Q1State should be changed in two-value clock CLK rising edge and falling edge respectively.In summary
Know, signal Q0And Q1It is two-value clock CLK three frequency division signal.Two-value clock CLK and signal Q0And Q1Waveform diagram and it
Between sequential relationship it is as shown in Figure 2.
To obtain Q by two-value clock CLK0And Q1Two signals, the JK flip-flop that the present invention is triggered using a rising edge
(FF0) and the JK flip-flop (FF1) of trailing edge triggering forms two-value clock CLK Divide-by-3 circuit.The JK triggerings
Device FF0 and FF1 are exported at CLK rising edges respectively and falling edge changes the three frequency division output signal Q of state0And Q1, signalWithIt is Q respectively0And Q1Inverted signal.In the present invention, the connection situation of the Divide-by-3 circuit is as in Fig. 1
Shown in left circuit, its circuit design is specifically described as：SignalWithIt is respectively connected to the input J of the JK flip-flop FF11
With FF0 input J0, the input K of the JK flip-flop FF0 and FF10And K1All connect the voltage source that logical value is 3；This is also
It is to say, the expression formula of two input signals of the JK flip-flop FF0 isK0=3；The two of the JK flip-flop FF1 are defeated
The expression formula for entering signal isK1=3；The clock signal of the trigger FF0 and FF1 is the two-value clock CLK of input.
So, trigger FF0 is sensitive to CLK rising edge, its output signal Q0It is two-value clock CLK three frequency division signal and Q0It is low
The ratio between duration of level and high level is 2: 1；Trigger FF1 is sensitive to CLK trailing edge, its output signal Q1Also it is two
It is worth clock CLK three frequency divisions signal and Q1Low level and high level Duration Ratio be 2: 1.Signal Q0And Q1It is exactly the present invention
Required generation four is worth clock QCLK control signal.There is the control signal for producing four value clock QCLK, according to the content of the invention
It is theoretical with the transmission voltage switch in document [4,5], list four value clock QCLK and two-value clock CLK, signal Q0And Q1Switch
Level function expression：
To realize the QCLK function expressions, the present invention uses four PMOSs (P1, P2, P3 and P4) and four NMOS
Pipe (N1, N2, N3 and N4) produces four value clock QCLK circuit to form, that is, produces the metal-oxide-semiconductor network of four value clocks.The part
As shown in the right circuit in Fig. 1, its circuit design is described in detail below the connection situation of circuit：The source of the PMOS P1
Pole and drain electrode connect with the signal source of level logic value 3 and the source electrode of the PMOS P2 respectively, the source electrode of the PMOS P3
With drain electrode connect respectively with the signal source of level logic value 2 and the source electrode of the PMOS P4, the source electrode of the NMOS tube N1 with
Drain electrode connects with the signal source of level logic value 1 and the source electrode of the NMOS tube N2 respectively, the source electrode of the NMOS tube N3 and leakage
Pole connects with power supply with the source electrode of the NMOS tube N4 respectively, and described metal-oxide-semiconductor P2, P4, N2 and N4 drain electrode connect as four
Be worth clock QCLK output end, described metal-oxide-semiconductor P1, P2, P3, P4, N1, N2, N3 and N4 grid respectively with signal CLK,Q1、CLK and Q1It is connected, under the control of these signals, is exported in circuit output end
The four value periodic signals that level logic value switch sequence is 0 → 1 → 2 → 3 → 2 → 1 → 0 are four value clock QCLK.
Understand in summary, to the circuit input two-value clock CLK and its inverted signal shown in Fig. 1Can
The four value clock QCLK that logical value switches to 0 → 1 → 2 → 3 → 2 → 1 → 0 are obtained at the output end QCLK of the circuit.Therefore,
Circuit shown in Fig. 1 is circuit unit --- the QCG circuit units based on JKFF for realizing the present invention.For the base of checking invention
In JKFF QCG circuit units, it is simulated with HSPICE softwares below.Using TSMC 180nm CMOS works during simulation
Skill parameter, output loading 30fF.Magnitude of voltage corresponding to two-value clock CLK two level logic values 0 and 3 be respectively 0V and
3.3V；Magnitude of voltage corresponding to four value clock QCLK four level logic values 0,1,2 and 3 be respectively 0V, 1.1V, 2.2V and
3.3V.The voltage transient waveforms of the QCG circuit units simulation gained based on JKFF are as shown in figure 3, wherein CLK, Q0、Q1With
QCLK is respectively the four of two-value clock, the signal of FF0 outputs, the signal of FF1 outputs and the QCG circuit units output based on JKFF
It is worth clock waveform.Fig. 3 analog result shows that the present invention is that the QCG circuit units based on JKFF have correct logic function.
Summarize：Because the present invention has only used two JK flip-flops and eight metal-oxide-semiconductors, and CMOS works conventional at present can be used
Skill is manufactured, so, the QCG circuit unit circuits based on JKFF of invention are simple.Through analysis, the QCG based on JKFF
Circuit unit is the circuit of an energy self-starting, and four level values of four value clocks are four metal-oxide-semiconductors of the voltage source through conducting
Output is formed, therefore working stability of the present invention is efficient.In a word, the QCG circuit units based on JKFF have correct logic function,
Solve the problems, such as to produce four value clocks currently without actual integrated circuit.The blank for producing four value clock circuits has been filled up, this
Embodying the present invention has novelty, creativeness and practicality, meets the patentable regulation of Patent Law.
Claims (1)
- A kind of 1. QCG circuit units based on JKFF, with the two-value clock CLK and its inverted signal of inputProduce sequence Four for 0 → 1 → 2 → 3 → 2 → 1 → 0 are worth clock QCLK, and it includes JK flip-flop FF0 of rising edge triggering, under one JK flip-flop FF1, four PMOS P1, P2, P3 and P4s and four NMOS tube N1, N2, N3 and N4s of the drop along triggering；First, use The JK flip-flop FF0 and FF1 carries out three frequency division to two-value clock CLK, respectively obtains and changes at CLK rising edges with falling edge The three frequency division output signal Q of change state0And Q1, their dutycycle is all 33.3%, signalWithIt is Q respectively0And Q1It is anti- Signal；Then, the metal-oxide-semiconductor network of four value clocks, the metal-oxide-semiconductor net are produced with four PMOSs and four NMOS tube compositions The source electrode that the circuit of network is connected as the PMOS P1 connects with the signal source of logical value 3, the drain electrode of the PMOS P1 and institute The source electrode for stating PMOS P2 connects, and the source electrode of the PMOS P3 connects with the signal source of logical value 2, the leakage of the PMOS P3 Pole connects with the source electrode of the PMOS P4, and the source electrode of the NMOS tube N1 connects with the signal source of logical value 1, the NMOS tube N1 drain electrode connects with the source electrode of the NMOS tube N2, and the source electrode of the NMOS tube N3 connects with power supply, the NMOS tube N3 Drain electrode connect with the source electrode of the NMOS tube N4, described metal-oxide-semiconductor P2, P4, N2 and N4 drain electrode are connected together as four values Clock QCLK output end；Finally, with CLK,And Q1The metal-oxide-semiconductor network is controlled to produce four value clock QCLK；The QCG circuit units based on JKFF are characterised by：The expression formula of two input signals of the JK flip-flop FF0 isK0=3；The expression formula of two input signals of the JK flip-flop FF1 isK1=3；The expression formulaK0=3 HesK1=3 are embodied as signal on circuitAccess the input J of the JK flip-flop FF11, letter NumberAccess the input J of the JK flip-flop FF00, the input K of the JK flip-flop FF0 and FF10And K1All connect logical value For 3 voltage source；The signal of the metal-oxide-semiconductor network is controlled specifically to be connected as：Signal CLK connects with the grid of the metal-oxide-semiconductor P1, SignalConnect with the grid of the P2, signalConnect with the grid of the P3, signal Q1With the grid phase of the P4 Connect, signalConnect with the grid of the N1, signalConnect with the grid of the N2, signal CLK and N3 grid Pole connects, signal Q1Connect with the grid of the N4.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510096485.3A CN104639111B (en) | 2015-03-04 | 2015-03-04 | QCG circuit units based on JKFF |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510096485.3A CN104639111B (en) | 2015-03-04 | 2015-03-04 | QCG circuit units based on JKFF |
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| CN104639111B true CN104639111B (en) | 2017-11-24 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102983841A (en) * | 2012-12-20 | 2013-03-20 | 上海工程技术大学 | Reversible master-slave RS flip-flop based on reversible logical gate |
| CN104320126A (en) * | 2014-11-14 | 2015-01-28 | 浙江工商大学 | Circuit unit converting QC into BC21 |
| CN104333355A (en) * | 2014-11-14 | 2015-02-04 | 浙江工商大学 | QC-BC01 circuit module for clock transformation |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4164357B2 (en) * | 2002-12-27 | 2008-10-15 | 三菱電機株式会社 | Frequency comparator |
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2015
- 2015-03-04 CN CN201510096485.3A patent/CN104639111B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102983841A (en) * | 2012-12-20 | 2013-03-20 | 上海工程技术大学 | Reversible master-slave RS flip-flop based on reversible logical gate |
| CN104320126A (en) * | 2014-11-14 | 2015-01-28 | 浙江工商大学 | Circuit unit converting QC into BC21 |
| CN104333355A (en) * | 2014-11-14 | 2015-02-04 | 浙江工商大学 | QC-BC01 circuit module for clock transformation |
Non-Patent Citations (2)
| Title |
|---|
| "多值低功耗双边沿触发器的简化设计";郎燕峰等;《杭州电子科技大学学报》;20101031;第30卷(第5期);第21-24页 * |
| "多值时钟与并列式多拍多值触发器";夏银水等;《电子学报》;19970831;第25卷(第8期);第52-54页 * |
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