CN104459564A - Power source burr signal detecting circuit and method preventing power source attack - Google Patents
Power source burr signal detecting circuit and method preventing power source attack Download PDFInfo
- Publication number
- CN104459564A CN104459564A CN201410689271.2A CN201410689271A CN104459564A CN 104459564 A CN104459564 A CN 104459564A CN 201410689271 A CN201410689271 A CN 201410689271A CN 104459564 A CN104459564 A CN 104459564A
- Authority
- CN
- China
- Prior art keywords
- pipe
- phase inverter
- power supply
- node
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The invention relates to a power source burr signal detecting system and method for preventing power source attack. The power source burr signal detecting system is provided with a low pass filter, two similar inverters, two inverters and a logic unit. When the |VGS| voltage value of PMOS tubes in the similar inverters, namely the potential difference of a power source before and after filtering exceeds the absolute value of the threshold voltage of the PMOS tubes, it is judged that power source burrs occur in the power source before filtering, and then burr attacking alarming is triggered. The edge slope and burr depth of the power source burrs are co-determined by the filtering frequency, the size of the PMOS tubes and the threshold value. The power source burr signal detecting system and method have the advantages that the circuit structure is simple, the chip area is saved, the detecting system and method are easy to achieve, the responding speed is high, mistaken judgment does not occur easily, and the static power consumption is extremely low.
Description
Technical field
The present invention relates to power technology, particularly a kind of power supply burr signal testing circuit of anti-source attack and detection method.
Background technology
Along with the widespread use of smart card, become the key object of assault at the smart card of security fields.It is by changing the supply voltage or the ground voltage that are input to intelligent card chip fast that power supply burr (power glitch) is attacked, some circuit unit in chip is affected, one or more circuit unit is caused to enter error condition, thus cause chip processor to be skipped or the operation of state implementation mistake according to mistake, and then make the security information a kind of attack means come out gradually hidden in chip.
Summary of the invention
The invention provides a kind of power supply burr signal testing circuit and detection method of anti-source attack, structure is simple, detects fast effectively.
In order to achieve the above object, a technical scheme of the present invention is to provide a kind of power supply burr signal testing circuit of anti-source attack, wherein comprises:
Low-pass filter, monitored power supply is divided into the first power supply VCC before filtering by it, and through the filtered second source VCCin of this low-pass filter;
First kind phase inverter, comprises the PMOS MP1 and NMOS tube NM2 that are connected; Source electrode and the grid of pipe MP1 are connected the first power supply VCC and second source VCCin respectively; The node a that the drain electrode that electric capacity C2 is connected to pipe MP1 is connected with the drain electrode of pipe MN2;
First phase inverter, comprises the PMOS MP2 and NMOS tube MN3 that are connected; The tie point of the grid of pipe MP2 and the grid of pipe MN3, is connected to the node a of described first kind phase inverter; The node c that the drain electrode of pipe MP2 is connected with the drain electrode of pipe MN3, is connected to logical block;
Wherein, as the electric potential difference VPP of the first power supply VCC and second source VCCin
(VCC-VCCin)exceed the threshold voltage of pipe MP1 | during Vthp|, pipe MP1 opens and charges to electric capacity C2, and then when making the current potential of node a be promoted to the turnover voltage Vth_MN3 of the first phase inverter, the node c of the first phase inverter sends the first trigger pip to logical block, makes logical block produce the first alerting signal and reports to the police to the forward burr that the first power supply VCC occurs.
Preferably, also comprise in described power supply burr signal testing circuit:
Equations of The Second Kind phase inverter, comprises the PMOS MP3 and NMOS tube NM4 that are connected; Grid and the source electrode of pipe MP3 are connected the first power supply VCC and second source VCCin respectively; The node b that the drain electrode that electric capacity C3 is connected to pipe MP3 is connected with the drain electrode of pipe MN4;
Second phase inverter, comprises the PMOS MP4 and NMOS tube MN5 that are connected; The tie point of the grid of pipe MP4 and the grid of pipe MN5, is connected to the node b of described Equations of The Second Kind phase inverter; The node d that the drain electrode of pipe MP4 is connected with the drain electrode of pipe MN5, is connected to logical block;
Wherein, as the electric potential difference VPP of second source VCCin and the first power supply VCC
(VCCin-VCC)exceed the threshold voltage of pipe MP3 | Vthp ' | time, pipe MP3 opens and charges to electric capacity C3, and then when making the current potential of node b be promoted to the turnover voltage Vth_MN5 of the second phase inverter, the node d of the second phase inverter sends the second trigger pip to logical block, makes logical block produce the second alerting signal and reports to the police to the negative sense burr that the first power supply VCC occurs.
Preferably, in described logical block, comprise further:
First impact damper, its input end is connected to the node c of described first phase inverter, carries out shaping to the first trigger pip that the first phase inverter exports;
Second impact damper, its input end is connected to the node d of described second phase inverter, carries out shaping to the second trigger pip that the second phase inverter exports;
Or door, two input end is connected to the output terminal of the first impact damper and the second impact damper respectively;
D type flip flop, its input end is connected to or the output terminal of door, comes corresponding generation first alerting signal and the second alerting signal according to the first trigger pip after shaping and logical OR computing and the second trigger pip.
Preferably, described d type flip flop is provided with clear terminal or set end, receives the reset signal externally to its feedback or asserts signal, resets or set the signal that this d type flip flop exports.
Preferably, described first phase inverter and the second phase inverter are asymmetrical phase inverters.
Preferably, the grid of described pipe MN2 and the grid of pipe MN4, be all connected to grid and the bias voltage of NMOS tube MN1, makes pipe MN2, mirror image that the electric current of pipe MN4 is the electric current of pipe MN1.
Preferably, described low-pass filter comprises resistance R1 and the electric capacity C1 of series connection, by the second source VCCin after the series connection point output filtering of resistance R1 and electric capacity C1.
Another technical scheme of the present invention is to provide a kind of power supply burr signal detection method of anti-source attack, wherein comprises following process:
Low-pass filter is set, monitored power supply is divided into the first power supply VCC before filtering and filtered second source VCCin;
In first kind phase inverter, make the tie point of the drain electrode of PMOS MP1 and the drain electrode of NMOS tube NM2 as output node a, be connected with the input node of electric capacity C2 and the first phase inverter respectively;
In Equations of The Second Kind phase inverter, make the tie point of the drain electrode of PMOS MP3 and the drain electrode of NMOS tube NM4 as output node b, be connected with the input node of electric capacity C3 and the second phase inverter respectively;
Described pipe MP1's | VGS| magnitude of voltage is the electric potential difference VPP of the first power supply VCC and second source VCCin
(VCC-VCCin)as pipe MP1 | VGS| magnitude of voltage exceedes the threshold voltage of pipe MP1 | during Vthp|, pipe MP1 opens and charges to electric capacity C2, and then when making the current potential of the output node a of first kind phase inverter be promoted to the turnover voltage Vth_MN3 of described first phase inverter, the output node c of the first phase inverter exports the first trigger pip;
Described pipe MP3's | VGS| magnitude of voltage is the electric potential difference VPP of second source VCCin and the first power supply VCC
(VCCin-VCC)as pipe MP3 | VGS| magnitude of voltage exceedes the threshold voltage of pipe MP3 | Vthp ' | time, pipe MP3 opens and charges to electric capacity C3, and then when making the current potential of the output node b of Equations of The Second Kind phase inverter be promoted to the turnover voltage Vth_MN5 of described second phase inverter, the output node d of the second phase inverter exports the second trigger pip;
Described first trigger pip or the second trigger pip are negative edge signal, rising edge signal is obtained after the computing of shaping and logical OR, make a d type flip flop export the first alerting signal or the second alerting signal that are overturn by low level to high level according to this rising edge signal, the forward burr that the first power supply VCC occurs or negative sense burr are reported to the police.
Preferably, when the electric potential difference of described first power supply VCC and second source VCCin is zero, the output node a of described first kind phase inverter and the output node b of described Equations of The Second Kind phase inverter exports no-voltage, make the output node d of the output node c of described first phase inverter and described second phase inverter export high level, after the computing of shaping and logical OR, make described d type flip flop be in export be zero hold mode.
Preferably, after described d type flip flop exports the first alerting signal or the second alerting signal, by the reset signal fed back externally to this d type flip flop, the first alerting signal or the second alerting signal are reset, this d type flip flop is returned to export be zero hold mode.
Compared with prior art, the power supply burr testing circuit of anti-source attack of the present invention and detection method, its circuit sampling end is made up of RC wave filter and PMOS, the threshold voltage whether being reached described PMOS by the voltage difference of the band power supply VCC of burr and the power supply VCCin after RC filter filtering has judged whether power supply burr, if will trigger burr time above-mentioned voltage difference exceedes the threshold voltage of this PMOS to attack warning.The size of RC frequency filtering and PMOS and threshold value determine edge slope (glitch slope) and the burr degree of depth of the power supply burr judged jointly.It is simple that the present invention has circuit structure, the advantages such as saving chip area, easily realizes, and fast response time not easily occurs erroneous judgement, and quiescent dissipation is extremely low.
Accompanying drawing explanation
Fig. 1 is the structure principle chart of the power supply burr signal testing circuit of anti-source attack of the present invention;
The schematic diagram of Fig. 2 to be the burr signal of power supply described in the present invention be forward burr signal;
The schematic diagram of key signal action when being forward burr signal that Fig. 3 is the burr signal of power supply described in the present invention;
The schematic diagram of Fig. 4 to be the burr signal of power supply described in the present invention be negative sense burr signal;
The schematic diagram of key signal action when being negative sense burr signal that Fig. 5 is the burr signal of power supply described in the present invention.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described.
As shown in Figure 1, in the power supply burr signal testing circuit of anti-source attack of the present invention, be provided with RC low-pass filter, it comprises resistance R1 and the electric capacity C1 of series connection.This RC low-pass filter, by monitored power supply, is with the power supply VCC of burr before being divided into filtering, and the power supply VCCin not with frequency glitches after the filtering of RC low-pass filter.
Two PMOS MP1 and MP3 are set; Make the grid of the source electrode of pipe MP1, pipe MP3, be connected with the power supply VCC with burr before above-mentioned filtering respectively; By the source electrode of the grid of pipe MP1, pipe MP3, be connected with the power supply VCCin not with burr after above-mentioned filtering respectively.
Two current source NMOS tube MN2 and MN4 are set; Pipe MP1 and pipe MN2 is connected to form first class phase inverter; Similarly, pipe MP3 and pipe MN4 is connected to form second class phase inverter; In the output stage of these two class phase inverters, be connected to electric capacity C2, C3, (power supply do not have burr time) can not produce power loss thus in the quiescent state.
Wherein, electric capacity C2 is connected to pipe MP1 and drains and to drain the node a be connected with pipe MN2; Electric capacity C3 is connected to pipe MP3 and drains and to drain the node b be connected with pipe MN4.The grid of pipe MN2 and the grid of pipe MN4, be connected to the grid of another NMOS tube MN1 respectively.
Two other PMOS MP2 and MP4 is set, and two other NMOS tube MN3 and MN5; Pipe MP2 and pipe MN3 is connected to form first phase inverter; Similarly, pipe MP4 and pipe MN5 is connected to form second phase inverter.These two phase inverters can be arranged to asymmetrical phase inverter, its trigging signal be set to lower with the susceptibility increased the response of power supply burr.
By the tie point of pipe MP2 grid and pipe MN3 grid, be connected with the anode of above-mentioned electric capacity C2, be namely connected to described node a; By the tie point of pipe MP4 grid and pipe MN5 grid, be connected with the anode of above-mentioned electric capacity C3, be namely connected to described node b.
The source electrode of described pipe MP2, the source electrode of pipe MP4, be with the power supply VCC of burr before being connected to above-mentioned filtering respectively.Drain pipe MP2 drain electrode and pipe MN3 in first phase inverter the node c be connected, and is connected with the input end of first impact damper (buffer) I1; Drain pipe MP4 drain electrode and pipe MN5 in second phase inverter the node d be connected, and is connected with the input end of second impact damper I2.The output terminal of two impact dampers I1, I2 is connected to or two input ends of door I3, and output terminal that is described or door I3 is connected to the input end of d type flip flop I4.
The response of signal to burr that these two phase inverters export embodies in the form of a pulse, by described impact damper I1, I2 shaping and or door I3 computing after export, make response by the pulse of any above-mentioned phase inverter; The d type flip flop I4 triggered by rising edge again obtains also can obtaining low level alerting signal in other examples of alarm signal A LARM(of the high level wanted); The clear terminal CLR of described d type flip flop and set end SET, is controlled to carry out resetting and set by the signal of system feedback.
Original state is when power supply not having burr, the electric potential difference of power supply VCC and VCCin is 0, these two PMOS of MP1 and MP3 are made to be in closed condition, now electric capacity C2 and C3 electric charge by by their electric current of current source MN2 and MN4(by pipe MN1 mirror image) electric discharge, therefore during static state, the voltage of node a and b is 0, pass through by pipe MP2 and pipe MN3, two phase inverters that pipe MP4 and pipe MN5 forms, export high level respectively, again through impact damper I1 and I2, or export as low level 0 after door I3, the d type flip flop that then rising edge triggers below is in hold mode, be defaulted as 0.It should be noted that, the logical gate power domain in Fig. 1 in right frame can be inconsistent with detected power domain, but require that rational level logic is changed.
Below explain and detect forward burr signal trigger mechanism on power supply:
Coordinate see shown in Fig. 2, Fig. 3, suppose that power supply VCC occurs that edge slope (glitch slope) and the burr degree of depth all meet the requirements of upwards burr (Fig. 2), be then a relatively stable power supply by the power supply VCCin after low-pass filter, so source electrode and grid meet the PMOS MP1 of power supply VCC and VCCin respectively | and VGS| magnitude of voltage is the electric potential difference VPP of power supply VCC and VCCin
(VCC-VCCin), the burr degree of depth of the upwards burr namely produced close to above-mentioned hypothesis.Suppose that edge slope and the burr degree of depth of this burr all reach requirement above, therefore pipe MP1 | VGS| magnitude of voltage will exceed the threshold voltage of self | and Vthp|, therefore pipe MP1 will open and charge to electric capacity C2.Because current source MN2 is by the current mirror (bias current that can arrange is lower) of pipe MN1, and the very fast current potential by node a is charged to enough large by the conducting of pipe MP1 instantaneously, this voltage enough reaches the turnover voltage Vth_MN3 of the asymmetric phase inverter be made up of pipe MP2 and pipe MN3, its output node c produces negative edge signal, again through impact damper I1 and or door I3 after by generation rising edge signal, thus triggering d type flip flop below, 0 upset that this d type flip flop is exported is 1 i.e. generation alarm signal A LARM; Alarm signal A LARM resets by the reset signal that so far waiting system feeds back by this d type flip flop, and recovers initial armed state.
Below explain and detect negative sense burr signal trigger mechanism on power supply:
Coordinate see shown in Fig. 4, Fig. 5, suppose that power supply VCC occurs that edge slope and the burr degree of depth all meet the requirements of downward burr (Fig. 4), be then a relatively stable power supply by the power supply VCCin after low-pass filter, so source electrode and grid meet the PMOS MP3 of power supply VCCin and VCC respectively | and VGS| magnitude of voltage is the electric potential difference VPP of power supply VCCin and VCC
(VCCin-VCC), the burr degree of depth of the downward burr namely produced close to above-mentioned hypothesis.Suppose that edge slope and the burr degree of depth of this burr all reach requirement above, therefore pipe MP3 | VGS| magnitude of voltage will exceed the threshold voltage of self | Vthp ' |, therefore pipe MP3 will open and charge to electric capacity C3.Because current source MN4 is by the current mirror (bias current that can arrange is lower) of pipe MN1, and the very fast current potential by node b is charged to enough large by the conducting of pipe MP3 instantaneously, this voltage enough reaches the turnover voltage Vth_MN5 of the asymmetric phase inverter be made up of pipe MP4 and pipe MN5, its output node d produces negative edge signal, again through impact damper I2 and or door I3 after by generation rising edge signal, thus triggering d type flip flop below, 0 upset that this d type flip flop is exported is 1 i.e. generation alarm signal A LARM; Alarm signal A LARM resets by the reset signal that so far waiting system feeds back by d type flip flop, and recovers initial armed state.
Although content of the present invention has done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.After those skilled in the art have read foregoing, for multiple amendment of the present invention and substitute will be all apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (10)
1. a power supply burr signal testing circuit for anti-source attack, is characterized in that, comprise:
Low-pass filter, monitored power supply is divided into the first power supply VCC before filtering by it, and through the filtered second source VCCin of this low-pass filter;
First kind phase inverter, comprises the PMOS MP1 and NMOS tube NM2 that are connected; Source electrode and the grid of pipe MP1 are connected the first power supply VCC and second source VCCin respectively; The node a that the drain electrode that electric capacity C2 is connected to pipe MP1 is connected with the drain electrode of pipe MN2;
First phase inverter, comprises the PMOS MP2 and NMOS tube MN3 that are connected; The tie point of the grid of pipe MP2 and the grid of pipe MN3, is connected to the node a of described first kind phase inverter; The node c that the drain electrode of pipe MP2 is connected with the drain electrode of pipe MN3, is connected to logical block;
Wherein, as the electric potential difference VPP of the first power supply VCC and second source VCCin
(VCC-VCCin)exceed the threshold voltage of pipe MP1 | during Vthp|, pipe MP1 opens and charges to electric capacity C2, and then when making the current potential of node a be promoted to the turnover voltage Vth_MN3 of the first phase inverter, the node c of the first phase inverter sends the first trigger pip to logical block, makes logical block produce the first alerting signal and reports to the police to the forward burr that the first power supply VCC occurs.
2. the power supply burr signal testing circuit of anti-source attack as claimed in claim 1, is characterized in that, also comprise:
Equations of The Second Kind phase inverter, comprises the PMOS MP3 and NMOS tube NM4 that are connected; Grid and the source electrode of pipe MP3 are connected the first power supply VCC and second source VCCin respectively; The node b that the drain electrode that electric capacity C3 is connected to pipe MP3 is connected with the drain electrode of pipe MN4;
Second phase inverter, comprises the PMOS MP4 and NMOS tube MN5 that are connected; The tie point of the grid of pipe MP4 and the grid of pipe MN5, is connected to the node b of described Equations of The Second Kind phase inverter; The node d that the drain electrode of pipe MP4 is connected with the drain electrode of pipe MN5, is connected to logical block;
Wherein, as the electric potential difference VPP of second source VCCin and the first power supply VCC
(VCCin-VCC)exceed the threshold voltage of pipe MP3 | Vthp ' | time, pipe MP3 opens and charges to electric capacity C3, and then when making the current potential of node b be promoted to the turnover voltage Vth_MN5 of the second phase inverter, the node d of the second phase inverter sends the second trigger pip to logical block, makes logical block produce the second alerting signal and reports to the police to the negative sense burr that the first power supply VCC occurs.
3. the power supply burr signal testing circuit of anti-source attack as claimed in claim 2, is characterized in that,
In described logical block, comprise further:
First impact damper, its input end is connected to the node c of described first phase inverter, carries out shaping to the first trigger pip that the first phase inverter exports;
Second impact damper, its input end is connected to the node d of described second phase inverter, carries out shaping to the second trigger pip that the second phase inverter exports;
Or door, two input end is connected to the output terminal of the first impact damper and the second impact damper respectively;
D type flip flop, its input end is connected to or the output terminal of door, comes corresponding generation first alerting signal and the second alerting signal according to the first trigger pip after shaping and logical OR computing and the second trigger pip.
4. the power supply burr signal testing circuit of anti-source attack as claimed in claim 3, is characterized in that,
Described d type flip flop is provided with clear terminal or set end, receives the reset signal externally to its feedback or asserts signal, resets or set the signal that this d type flip flop exports.
5. the power supply burr signal testing circuit of anti-source attack as claimed in claim 2, is characterized in that,
Described first phase inverter and the second phase inverter are asymmetrical phase inverters.
6. the power supply burr signal testing circuit of anti-source attack as claimed in claim 2, is characterized in that,
The grid of described pipe MN2 and the grid of pipe MN4, be all connected to grid and the bias voltage of NMOS tube MN1, makes pipe MN2, mirror image that the electric current of pipe MN4 is the electric current of pipe MN1.
7. the power supply burr signal testing circuit of anti-source attack as claimed in claim 1, is characterized in that,
Described low-pass filter comprises resistance R1 and the electric capacity C1 of series connection, by the second source VCCin after the series connection point output filtering of resistance R1 and electric capacity C1.
8. a power supply burr signal detection method for anti-source attack, is characterized in that, comprise following process:
Low-pass filter is set, monitored power supply is divided into the first power supply VCC before filtering and filtered second source VCCin;
In first kind phase inverter, make the tie point of the drain electrode of PMOS MP1 and the drain electrode of NMOS tube NM2 as output node a, be connected with the input node of electric capacity C2 and the first phase inverter respectively;
In Equations of The Second Kind phase inverter, make the tie point of the drain electrode of PMOS MP3 and the drain electrode of NMOS tube NM4 as output node b, be connected with the input node of electric capacity C3 and the second phase inverter respectively;
Described pipe MP1's | VGS| magnitude of voltage is the electric potential difference VPP of the first power supply VCC and second source VCCin
(VCC-VCCin)as pipe MP1 | VGS| magnitude of voltage exceedes the threshold voltage of pipe MP1 | during Vthp|, pipe MP1 opens and charges to electric capacity C2, and then when making the current potential of the output node a of first kind phase inverter be promoted to the turnover voltage Vth_MN3 of described first phase inverter, the output node c of the first phase inverter exports the first trigger pip;
Described pipe MP3's | VGS| magnitude of voltage is the electric potential difference VPP of second source VCCin and the first power supply VCC
(VCCin-VCC)as pipe MP3 | VGS| magnitude of voltage exceedes the threshold voltage of pipe MP3 | Vthp ' | time, pipe MP3 opens and charges to electric capacity C3, and then when making the current potential of the output node b of Equations of The Second Kind phase inverter be promoted to the turnover voltage Vth_MN5 of described second phase inverter, the output node d of the second phase inverter exports the second trigger pip;
Described first trigger pip or the second trigger pip are negative edge signal, rising edge signal is obtained after the computing of shaping and logical OR, make a d type flip flop export the first alerting signal or the second alerting signal that are overturn by low level to high level according to this rising edge signal, the forward burr that the first power supply VCC occurs or negative sense burr are reported to the police.
9. the power supply burr signal detection method of anti-source attack as claimed in claim 8, is characterized in that,
When the electric potential difference of described first power supply VCC and second source VCCin is zero, the output node a of described first kind phase inverter and the output node b of described Equations of The Second Kind phase inverter exports no-voltage, make the output node d of the output node c of described first phase inverter and described second phase inverter export high level, after the computing of shaping and logical OR, make described d type flip flop be in export be zero hold mode.
10. the power supply burr signal detection method of anti-source attack as claimed in claim 8, is characterized in that,
After described d type flip flop exports the first alerting signal or the second alerting signal, by the reset signal fed back externally to this d type flip flop, the first alerting signal or the second alerting signal are reset, this d type flip flop is returned to export be zero hold mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410689271.2A CN104459564B (en) | 2014-11-26 | 2014-11-26 | The power supply burr signal detection circuit and detection method of a kind of anti-source attack |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410689271.2A CN104459564B (en) | 2014-11-26 | 2014-11-26 | The power supply burr signal detection circuit and detection method of a kind of anti-source attack |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104459564A true CN104459564A (en) | 2015-03-25 |
| CN104459564B CN104459564B (en) | 2017-09-05 |
Family
ID=52905920
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410689271.2A Active CN104459564B (en) | 2014-11-26 | 2014-11-26 | The power supply burr signal detection circuit and detection method of a kind of anti-source attack |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104459564B (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105116353A (en) * | 2015-09-29 | 2015-12-02 | 成都贝发信息技术有限公司 | Low-power consumption power source detector based on information system |
| CN105242220A (en) * | 2015-09-29 | 2016-01-13 | 成都贝发信息技术有限公司 | Wide-range power supply detection apparatus based on information system |
| CN110462410A (en) * | 2019-06-24 | 2019-11-15 | 深圳市汇顶科技股份有限公司 | Burr signal detection circuit, safety chip and electronic equipment |
| CN110462415A (en) * | 2019-06-24 | 2019-11-15 | 深圳市汇顶科技股份有限公司 | Burr signal detection circuit, safety chip and electronic equipment |
| CN111722020A (en) * | 2019-03-18 | 2020-09-29 | 深圳市汇顶科技股份有限公司 | Burr detection circuit |
| CN111835187A (en) * | 2019-04-15 | 2020-10-27 | 合肥格易集成电路有限公司 | Switching circuit |
| CN112148103A (en) * | 2020-09-09 | 2020-12-29 | 北京中电华大电子设计有限责任公司 | Circuit for protecting power supply attack implemented from PAD |
| WO2021026914A1 (en) * | 2019-08-15 | 2021-02-18 | 深圳市汇顶科技股份有限公司 | Power glitch signal detection circuit, secure chip and electronic device |
| WO2021196093A1 (en) * | 2020-04-01 | 2021-10-07 | 深圳市汇顶科技股份有限公司 | Voltage attack detection circuit and chip |
| CN115356513A (en) * | 2022-08-09 | 2022-11-18 | 苏州聚元微电子股份有限公司 | Digital detection circuit for power supply fluctuation |
| TWI804449B (en) * | 2022-01-05 | 2023-06-01 | 聯發科技股份有限公司 | Chip with power-glitch detection |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6894540B1 (en) * | 2003-12-17 | 2005-05-17 | Freescale Semiconductor, Inc. | Glitch removal circuit |
| CN101943728A (en) * | 2009-07-06 | 2011-01-12 | 北京中电华大电子设计有限责任公司 | Detection circuit capable of preventing attack of power supply burrs |
| CN101943729A (en) * | 2009-07-06 | 2011-01-12 | 北京中电华大电子设计有限责任公司 | Circuit for quickly detecting power sources and glitches on ground with low power consumption |
-
2014
- 2014-11-26 CN CN201410689271.2A patent/CN104459564B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6894540B1 (en) * | 2003-12-17 | 2005-05-17 | Freescale Semiconductor, Inc. | Glitch removal circuit |
| CN101943728A (en) * | 2009-07-06 | 2011-01-12 | 北京中电华大电子设计有限责任公司 | Detection circuit capable of preventing attack of power supply burrs |
| CN101943729A (en) * | 2009-07-06 | 2011-01-12 | 北京中电华大电子设计有限责任公司 | Circuit for quickly detecting power sources and glitches on ground with low power consumption |
Cited By (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105242220A (en) * | 2015-09-29 | 2016-01-13 | 成都贝发信息技术有限公司 | Wide-range power supply detection apparatus based on information system |
| CN105116353A (en) * | 2015-09-29 | 2015-12-02 | 成都贝发信息技术有限公司 | Low-power consumption power source detector based on information system |
| CN111722020B (en) * | 2019-03-18 | 2023-03-14 | 深圳市汇顶科技股份有限公司 | Burr detection circuit |
| CN111722020A (en) * | 2019-03-18 | 2020-09-29 | 深圳市汇顶科技股份有限公司 | Burr detection circuit |
| CN111835187B (en) * | 2019-04-15 | 2021-06-11 | 合肥格易集成电路有限公司 | Switching circuit |
| CN111835187A (en) * | 2019-04-15 | 2020-10-27 | 合肥格易集成电路有限公司 | Switching circuit |
| CN110462415B (en) * | 2019-06-24 | 2021-12-28 | 深圳市汇顶科技股份有限公司 | Burr signal detection circuit, safety chip and electronic equipment |
| CN110462415A (en) * | 2019-06-24 | 2019-11-15 | 深圳市汇顶科技股份有限公司 | Burr signal detection circuit, safety chip and electronic equipment |
| WO2020257959A1 (en) * | 2019-06-24 | 2020-12-30 | 深圳市汇顶科技股份有限公司 | Glitch signal detection circuit, security chip, and electronic apparatus |
| US11763037B2 (en) | 2019-06-24 | 2023-09-19 | Shenzhen GOODIX Technology Co., Ltd. | Power glitch signal detection circuit, security chip and electronic apparatus |
| US11609277B2 (en) | 2019-06-24 | 2023-03-21 | Shenzhen GOODIX Technology Co., Ltd. | Power glitch signal detection circuit and security chip |
| EP3783371A4 (en) * | 2019-06-24 | 2021-04-28 | Shenzhen Goodix Technology Co., Ltd. | Glitch signal detection circuit, security chip, and electronic apparatus |
| CN110462410A (en) * | 2019-06-24 | 2019-11-15 | 深圳市汇顶科技股份有限公司 | Burr signal detection circuit, safety chip and electronic equipment |
| WO2020257958A1 (en) * | 2019-06-24 | 2020-12-30 | 深圳市汇顶科技股份有限公司 | Glitch signal detection circuit, security chip, and electronic device |
| US11187731B2 (en) | 2019-08-15 | 2021-11-30 | Shenzhen GOODIX Technology Co., Ltd. | Power glitch signal detection circuit, security chip and electronic apparatus |
| CN112673263A (en) * | 2019-08-15 | 2021-04-16 | 深圳市汇顶科技股份有限公司 | Burr signal detection circuit, safety chip and electronic equipment |
| WO2021026914A1 (en) * | 2019-08-15 | 2021-02-18 | 深圳市汇顶科技股份有限公司 | Power glitch signal detection circuit, secure chip and electronic device |
| WO2021196093A1 (en) * | 2020-04-01 | 2021-10-07 | 深圳市汇顶科技股份有限公司 | Voltage attack detection circuit and chip |
| CN112148103A (en) * | 2020-09-09 | 2020-12-29 | 北京中电华大电子设计有限责任公司 | Circuit for protecting power supply attack implemented from PAD |
| TWI804449B (en) * | 2022-01-05 | 2023-06-01 | 聯發科技股份有限公司 | Chip with power-glitch detection |
| US11916432B2 (en) | 2022-01-05 | 2024-02-27 | Mediatek Inc. | Chip with power-glitch detection |
| CN115356513A (en) * | 2022-08-09 | 2022-11-18 | 苏州聚元微电子股份有限公司 | Digital detection circuit for power supply fluctuation |
| CN115356513B (en) * | 2022-08-09 | 2023-09-01 | 苏州聚元微电子股份有限公司 | Digital detection circuit for power supply fluctuation |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104459564B (en) | 2017-09-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104459564A (en) | Power source burr signal detecting circuit and method preventing power source attack | |
| CN103034804B (en) | Safety chip and attack detecting circuit thereof | |
| CN102739224B (en) | Omnipolare magnetschalter and method for providing same | |
| CN110462415B (en) | Burr signal detection circuit, safety chip and electronic equipment | |
| CN104714193A (en) | High-precision low-power-consumption power glitch detection circuit | |
| CN108667443B (en) | Power-on reset circuit | |
| CN107576930B (en) | power supply and relay status detection circuit and method | |
| CN103675421A (en) | Power burr signal detection circuit and detection method thereof | |
| CN103873030A (en) | Latched fault detection circuit and realizing method thereof | |
| CN103712642A (en) | Method and apparatus for realizing self-detection of safety detector | |
| CN111095004B (en) | Detection circuit, safety chip and electronic equipment of electromagnetic fault injection | |
| CN204964722U (en) | Power supply voltage negative sense detection circuitry among information interaction system | |
| CN112673263A (en) | Burr signal detection circuit, safety chip and electronic equipment | |
| CN104579259B (en) | Clock signal missing detecting circuit | |
| CN106200846B (en) | Power on and off reset circuit and chip | |
| EP3783372B1 (en) | Glitch signal detection circuit, security chip, and electronic device | |
| CN108169694A (en) | It is a kind of that there is temperature, the burr detection circuit of process compensation function | |
| CN101566645B (en) | Detection circuit for power supply voltage pulse interference | |
| CN203761353U (en) | Fault detection circuit with latch | |
| CN106712753A (en) | Electrostatic protection circuit | |
| CN111130536A (en) | Circuit with aging detection and PUF (physical unclonable function) functions | |
| CN105891734B (en) | A kind of super low-power consumption power sense circuit | |
| CN202903970U (en) | Button detection circuit for electric energy meter | |
| CN201210174Y (en) | Detection circuit used for main voltage pulse interference | |
| CN205015464U (en) | Power supply voltage forward detection circuitry among information interaction system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 200233 Room 704, Building 2, No. 2570 Hechuan Road, Minhang District, Shanghai Patentee after: Shanghai Hangxin Electronic Technology Co.,Ltd. Address before: 200241, building 6, building 555, No. 8, Dongchuan Road, Shanghai, Minhang District Patentee before: SHANGHAI AISINOCHIP ELECTRONIC TECHNOLOGY Co.,Ltd. |