CN104459564B - The power supply burr signal detection circuit and detection method of a kind of anti-source attack - Google Patents
The power supply burr signal detection circuit and detection method of a kind of anti-source attack Download PDFInfo
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- CN104459564B CN104459564B CN201410689271.2A CN201410689271A CN104459564B CN 104459564 B CN104459564 B CN 104459564B CN 201410689271 A CN201410689271 A CN 201410689271A CN 104459564 B CN104459564 B CN 104459564B
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Abstract
The present invention relates to a kind of power supply burr signal detecting system of anti-source attack and method, low pass filter, two class phase inverters, two phase inverters and logic unit are provided with.When the PMOS in class phase inverter | VGS | magnitude of voltage, that is, the electrical potential difference of power supply exceedes the threshold voltage absolute value of PMOS before and after filtering, and judges that power supply burr occurs in the power supply before filtering, so as to trigger burr attack alarm.The size and threshold value of frequency filtering and PMOS together decide on the edge slope and burr depth of power supply burr.The present invention has circuit structure simple, saves chip area, easily realizes, fast response time is less prone to erroneous judgement, the advantages of quiescent dissipation is extremely low.
Description
Technical field
The present invention relates to power technology, the power supply burr signal detection circuit of more particularly to a kind of anti-source attack and detection
Method.
Background technology
With the extensive use of smart card, the smart card in security fields becomes the key object of assault.Power supply
Burr（power glitch）Attack is the supply voltage or ground voltage that intelligent card chip is input to by quickly changing so that
Some circuit units in chip are affected, and cause one or more circuit unit to enter error condition, so as to cause core
Piece processor is skipped or implements the operation of mistake according to the state of mistake, and then makes the security information hidden in chip gradual
A kind of attack meanses being exposed.
The content of the invention
Circuit and detection method are detected the invention provides a kind of power supply burr signal of anti-source attack, it is simple in construction,
Detection is quick effective.
In order to achieve the above object, a technical scheme of the invention is to provide a kind of power supply burr letter of anti-source attack
Number detection circuit, wherein including：
Low pass filter, monitored power supply is divided into the first power supply VCC before filtering by it, and passes through the low pass filter
Filtered second source VCCin；
First kind phase inverter, includes the PMOS MP1 and NMOS tube MN2 being connected；Pipe MP1 source electrode and grid connects respectively
Meet the first power supply VCC and second source VCCin；Electric capacity C2 is connected to the node a that pipe MP1 drain electrode is connected with pipe MN2 drain electrode；
First phase inverter, includes the PMOS MP2 and NMOS tube MN3 being connected；Pipe MP2 grid and pipe MN3 grid
Tie point, be connected to the node a of the first kind phase inverter；The node c that pipe MP2 drain electrode is connected with pipe MN3 drain electrode, even
It is connected to logic unit；
Wherein, as the first power supply VCC and second source VCCin electrical potential difference VPP（VCC- VCCin）Threshold value electricity more than pipe MP1
Pressure | Vthp | when, pipe MP1 is opened to charge to electric capacity C2, and then node a current potential is promoted to the upset of the first phase inverter
During voltage Vth_MN3, the node c of the first phase inverter sends the first trigger signal to logic unit, logic unit is produced first
Alarm signal is alarmed the positive burr occurred on the first power supply VCC.
Preferably, also included in power supply burr signal detection circuit：
Equations of The Second Kind phase inverter, includes the PMOS MP3 and NMOS tube MN4 being connected；Pipe MP3 grid and source electrode connects respectively
Meet the first power supply VCC and second source VCCin；Electric capacity C3 is connected to the node b that pipe MP3 drain electrode is connected with pipe MN4 drain electrode；
Second phase inverter, includes the PMOS MP4 and NMOS tube MN5 being connected；Pipe MP4 grid and pipe MN5 grid
Tie point, be connected to the node b of the Equations of The Second Kind phase inverter；The node d that pipe MP4 drain electrode is connected with pipe MN5 drain electrode, even
It is connected to logic unit；
Wherein, as second source VCCin and the first power supply VCC electrical potential difference VPP（VCCin-VCC）Threshold value electricity more than pipe MP3
Pressure | Vthp ' | when, pipe MP3 is opened to charge to electric capacity C3, and then node b current potential is promoted to the upset of the second phase inverter
During voltage Vth_MN5, the node d of the second phase inverter sends the second trigger signal to logic unit, logic unit is produced second
Alarm signal is alarmed the negative sense burr occurred on the first power supply VCC.
Preferably, in described logic unit, further include：
First buffer, its input is connected to the node c of first phase inverter, first exported to the first phase inverter
Trigger signal carries out shaping；
Second buffer, its input is connected to the node d of second phase inverter, second exported to the second phase inverter
Trigger signal carries out shaping；
OR gate, two input is respectively connecting to the output end of the first buffer and the second buffer；
D type flip flop, its input is connected to the output end of OR gate, according to the first triggering after shaping and logic or computing
Signal and the second trigger signal accordingly produce the first alarm signal and the second alarm signal.
Preferably, the d type flip flop is provided with clear terminal or set end, receives the outside reset signal fed back to it or puts
Position signal, is zeroed out or set to the signal that the d type flip flop is exported.
Preferably, first phase inverter and the second phase inverter are asymmetrical phase inverters.
Preferably, the grid of the pipe MN2 and pipe MN4 grid, is connected to NMOS tube MN1 grid and biased electrical
Pressure, make pipe MN2, pipe MN4 electric current for pipe MN1 electric current mirror image.
Preferably, the low pass filter includes the resistance R1 and electric capacity C1 of series connection, by connecting for resistance R1 and electric capacity C1
Second source VCCin after point output filtering.
Another technical scheme of the present invention is to provide a kind of power supply burr signal detection method of anti-source attack, wherein
Include procedure below：
Low pass filter is set, monitored power supply is divided into the first power supply VCC before filtering and filtered second electricity
Source VCCin；
In first kind phase inverter, the tie point of PMOS MP1 drain electrode and NMOS tube MN2 drain electrode is set to be saved as output
Point a, respectively the input node with electric capacity C2 and the first phase inverter be connected；
In Equations of The Second Kind phase inverter, the tie point of PMOS MP3 drain electrode and NMOS tube MN4 drain electrode is set to be saved as output
Point b, respectively the input node with electric capacity C3 and the second phase inverter be connected；
The pipe MP1's | VGS | magnitude of voltage is the first power supply VCC and second source VCCin electrical potential difference VPP（VCC-VCCin）,
As pipe MP1 | VGS | magnitude of voltage exceedes pipe MP1 threshold voltage | Vthp | when, pipe MP1 is opened to charge to electric capacity C2, and then makes
When the output node a of first kind phase inverter current potential is promoted to the turnover voltage Vth_MN3 of first phase inverter, first is anti-phase
The output node c of device exports the first trigger signal；
The pipe MP3's | VGS | magnitude of voltage is second source VCCin and the first power supply VCC electrical potential difference VPP（VCCin-VCC）,
As pipe MP3 | VGS | magnitude of voltage exceedes pipe MP3 threshold voltage | Vthp ' | when, pipe MP3 is opened to charge to electric capacity C3, and then makes
When the output node b of Equations of The Second Kind phase inverter current potential is promoted to the turnover voltage Vth_MN5 of second phase inverter, second is anti-phase
The output node d of device exports the second trigger signal；
First trigger signal or the second trigger signal be trailing edge signal, by shaping and logic or computing after
Rising edge signal is obtained, a d type flip flop is exported the first report overturn by low level to high level according to the rising edge signal
Alert signal or the second alarm signal, to alarm the positive burr or negative sense burr that occur on the first power supply VCC.
Preferably, when the first power supply VCC and second source VCCin electrical potential difference is zero, the first kind phase inverter
Output node a and the Equations of The Second Kind phase inverter output node b output no-voltage, make the output node of first phase inverter
The output node d output high level of c and second phase inverter, by shaping and logic or computing after trigger the D
Device is in the hold mode for being output as zero.
Preferably, after the d type flip flop exports the first alarm signal or the second alarm signal, triggered from outside to the D
The reset signal of device feedback resets the first alarm signal or the second alarm signal, returns to the d type flip flop and is output as zero
Hold mode.
Compared with prior art, the power supply burr detection circuit and detection method of anti-source attack of the present invention, its electricity
Road sampling end is made up of RC wave filters and PMOS, by the power supply VCC with burr and the power supply after RC filter filterings
Whether VCCin voltage difference reaches the threshold voltage of the PMOS to determine whether power supply burr, if above-mentioned voltage difference
More than this PMOS threshold voltage when will trigger burr attack alarm.The size and threshold of RC frequency filterings and PMOS
Value together decides on the edge slope of the power supply burr of judgement（glitch slope）And burr depth.The present invention has circuit structure
Simply, chip area is saved, is easily realized, fast response time is less prone to erroneous judgement, the advantages of quiescent dissipation is extremely low.
Brief description of the drawings
Fig. 1 is that the power supply burr signal of anti-source attack of the present invention detects the structure principle chart of circuit；
Fig. 2 is the schematic diagram that heretofore described power supply burr signal is positive burr signal；
Fig. 3 is the schematic diagram of key signal action when heretofore described power supply burr signal is positive burr signal；
Fig. 4 is the schematic diagram that heretofore described power supply burr signal is negative sense burr signal；
Fig. 5 is the schematic diagram of key signal action when heretofore described power supply burr signal is negative sense burr signal.
Embodiment
Below in conjunction with the embodiment of the brief description of the drawings present invention.
As shown in figure 1, in the power supply burr signal detection circuit of anti-source attack of the present invention, being provided with RC low pass filtereds
Ripple device, it includes the resistance R1 and electric capacity C1 of series connection.Monitored power supply is divided into band hair before filtering by the RC low pass filters
The power supply VCC of thorn, and the power supply VCCin after the filtering of RC low pass filters without frequency glitches.
Two PMOSs MP1 and MP3 are set；Make pipe MP1 source electrode, pipe MP3 grid, respectively with band hair before above-mentioned filtering
The power supply VCC connections of thorn；By pipe MP1 grid, pipe MP3 source electrode, respectively with the power supply VCCin after above-mentioned filtering without burr
Connection.
Two current source NMOS tubes MN2 and MN4 are set；Pipe MP1 is connected with pipe MN2 to form first class phase inverter；Class
As, pipe MP3 is connected with pipe MN4 to form second class phase inverter；In the output stage of the two class phase inverters, it is connected to
Electric capacity C2, C3, thus in the quiescent state（When power supply does not have burr）Energy loss will not be produced.
Wherein, electric capacity C2 is connected to the node a that pipe MP1 drain electrodes are connected with pipe MN2 drain electrodes；Electric capacity C3 is connected to pipe MP3 leakages
The node b that pole is connected with pipe MN4 drain electrodes.Pipe MN2 grid and pipe MN4 grid, are respectively connecting to another NMOS tube MN1
Grid.
Two other PMOS MP2 and MP4, and two other NMOS tube MN3 and MN5 are set；Pipe MP2 and pipe MN3 is connected
Connect to form first phase inverter；Similarly, pipe MP4 and pipe MN5 are connected to form second phase inverter.Can be anti-phase by the two
Device is arranged to asymmetrical phase inverter, and its trigging signal is set to lower to increase the susceptibility for responding power supply burr.
By the tie point of pipe MP2 grids and pipe MN3 grids, be connected with above-mentioned electric capacity C2 anode, that is, be connected to described in
Node a；By pipe MP4 grids and the tie point of pipe MN5 grids, it is connected with above-mentioned electric capacity C3 anode, that is, is connected to described section
Point b.
Source electrode, the pipe MP4 source electrode of the pipe MP2, is respectively connecting to before above-mentioned filtering the power supply VCC with burr.By
The node c that pipe MP2 drain electrodes are connected with pipe MN3 drain electrodes in one phase inverter, with first buffer（buffer）I1 input
Connection；Pipe MP4 drain electrodes in second phase inverter are drained with pipe MN5 the node d being connected, the input with second buffer I2
Connection.Two buffers I1, I2 output end are connected to OR gate I3 two inputs, and the output end of the OR gate I3 is connected to
D type flip flop I4 input.
Response of the signal of the two phase inverters output to burr is to embody in the form of a pulse, by the buffer
Exported after I1, I2 shaping and OR gate I3 computings, the pulse to any of above phase inverter is responded；Triggered again by rising edge
D type flip flop I4 obtains the alarm signal A LARM of desired high level（Low level alarm signal can also be obtained in other examples
Number）；The clear terminal CLR and set end SET of the d type flip flop, are zeroed out and set by the signal control of system feedback.
Original state is that on power supply when do not have burr, power supply VCC and VCCin electrical potential difference are 0, make MP1 and MP3 this
Two PMOSs are closed, and now electric capacity C2 and C3 electric charge will be by current source MN2 and MN4（Their electric current is by pipe
MN1 mirror images）Electric discharge, therefore node a and b voltage are 0 when static, by by pipe MP2 and pipe MN3, pipe MP4 and pipe
Two phase inverters of MN5 compositions, export high level respectively, then are output as low level 0 after buffer I1 and I2, OR gate I3,
Then the d type flip flop of rising edge triggering below is in hold mode, is defaulted as 0.It should be noted that patrolling in right frame in Fig. 1
Collecting partial power domain can be inconsistent with detected power domain, but requires rational level logic conversion.
Positive burr signal trigger mechanism on detection power supply explained below：
Coordinate referring to shown in Fig. 2, Fig. 3, it is assumed that edge slope occurs in power supply VCC（glitch slope）And burr depth is equal
Reach the upward burr of requirement（Fig. 2）, it is then a power supply relatively stablized by the power supply VCCin after low pass filter,
So source electrode and grid meet power supply VCC and VCCin PMOS MP1 respectively | VGS | magnitude of voltage is power supply VCC and VCCin
Electrical potential difference VPP（VCC- VCCin）, i.e., the burr depth of the upward burr produced close to above-mentioned hypothesis.This hair is hypothesized above
The edge slope and burr depth of thorn reach requirement, therefore pipe MP1 | VGS | magnitude of voltage is by more than the threshold voltage of itself |
Vthp |, thus pipe MP1 will open and to electric capacity C2 charge.Because current source MN2 is by pipe MN1 current mirror（It can set
The bias current put is relatively low）, and pipe MP1 conducting moment node a current potential is charged to by quickly sufficiently large, this voltage reaches enough
Trailing edge letter is produced to the turnover voltage Vth_MN3 by pipe MP2 and pipe the MN3 asymmetric phase inverter constituted, its output node c
Number, then a rising edge signal will be produced after buffer I1 and OR gate I3, so as to trigger d type flip flop below, touch the D
0 upset for sending out device output produces alarm signal A LARM for 1；So far the d type flip flop carrys out the reset signal that waiting system feeds back
Alarm signal A LARM is reset, and recovers initial armed state.
Negative sense burr signal trigger mechanism on detection power supply explained below：
Coordinate referring to shown in Fig. 4, Fig. 5, it is assumed that edge slope occurs in power supply VCC and burr depth reaches the downward of requirement
Burr（Fig. 4）, it is then a power supply relatively stablized by the power supply VCCin after low pass filter, then source electrode and grid
Power supply VCCin and VCC PMOS MP3 are met respectively | VGS | magnitude of voltage is power supply VCCin and VCC electrical potential difference
VPP（VCCin-VCC）, i.e., the burr depth of the downward burr produced close to above-mentioned hypothesis.The side of this burr is hypothesized above
Requirement is reached along slope and burr depth, therefore pipe MP3 | VGS | magnitude of voltage is by more than the threshold voltage of itself | Vthp ' |,
Therefore pipe MP3 will be opened and electric capacity C3 will be charged.Because current source MN4 is by pipe MN1 current mirror（What can be set is inclined
Put electric current relatively low）, and pipe MP3 conducting moment node b current potential is charged to by quickly sufficiently large, this voltage reaches by pipe enough
The turnover voltage Vth_MN5 of the asymmetric phase inverter of MP4 and pipe MN5 compositions, its output node d produces trailing edge signal, then passes through
A rising edge signal will be produced by crossing after buffer I2 and OR gate I3, so as to trigger d type flip flop below, make the d type flip flop defeated
0 upset gone out produces alarm signal A LARM for 1；So far the reset signal that d type flip flop feeds back waiting system is by alarm signal
Number ALARM is reset, and recovers initial armed state.
Although present disclosure is discussed in detail by above preferred embodiment, but it should be appreciated that above-mentioned
Description is not considered as limitation of the present invention.After those skilled in the art have read the above, for the present invention's
A variety of modifications and substitutions all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (9)
1. the power supply burr signal detection circuit of a kind of anti-source attack, it is characterised in that include：
Low pass filter, monitored power supply is divided into the first power supply VCC before filtering by it, and by low pass filter filtering
Second source VCCin afterwards；
First kind phase inverter, includes the PMOS MP1 and NMOS tube MN2 being connected；Pipe MP1 source electrode and grid connects respectively
One power supply VCC and second source VCCin；Electric capacity C2 is connected to the node a that pipe MP1 drain electrode is connected with pipe MN2 drain electrode；
First phase inverter, includes the PMOS MP2 and NMOS tube MN3 being connected；The company of pipe MP2 grid and pipe MN3 grid
Contact, is connected to the node a of the first kind phase inverter；The node c that pipe MP2 drain electrode is connected with pipe MN3 drain electrode, is connected to
Logic unit；
Wherein, as the first power supply VCC and second source VCCin electrical potential difference VPP（VCC- VCCin）More than pipe MP1 threshold voltage |
Vthp | when, pipe MP1 is opened to charge to electric capacity C2, and then node a current potential is promoted to the turnover voltage of the first phase inverter
During Vth_MN3, the node c of the first phase inverter sends the first trigger signal to logic unit, logic unit is produced first and alarms
Signal is alarmed the positive burr occurred on the first power supply VCC；
The grid of the pipe MN2 is connected to NMOS tube MN1 grid and bias voltage, the electric current that the electric current for making pipe MN2 is pipe MN1
Mirror image.
2. the power supply burr signal detection circuit of anti-source attack as claimed in claim 1, it is characterised in that also include：
Equations of The Second Kind phase inverter, includes the PMOS MP3 and NMOS tube MN4 being connected；Pipe MP3 grid and source electrode connects respectively
One power supply VCC and second source VCCin；Electric capacity C3 is connected to the node b that pipe MP3 drain electrode is connected with pipe MN4 drain electrode；
Second phase inverter, includes the PMOS MP4 and NMOS tube MN5 being connected；The company of pipe MP4 grid and pipe MN5 grid
Contact, is connected to the node b of the Equations of The Second Kind phase inverter；The node d that pipe MP4 drain electrode is connected with pipe MN5 drain electrode, is connected to
Logic unit；
Wherein, as second source VCCin and the first power supply VCC electrical potential difference VPP（VCCin- VCC）More than pipe MP3 threshold voltage |
Vthp ' | when, pipe MP3 is opened to charge to electric capacity C3, and then node b current potential is promoted to the upset electricity of the second phase inverter
When pressing Vth_MN5, the node d of the second phase inverter sends the second trigger signal to logic unit, logic unit is produced second and reports
Signal is warned to alarm to the negative sense burr occurred on the first power supply VCC.
3. the power supply burr signal detection circuit of anti-source attack as claimed in claim 2, it is characterised in that
In described logic unit, further include：
First buffer, its input is connected to the node c of first phase inverter, the first triggering exported to the first phase inverter
Signal carries out shaping；
Second buffer, its input is connected to the node d of second phase inverter, the second triggering exported to the second phase inverter
Signal carries out shaping；
OR gate, two input is respectively connecting to the output end of the first buffer and the second buffer；
D type flip flop, its input is connected to the output end of OR gate, according to the first trigger signal after shaping and logic or computing
And second trigger signal come accordingly produce the first alarm signal and the second alarm signal.
4. the power supply burr signal detection circuit of anti-source attack as claimed in claim 3, it is characterised in that
The d type flip flop is provided with clear terminal or set end, the outside reset signal or set signal fed back to it is received, to this
The signal of d type flip flop output is zeroed out or set.
5. the power supply burr signal detection circuit of anti-source attack as claimed in claim 2, it is characterised in that
First phase inverter and the second phase inverter are asymmetrical phase inverters.
6. the power supply burr signal detection circuit of anti-source attack as claimed in claim 2, it is characterised in that
The grid of the pipe MN4 is connected to NMOS tube MN1 grid and bias voltage, the electric current that the electric current for making pipe MN4 is pipe MN1
Mirror image.
7. the power supply burr signal detection circuit of anti-source attack as claimed in claim 1, it is characterised in that
The low pass filter includes the resistance R1 and electric capacity C1 of series connection, after resistance R1 and electric capacity C1 series connection point output filtering
Second source VCCin.
8. the power supply burr signal detection method of a kind of anti-source attack, it is characterised in that include procedure below：
Low pass filter is set, monitored power supply is divided into the first power supply VCC and filtered second source before filtering
VCCin；
In first kind phase inverter, make the tie point of PMOS MP1 drain electrode and NMOS tube MN2 drain electrode as output node a,
The input node with electric capacity C2 and the first phase inverter is connected respectively；
In Equations of The Second Kind phase inverter, make the tie point of PMOS MP3 drain electrode and NMOS tube MN4 drain electrode as output node b,
The input node with electric capacity C3 and the second phase inverter is connected respectively；
The pipe MP1's | VGS | magnitude of voltage is the first power supply VCC and second source VCCin electrical potential difference VPP（VCC- VCCin）, when
Pipe MP1's | VGS | magnitude of voltage exceedes pipe MP1 threshold voltage | Vthp | when, pipe MP1 is opened to charge to electric capacity C2, and then makes the
When the output node a of one class phase inverter current potential is promoted to the turnover voltage Vth_MN3 of first phase inverter, the first phase inverter
Output node c export the first trigger signal；
The pipe MP3's | VGS | magnitude of voltage is second source VCCin and the first power supply VCC electrical potential difference VPP（VCCin- VCC）, when
Pipe MP3's | VGS | magnitude of voltage exceedes pipe MP3 threshold voltage | Vthp ' | when, pipe MP3 is opened to charge to electric capacity C3, and then makes the
When the output node b of two class phase inverters current potential is promoted to the turnover voltage Vth_MN5 of second phase inverter, the second phase inverter
Output node d export the second trigger signal；
First trigger signal or the second trigger signal be trailing edge signal, by shaping and logic or computing after obtain
Rising edge signal, makes a d type flip flop export the first alarm signal overturn by low level to high level according to the rising edge signal
Number or the second alarm signal, to alarm the positive burr or negative sense burr that occur on the first power supply VCC；
When the first power supply VCC and second source VCCin electrical potential difference is zero, the output node a of the first kind phase inverter
And the output node b output no-voltages of the Equations of The Second Kind phase inverter, make the output node c and described second of first phase inverter
Phase inverter output node d output high level, by shaping and logic or computing after make the d type flip flop be in be output as
Zero hold mode.
9. the power supply burr signal detection method of anti-source attack as claimed in claim 8, it is characterised in that
The d type flip flop is exported after the first alarm signal or the second alarm signal, the clearing fed back from outside to the d type flip flop
Signal resets the first alarm signal or the second alarm signal, make the d type flip flop return to be output as zero hold mode.
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| CN111722020B (en) * | 2019-03-18 | 2023-03-14 | 深圳市汇顶科技股份有限公司 | Burr detection circuit |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6894540B1 (en) * | 2003-12-17 | 2005-05-17 | Freescale Semiconductor, Inc. | Glitch removal circuit |
| CN101943728A (en) * | 2009-07-06 | 2011-01-12 | 北京中电华大电子设计有限责任公司 | Detection circuit capable of preventing attack of power supply burrs |
| CN101943729A (en) * | 2009-07-06 | 2011-01-12 | 北京中电华大电子设计有限责任公司 | Circuit for quickly detecting power sources and glitches on ground with low power consumption |
-
2014
- 2014-11-26 CN CN201410689271.2A patent/CN104459564B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6894540B1 (en) * | 2003-12-17 | 2005-05-17 | Freescale Semiconductor, Inc. | Glitch removal circuit |
| CN101943728A (en) * | 2009-07-06 | 2011-01-12 | 北京中电华大电子设计有限责任公司 | Detection circuit capable of preventing attack of power supply burrs |
| CN101943729A (en) * | 2009-07-06 | 2011-01-12 | 北京中电华大电子设计有限责任公司 | Circuit for quickly detecting power sources and glitches on ground with low power consumption |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3783372A4 (en) * | 2019-06-24 | 2021-05-19 | Shenzhen Goodix Technology Co., Ltd. | Glitch signal detection circuit, security chip, and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104459564A (en) | 2015-03-25 |
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