WO2020257958A1 - Glitch signal detection circuit, security chip, and electronic device - Google Patents

Glitch signal detection circuit, security chip, and electronic device Download PDF

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Publication number
WO2020257958A1
WO2020257958A1 PCT/CN2019/092499 CN2019092499W WO2020257958A1 WO 2020257958 A1 WO2020257958 A1 WO 2020257958A1 CN 2019092499 W CN2019092499 W CN 2019092499W WO 2020257958 A1 WO2020257958 A1 WO 2020257958A1
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WO
WIPO (PCT)
Prior art keywords
mos tube
voltage
glitch
signal
mos transistor
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PCT/CN2019/092499
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French (fr)
Chinese (zh)
Inventor
薛建锋
杨江
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深圳市汇顶科技股份有限公司
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to EP19919571.0A priority Critical patent/EP3783372B1/en
Priority to CN201980001100.7A priority patent/CN110462410B/en
Priority to PCT/CN2019/092499 priority patent/WO2020257958A1/en
Priority to US17/026,211 priority patent/US11763037B2/en
Publication of WO2020257958A1 publication Critical patent/WO2020257958A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/76—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16504—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed
    • G01R19/16519—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed using FET's
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16533—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31719—Security aspects, e.g. preventing unauthorised access during test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/40—Testing power supplies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration

Definitions

  • the embodiments of the present application relate to the field of electronics, and more specifically, to glitch signal detection circuits, security chips, and electronic devices.
  • Security chips can be used to realize functions such as user identification and key data storage. They are widely used in the financial field and are a key target of attackers.
  • Attackers can use fault attacks (such as power glitch attacks) to make the chip work in an abnormal state, resulting in chip misbehavior; at this time, the attacker can easily obtain the confidential data in the security chip by using fault analysis technology .
  • fault attacks such as power glitch attacks
  • the glitch signal detection circuit needs to include a resistance-capacitance (RC) sampling structure and a comparator structure.
  • the RC sampling structure uses a low-pass filter to sample the power supply voltage (or ground voltage), and the comparator structure sets a judgment threshold through a resistor divider, and compares the sampled power supply voltage (or ground voltage) with the judgment threshold to determine whether to trigger an alarm signal.
  • the advantage of the RC sampling structure is that it can detect nanosecond (ns)-level glitches, but the RC sampling structure with a larger RC generally requires a larger area overhead.
  • the advantage of the comparator structure is that the determination threshold can be accurately set, but the static bias current in the comparator structure will cause static bias power consumption.
  • the existing glitch signal detection circuit has disadvantages such as low response speed, low sensitivity, and low portability.
  • a glitch signal detection circuit, security chip and electronic equipment are provided, which can not only detect glitches on power supply voltage or ground voltage, but also have low power consumption, small area, high speed, high sensitivity, and portability. Strong sex and other advantages.
  • a glitch signal detection circuit including:
  • a voltage sampling module includes:
  • a first metal oxide semiconductor MOS tube and a capacitor for sampling the power supply voltage the gate terminal of the first MOS tube is connected to the capacitor, the source terminal of the first MOS tube is connected to the ground voltage, and the power supply voltage
  • the voltage value of the drain terminal of the first MOS tube is the ground voltage
  • the voltage value of the gate terminal of the first MOS tube is passed through the capacitor Sampled power supply voltage
  • the glitch signal detection circuit also includes a second MOS tube and a signal output module;
  • One end of the second MOS tube is connected to the gate terminal of the first MOS tube, the other end of the second MOS tube is connected to the power supply voltage, and the drain terminal of the second MOS tube is connected to the first MOS tube.
  • the drain terminal of a MOS tube is connected to the gate terminal of the first MOS tube, the other end of the second MOS tube is connected to the power supply voltage, and the drain terminal of the second MOS tube is connected to the first MOS tube.
  • the signal output module is used to generate and output a target signal according to the change of the voltage value of the drain terminal of the second MOS tube, and the target signal is used to indicate whether a glitch signal occurs in the power supply voltage or the ground voltage.
  • the voltage value of the drain terminal of the first MOS tube is the ground voltage
  • the voltage value of the gate terminal of the first MOS tube is the power supply voltage sampled by the capacitor.
  • the signal output module can generate and output the target signal according to the change in the voltage value of the drain terminal of the second MOS transistor.
  • Sampling the power supply voltage based on the capacitor is different from the traditional resistance-capacitance sampling structure. Specifically, sampling the power supply voltage based on the capacitor does not require the use of resistors, thereby reducing the area and hardware overhead of the glitch signal detection circuit; in addition, the working state of the second MOS transistor is controlled by the glitch signal, and then the signal The output module detects the voltage of the drain terminal of the second MOS tube, which can effectively improve the detection speed and sensitivity; the quiescent current of the glitch signal detection circuit is only the leakage current of the device used, and there is no static bias current, which can reduce the glitch signal detection circuit Static power consumption; secondly, the above-mentioned glitch signal detection circuit can be compatible with digital (Complementary Metal-Oxide-Semiconductor Transistor, CMOS) technology, which can enhance the portability of the glitch signal detection circuit. In short, the above-mentioned glitch signal detection circuit can not only detect glitches on the power supply voltage or ground voltage, but also has the advantages of
  • the gate terminal of the second MOS transistor is connected to the gate of the first MOS transistor, and the source terminal of the second MOS transistor is connected to the power supply voltage.
  • the signal output module For generating and outputting a first signal, the first signal is used to indicate that there is no glitch signal on the power supply voltage or the ground voltage; a glitch signal appears on the power supply voltage and/or a glitch signal appears on the ground voltage
  • the signal output module is used to generate and output a second signal, and the second signal is used to indicate a glitch in the power supply voltage or the ground voltage signal.
  • the signal output module can generate and output the target signal according to the change of the voltage value of the drain terminal of the second MOS transistor.
  • the glitch signal detection circuit further includes:
  • a third MOS tube the gate terminal of the third MOS tube is connected to the power supply voltage, the source terminal of the third MOS tube is connected to the gate terminal of the second MOS tube, and the drain terminal of the third MOS tube The terminal is connected to the drain terminal of the first MOS tube.
  • the signal output module is used to generate and output a third signal, the third signal is used to indicate that the power supply voltage or the ground voltage does not have a glitch signal; a glitch signal in the negative direction appears on the power supply voltage And/or when a glitch signal in the positive direction appears on the ground voltage, the voltage value of the drain terminal of the third MOS tube changes, the signal output module is used to generate and output a fourth signal, and the fourth signal The signal is used to indicate that a glitch signal occurs in the power supply voltage or the ground voltage.
  • the source terminal voltage of the third MOS tube remains unchanged, and the gate terminal voltage will decrease, which will cause the drain terminal voltage to increase.
  • the gate terminal voltage of the third MOS tube remains unchanged, and the voltage at the source terminal increases due to capacitive coupling, which in turn causes the drain terminal voltage of the second MOS tube to rise , which is equivalent to controlling the working state of the third MOS transistor through a glitch signal, so that the signal output module can generate and output the target signal according to the change in the voltage value of the drain terminal of the third MOS transistor.
  • the source terminal of the second MOS tube is connected to the gate of the first MOS tube, and the gate terminal of the second MOS tube is connected to the power supply voltage.
  • the glitch signal detection circuit includes:
  • one end of the capacitor connected to the gate terminal of the first MOS transistor is connected to the power supply voltage through the fourth MOS transistor, and the other end of the capacitor is connected to the ground voltage.
  • the capacitor By controlling the on and off of the fourth MOS tube, the capacitor can be used to sample the power supply voltage.
  • the glitch signal detection circuit further includes:
  • a fifth MOS transistor the drain terminal of the first MOS transistor is connected to the ground voltage through the fifth MOS transistor.
  • the voltage at the drain terminal of the first MOS transistor can be reset to prevent the drain terminal of the first MOS transistor from being in a high-impedance floating state, thereby ensuring the glitch The performance of the signal detection circuit.
  • the glitch signal detection circuit further includes:
  • the first inverter, the drain terminal of the first MOS tube is connected to the gate terminal of the first MOS tube through the first inverter.
  • the glitch signal detection circuit can detect in real time whether the power supply voltage or the ground voltage is attacked by a glitch.
  • the first MOS transistor, the second MOS transistor and the inverter can be used to form a latch. Detecting burrs on the power supply voltage or ground voltage based on the latch is different from the traditional resistance capacitance sampling structure and the comparator structure.
  • the latch does not need to use a resistor, so it can reduce the area of the glitch signal detection circuit and the hardware overhead; the positive feedback characteristic of the latch can improve the detection speed of the glitch signal detection circuit; compared to the resistance-capacitance structure, the lock The negative resistance hysteresis of the register can detect glitch signals of lower amplitude, thereby improving the sensitivity of the glitch signal detection circuit; the quiescent current of the latch is only the leakage current of the device used, and there is no static bias current, which can reduce the glitch signal The static power consumption of the detection circuit; the latch can be compatible with digital (Complementary Metal-Oxide-Semiconductor Transistor, CMOS) technology, which can enhance the portability of the glitch signal detection circuit.
  • CMOS Complementary Metal-Oxide-Semiconductor Transistor
  • the inverter includes:
  • the sixth MOS transistor and the seventh MOS transistor the source terminal of the sixth MOS transistor is connected to the power supply voltage, the gate terminal of the sixth MOS transistor is connected to the gate terminal of the seventh MOS transistor, and the The drain terminal of the six MOS tube is connected to the drain terminal of the seventh MOS tube, the source terminal of the seventh MOS tube is connected to the ground voltage, and the drain terminal of the sixth MOS tube is connected to the first MOS tube.
  • the gate end of the tube is connected to the drain terminal of the seventh MOS tube.
  • the signal output module is a D flip-flop.
  • the glitch signal detection circuit further includes:
  • Threshold judgment module the drain terminal of the second MOS tube is connected to the signal output module through the threshold judgment module, and the threshold judgment module is used to amplify the signal output by the drain terminal of the second MOS tube, and The amplified signal is sent to the signal output module.
  • threshold judgment module Through the threshold judgment module, glitch of lower amplitude can be detected, which further improves the sensitivity of the glitch signal detection circuit.
  • the threshold judgment module includes:
  • the source terminal of the eighth MOS transistor is connected to the power supply voltage
  • the gate terminal of the eighth MOS transistor is connected to the gate of the tenth MOS transistor
  • the drain terminal of the eighth MOS tube is connected to the drain terminal of the tenth MOS tube
  • the source terminal of the tenth MOS tube is connected to the ground voltage
  • the source terminal of the ninth MOS tube is connected to
  • the gate terminal of the ninth MOS tube is connected to the gate terminal of the eleventh MOS tube
  • the drain terminal of the ninth MOS tube is connected to the drain terminal of the eleventh MOS tube.
  • the source terminal of the eleventh MOS tube is connected to the ground voltage
  • the drain terminal of the eighth MOS tube is connected to the gate terminal of the ninth MOS tube
  • the gate terminal of the eighth MOS tube is connected to the first MOS tube.
  • the drain terminal of the second MOS tube, and the drain terminal of the ninth MOS tube is connected to the signal output module.
  • the aspect ratio of the eighth MOS transistor is less than a first preset threshold
  • the aspect ratio of the ninth MOS transistor is greater than a second preset threshold
  • the width of the tenth MOS transistor is The aspect ratio is greater than a third preset threshold
  • the aspect ratio of the eleventh MOS transistor is less than a fourth preset threshold, wherein the first preset threshold is less than or equal to the third preset threshold, and the first The second preset threshold is greater than or equal to the fourth preset threshold.
  • the eighth MOS transistor and the tenth MOS transistor form a second inverter
  • the ninth MOS transistor and the eleventh MOS transistor form a third inverter
  • the switching threshold of the second inverter is smaller than the switching threshold of the third inverter.
  • the flip threshold of the second inverter is 0.3
  • the flip threshold of the third inverter is 0.8, that is, the sensitivity of the glitch signal detection circuit 100 is improved by reducing the flip threshold of the second inverter.
  • the stability of the glitch signal detection circuit 100 is ensured.
  • a security chip including:
  • an electronic device including:
  • the processor is configured to receive a target signal sent by the security chip, and the target signal is used to indicate whether a glitch signal occurs in the power supply voltage or the ground voltage.
  • 1 to 3 are schematic circuit diagrams of the glitch signal detection circuit of the embodiment of the present application.
  • FIG. 4 is a schematic diagram of the voltage state of the gate terminal N of the first MOS tube and the voltage state of the drain terminal M of the first MOS tube in the voltage sampling module of the embodiment of the present application.
  • Fig. 5 is a schematic circuit diagram of a threshold judgment module of an embodiment of the present application.
  • a power glitch attack quickly changes the power supply voltage (or ground voltage) input to the chip, which affects certain circuit units of the chip; then causes one or more circuit units to enter an error state, causing the chip's processor to jump The wrong operation is performed or based on the error state; and the hidden security information in the chip is exposed.
  • FIG. 1 is a schematic circuit diagram of a glitch signal detection circuit 100 according to an embodiment of the present application.
  • the glitch signal detection circuit 100 may include a voltage sampling module 210.
  • the voltage sampling module 130 may include a first Metal-Oxide Semiconductor (MOS) tube 113 and a capacitor 160 for sampling the power supply voltage.
  • MOS Metal-Oxide Semiconductor
  • the gate terminal of the first MOS tube 113 is connected to the capacitor 160
  • the voltage value of the drain terminal of the first MOS transistor is equal to
  • the voltage value of the gate terminal of the first MOS tube is the power supply voltage sampled by the capacitor.
  • the power supply voltage sampled by the capacitor 160 that is not affected by the glitch signal can be obtained.
  • the voltage of the drain of the first MOS transistor 113 can be reset to prevent the drain terminal of the first MOS transistor 113 from being in a high-impedance floating state, so that no glitch signal appears on the power supply voltage and the When there is no glitch signal on the ground voltage, the voltage value of the drain terminal of the first MOS tube is the ground voltage, and the voltage value of the gate terminal of the first MOS tube is the power supply voltage sampled by the capacitor.
  • the glitch signal may be a regular or irregular pulse signal or spike signal in the input waveform of the circuit.
  • the voltage value when a positive glitch signal appears on the power supply voltage is equal to the voltage value when no glitch signal appears on the power supply voltage plus the voltage value of the glitch signal.
  • the voltage value when a negative and positive glitch signal appears on the power supply voltage is equal to the voltage value when there is no glitch signal on the power supply voltage minus the voltage value of the glitch signal.
  • a glitch signal in the positive direction and a glitch signal in the negative direction can also appear on the ground voltage.
  • the unstable power supply voltage it can also be considered as the voltage after a glitch signal is superimposed on the stable power supply voltage.
  • the unstable ground voltage it can also be considered as the voltage after a glitch signal is superimposed on the stable ground voltage.
  • the glitch signal detection circuit 100 may further include a positive direction glitch detection module 220.
  • the positive direction glitch detection module 220 may include a second MOS tube 111 and a signal output module 130.
  • the second MOS One end of the tube 111 is connected to the gate terminal of the first MOS tube 113, the other end of the second MOS tube 111 is connected to the power supply voltage, and the drain terminal of the second MOS tube 111 is connected to the first The drain terminal of the MOS tube 113;
  • the signal output module 130 is used to generate and output a target signal according to the change in the voltage value of the drain terminal of the second MOS tube 111, and the target signal is used to indicate the power supply voltage or the Whether there is a glitch signal in the ground voltage.
  • the signal output module 130 is used to generate and output The first signal, the first signal is used to indicate that there is no glitch signal on the power supply voltage or the ground voltage; when a glitch signal appears on the power supply voltage and/or a glitch signal appears on the ground voltage, the first signal
  • the signal output module 130 is used to generate and output a second signal, and the second signal is used to indicate that a glitch signal occurs in the power supply voltage or the ground voltage.
  • the voltage of the drain of the second MOS transistor 111 can be reset, avoiding the second
  • the drain terminal of the MOS transistor 111 is in a high-impedance floating state, so that when no glitch signal appears on the power supply voltage and no glitch signal appears on the ground voltage, the voltage value of the drain terminal of the second MOS transistor 111 is as follows The ground voltage.
  • the sampling of the power supply voltage based on the capacitor is different from the traditional resistance-capacitance sampling structure. Specifically, the sampling of the power supply voltage based on the capacitor does not require the use of resistors, so the area and hardware overhead of the glitch signal detection circuit can be reduced; in addition, the glitch signal Controlling the working state of the second MOS tube 111, and then detecting the voltage of the drain terminal of the second MOS tube 111 through the signal output module 130, can effectively improve the detection speed and sensitivity; secondly, the static state of the glitch signal detection circuit 100 The current is only the leakage current of the device used, and there is no static bias current, which can reduce the static power consumption of the glitch signal detection circuit; the glitch signal detection circuit 100 is also compatible with digital (Complementary Metal-Oxide-Semiconductor Transistor, CMOS) technology, and can Enhance the portability of the glitch signal detection circuit.
  • CMOS Complementary Metal-Oxide-Semiconductor Transistor
  • the glitch signal detection circuit 100 can not only detect glitches on the power supply voltage or ground voltage, but also has the advantages of low power consumption, small area, high speed, high sensitivity, and strong portability. advantage.
  • the gate terminal of the second MOS transistor 111 is connected to the gate of the first MOS transistor 113, and the source terminal of the second MOS transistor 111 is connected to the power supply voltage.
  • the voltage value of the drain terminal of the second MOS tube 111 will not change, and the signal
  • the output module 130 is used to generate and output a first signal, the first signal is used to indicate that there is no glitch signal in the power supply voltage or the ground voltage; a glitch signal in the positive direction appears on the power supply voltage and/or the
  • the signal output module 130 is used to generate and output a second signal. It indicates that a glitch signal appears on the power supply voltage or the ground voltage.
  • the source terminal voltage of the second MOS tube 111 increases, and the gate terminal voltage remains unchanged, which in turn causes the drain terminal voltage to increase; the local voltage appears negative.
  • the voltage at the gate terminal of the second MOS tube 111 will drop, and the voltage at the source terminal will remain unchanged, which in turn causes the voltage at the drain terminal of the second MOS tube 111 to rise.
  • the drain terminal of the second MOS transistor 111 will cause the voltage of the gate terminal of the second MOS transistor 111 to drop, and the gate of the second MOS transistor 111 The voltage at the source terminal of the second MOS transistor 111 remains unchanged, which in turn causes the voltage at the drain terminal of the second MOS transistor 111 to rise.
  • the signal output module 130 can generate and output the target signal according to the change of the voltage value of the drain terminal of the second MOS transistor 111.
  • the glitch signal detection circuit 100 can detect whether a glitch signal in a positive direction appears on the power supply voltage and whether a glitch signal in a negative direction appears on the ground voltage through the second MOS tube 111.
  • the glitch signal detection circuit 100 may also include a negative direction glitch detection module 230.
  • the positive direction glitch detection module 230 may be a third MOS tube 170, and the gate terminal of the third MOS tube 170 Connected to the power supply voltage, the source terminal of the third MOS transistor 170 is connected to the gate terminal of the second MOS transistor 111, and the drain terminal of the third MOS transistor 170 is connected to the gate terminal of the first MOS transistor 113 Drain end.
  • the voltage value of the drain terminal of the third MOS transistor 170 does not change, and the signal
  • the output module 130 is used to generate and output a third signal, the third signal is used to indicate that the power supply voltage or the ground voltage does not have a glitch signal; the power supply voltage has a negative glitch signal and/or
  • the signal output module 130 is used to generate and output a fourth signal. It indicates that a glitch signal appears on the power supply voltage or the ground voltage.
  • the source terminal voltage of the third MOS transistor 170 remains unchanged, and the gate terminal voltage will decrease, which will cause the drain terminal voltage to increase.
  • the gate terminal voltage of the third MOS transistor 170 remains unchanged, and the voltage at the source terminal increases due to capacitive coupling, which in turn causes the voltage at the drain terminal of the second MOS transistor Will rise, which is equivalent to controlling the working state of the third MOS transistor 170 through a glitch signal, whereby the signal output module 130 can generate and output the target according to the change in the voltage value of the drain terminal of the third MOS transistor 170 signal.
  • the glitch signal detection circuit 100 can detect whether a glitch signal in a positive direction appears on the power supply voltage and whether a glitch signal in a negative direction appears on the ground voltage through the second MOS tube 111.
  • the third MOS transistor 170 can be used to detect whether a negative glitch signal appears on the power supply voltage and whether a positive glitch signal appears on the ground voltage.
  • the second MOS transistor 111 and the third MOS transistor 170 can be used to form a bidirectional detection module 240, which can realize bidirectional glitch detection.
  • the detection of the positive direction burr signal and the negative direction burr signal on the power supply voltage can be realized, and for example, the detection of the positive direction burr signal and the negative direction burr signal on the ground voltage can be realized.
  • the glitch signal detection circuit may also only include the voltage sampling module 210, the third MOS transistor 170, and the signal output module 130, that is, it is only used to detect whether the power supply voltage is A glitch signal in a negative direction appears and whether a glitch signal in a positive direction appears on the ground voltage.
  • FIG. 2 is a schematic diagram of a modified circuit of the glitch signal detection circuit 100 shown in FIG. 1 in an embodiment of the present invention.
  • the glitch signal detection circuit 100 may further include a fourth MOS transistor 140, and one end of the capacitor 160 connected to the gate terminal of the first MOS transistor 113 is connected to the fourth MOS transistor 140 through the fourth MOS transistor 140.
  • the other end of the capacitor 160 is connected to the ground voltage.
  • the capacitor can be used to sample the power supply voltage. For example, when the gate terminal of the fourth MOS transistor 140 receives a low-level control signal, the fourth MOS transistor 140 is turned on, and the capacitor 160 is charged by the power supply voltage until the voltage of the capacitor 160 is reached. When charged to the power supply voltage, the gate terminal of the fourth MOS transistor 140 receives a high-level control signal, and the fourth MOS transistor 140 is turned off, so that the voltage of the capacitor 160 is maintained at the power supply voltage.
  • the glitch signal detection circuit 100 may further include a fifth MOS transistor 150, and the drain terminal of the first MOS transistor 113 is connected to the ground voltage through the fifth MOS transistor 150.
  • the voltage at the drain terminal of the first MOS transistor 113 can be reset to prevent the drain terminal of the first MOS transistor 113 from being in a high-impedance floating state, thereby ensuring The performance of the glitch signal detection circuit 100.
  • control signal used to control the fourth MOS transistor 140 and the control signal used to control the fifth MOS transistor 150 may be a set of reverse signals.
  • the gate terminal of the fifth MOS transistor 150 is used to receive the first signal R
  • the gate terminal of the fourth MOS transistor 140 is used to receive the reverse signal R_b of the first signal R.
  • the fourth MOS transistor 140 and the fifth MOS transistor 150 are both turned on, that is, the power supply voltage charges the capacitor 160 through the fourth MOS transistor 140, so that The first voltage of the gate terminal N of the first MOS transistor 113 is "1", and the drain terminal M of the first MOS transistor 113 is connected to the ground through the fifth MOS transistor 150, so that the first MOS transistor The second voltage of the drain terminal M of 113 is "0". Then, when the first signal R is at a low level, the fourth MOS transistor 140 and the fifth MOS transistor 150 are both disconnected, so that the first voltage of the gate terminal N of the first MOS transistor 113 is maintained at "1". ", the second voltage of the drain terminal M of the first MOS transistor 113 is maintained at "0".
  • the gate terminal N of the first MOS transistor 113 can be pulled up to VDD through the control signal, and the drain terminal M of the first MOS transistor 113 can be pulled down to GND.
  • the glitch signal detection circuit 100 may also include a first inverter 211, and the drain terminal of the first MOS transistor 113 is connected to the first MOS transistor through the first inverter 211. 113's gate end.
  • the first inverter 211 By controlling the first inverter 211, it can be ensured that the voltage of the drain terminal of the first MOS transistor 113 is at "0", and thus the performance of the glitch signal detection circuit 100 can be ensured. Even if the voltage of the drain terminal of the first MOS transistor 113 increases, the first inverter 211 can ensure that the voltage of the drain terminal of the first MOS transistor 113 is restored to "0". Moreover, through the first inverter, leakage of the capacitor 160 can also be avoided, thereby ensuring that the voltage value of the capacitor remains at the power supply voltage. Therefore, the glitch signal detection circuit can detect in real time whether the power supply voltage or the ground voltage is attacked by a glitch.
  • FIG. 3 is another schematic diagram of the circuit structure described in FIG. 2.
  • the first inverter may include a sixth MOS transistor 112 and a seventh MOS transistor 114, the source terminal of the sixth MOS transistor 112 is connected to the power supply voltage, and the sixth MOS transistor 112
  • the gate terminal of the seventh MOS transistor 114 is connected to the gate terminal of the seventh MOS transistor 114
  • the drain terminal of the sixth MOS transistor 112 is connected to the drain terminal of the seventh MOS transistor 114
  • the source terminal of the seventh MOS transistor 114 is connected To the ground voltage
  • the drain terminal of the sixth MOS transistor 112 is connected to the gate terminal of the first MOS transistor 113.
  • the glitch signal detection circuit 100 may include a latch 100, and the latch 110 may include a second MOS tube 111, a first MOS tube 113, a sixth MOS tube 112, and a seventh MOS tube 114;
  • the source terminal of the second MOS transistor 111 is connected to the power supply voltage
  • the gate terminal of the second MOS transistor 111 is connected to the gate terminal of the sixth MOS transistor 112
  • the drain terminal of the second MOS transistor 111 Connected to the drain terminal of the sixth MOS transistor 112
  • the source terminal of the sixth MOS transistor 112 is connected to the ground voltage
  • the source terminal of the first MOS transistor 113 is connected to the power supply voltage
  • the The gate terminal of a MOS tube 113 is connected to the gate terminal of the seventh MOS tube 114
  • the drain terminal of the first MOS tube 113 is connected to the drain terminal of the seventh MOS tube 114
  • the seventh MOS tube 114 The source terminal of the second MOS tube 111 is connected to the ground voltage, the gate terminal
  • Detecting burrs on the power supply voltage or ground voltage based on the latch is different from the traditional resistance capacitance sampling structure and the comparator structure.
  • the latch does not need to use a resistor, so it can reduce the area of the glitch signal detection circuit and the hardware overhead; the positive feedback characteristic of the latch can improve the detection speed of the glitch signal detection circuit; compared to the resistance-capacitance structure, the lock
  • the negative resistance hysteresis of the register can detect glitch signals of lower amplitude, thereby improving the sensitivity of the glitch signal detection circuit;
  • the quiescent current of the latch is only the leakage current of the device used, and there is no static bias current, which can reduce the glitch signal
  • the latch can be compatible with digital (Complementary Metal-Oxide-Semiconductor Transistor, CMOS) technology, which can enhance the portability of the glitch signal detection circuit.
  • CMOS Complementary Metal-Oxide-Semiconductor Transistor
  • the signal output module 130 may be a D flip-flop.
  • the reset (RESET) terminal B of the D flip-flop is connected to the reset signal W, for example, the reset signal W may be the above-mentioned first signal R; the D terminal of the D flip-flop is connected to VDD; The detection terminal A of the D flip-flop is connected to the drain terminal of the first MOS transistor 113) for receiving a detection signal, and the output terminal Q of the D flip-flop outputs a target signal (ie, an early warning (ALARM) signal).
  • the signal output module 130 may also be other devices, such as a comparator.
  • the glitch signal detection circuit 100 may further include a threshold judgment module 120, the drain terminal of the first MOS transistor 113 is connected to the signal output module 130 through the threshold judgment module 120, and the threshold The judgment module 120 is used to amplify the signal output by the drain terminal of the first MOS transistor 113 and send the amplified signal to the signal output module 130.
  • glitch with a lower amplitude can be detected, which further improves the sensitivity of the glitch signal detection circuit 100.
  • the gate terminal N of the first MOS transistor 113 is pulled high by the fourth MOS transistor 140 to maintain the "1" state through the action of the latch 110.
  • the drain terminal M of the first MOS transistor 113 is pulled down by the fifth MOS transistor 150 to maintain a "0" state.
  • the static power consumption of the glitch signal detection circuit 100 is only the leakage power consumption of the used device.
  • the target signal output by the signal output module 130 is used to indicate that glitch appears on the power supply voltage or the ground voltage.
  • the voltage at the gate terminal of the second MOS transistor 111 (that is, the gate terminal N of the first MOS transistor 113) remains unchanged, and the voltage at the source terminal increases; the glitch amplitude is greater than that of the second MOS transistor 111
  • the second MOS transistor 111 is turned on and charges the drain terminal M of the first MOS transistor 113 to increase its voltage; the latch 110 triggers the gate terminal of the first MOS transistor 113
  • the voltage of N drops to "0"
  • the voltage of the drain terminal M of the first MOS transistor 113 further rises to "1".
  • the detection signal output by the threshold judgment module 120 is pulled up to "1".
  • the signal output module 130 After the signal output module 130 detects the rising edge of the Detection signal, it updates the output state of the D flip-flop, that is, the target signal output by the signal output module 130 becomes "1", which is used to indicate the presence of glitch on the power supply voltage or the ground voltage. .
  • the target signal output by the signal output module 130 is used to indicate that glitch appears on the power supply voltage or the ground voltage.
  • the voltage at the gate terminal of the second MOS transistor 111 (that is, the gate terminal N of the first MOS transistor 113) remains unchanged, and the voltage at the source terminal increases, and the glitch amplitude is close to that of the second MOS transistor 111.
  • VDD charges the drain terminal M of the first MOS transistor 113 through the leakage voltage of the second MOS transistor 111, causing its voltage to rise;
  • the gate terminal N of the first MOS tube 113 discharges, causing its voltage to drop; because the voltage of the drain terminal M of the first MOS tube 113 rises, the current passing through the second MOS tube 111 decreases, that is, the voltage of the first MOS tube 113 The voltage at the drain terminal M does not rise any further, and the voltage at the gate terminal N of the first MOS transistor 113 does not fall any further; through the latch 110, the drain terminal M of the first MOS transistor 113 passes a period of time Will drop to “0”, and the voltage of the gate terminal N of the first MOS transistor 113 will rise to “1” after a period of time.
  • the states of N and voltage and M point voltage can be as shown in Figure 4; the threshold judgment module 120 can detect that the voltage of the drain terminal M of the first MOS transistor 113 is in a state of maintaining a rising state for a period of time, and then The status is judged as "1", that is, the output (Detection) signal is pulled up to "1".
  • the threshold judgment module 120 detects that the maximum value of the difference V(M)-GND between the voltage V(M) of the drain terminal M of the first MOS transistor 113 and the ground voltage GND is greater than or equal to the threshold judgment module 120
  • the threshold judgment module 120 has a signal inversion (from 0 to 1).
  • the D flip-flop detects the rising edge of the Detection signal and updates the output state of the D flip-flop.
  • the target signal output by the signal output module 130 becomes "1", which is used to indicate that glitch appears on the power supply voltage or the ground voltage.
  • FIG. 3 is only an example of this application, and should not be understood as a limitation to this application.
  • the threshold determination module 120 detects the voltage of the gate terminal N of the first MOS transistor 113 When in a state of maintaining a downward rise for a period of time, this state is judged as "1", that is, the output (Detection) signal is pulled up to "1".
  • the threshold judgment module 120 detects that the difference between the voltage V(N) of the gate terminal N of the first MOS transistor 113 and the ground voltage GND is less than or equal to the power supply voltage VDD and the second threshold voltage of the threshold judgment module 120 When the difference of Vthp is VDD-
  • the D flip-flop in the signal output module 130 detects the falling edge of the Detection signal and updates the output state of the D flip-flop.
  • the target signal output by the signal output module 130 becomes "1", which is used to indicate the presence of glitch on the power supply voltage or the ground voltage. .
  • the target signal output by the signal output module 130 is used to indicate that glitch appears on the power supply voltage or the ground voltage.
  • capacitive coupling causes the voltage at the gate terminal of the second MOS tube 111 to drop, and the voltage at the source terminal remains unchanged.
  • the glitch amplitude is greater than the threshold voltage of the second MOS tube 111
  • the second MOS tube 111 Turn on and charge the drain terminal M of the first MOS transistor 113 to increase its voltage;
  • the latch 110 causes the voltage of the gate terminal N of the first MOS transistor 113 to drop to "0", and the first MOS transistor 113
  • the voltage of the drain terminal M of 113 further rises to "1".
  • the detection signal output by the threshold judgment module 120 is pulled up to "1"
  • the signal output module 130 updates the output state of the D flip-flop after detecting the rising edge of the Detection signal, that is, the output state of the signal output module 130
  • the target signal becomes "1", which is used to indicate glitch on the power supply voltage or ground voltage.
  • the target signal output by the signal output module 130 is used to indicate that glitch appears on the power supply voltage or the ground voltage.
  • capacitive coupling causes the voltage at the gate terminal of the second MOS transistor 111 to drop, while the voltage at the source terminal remains unchanged; when the glitch amplitude is close to the threshold voltage of the second MOS transistor 111, the power supply voltage passes through the
  • the second MOS tube 111 charges the drain terminal M of the first MOS tube 113 to increase its voltage; the seventh MOS tube 114 discharges the gate terminal N of the first MOS tube 113 to decrease its voltage
  • the rise of the voltage at the drain terminal M of the first MOS tube 113 causes the current through the second MOS tube 111 to drop, that is, the voltage at the drain terminal M of the first MOS tube 113 no longer rises, the first MOS tube 113
  • the voltage at the gate terminal N of the tube 113 does not drop further; through the function of the latch 110, the drain terminal M of the first MOS tube 113 will drop to "0" after a period of time, and the first MOS tube 113 The voltage at the gate terminal N will rise to "1" after a period
  • the states of the N and voltage and the voltage at point M can be as shown in FIG. 4; the threshold judgment module 120 can detect the leakage of the first MOS transistor 113
  • the voltage of the terminal M is in a state of maintaining a rising state for a period of time, and this state is judged as "1", that is, the output (Detection) signal is pulled up to "1".
  • the D flip-flop detects the rising edge of the Detection signal and updates the output state of the D flip-flop.
  • the target signal output by the signal output module 130 becomes "1", which is used to indicate that glitch appears on the power supply voltage or the ground voltage.
  • the target signal output by the signal output module 130 is used to indicate that glitch appears on the power supply voltage or the ground voltage.
  • the voltage of the source terminal of the third MOS transistor 170 (that is, the gate terminal N of the first MOS transistor 113) remains unchanged, and the power supply voltage of the gate terminal drops, and the glitch amplitude is greater than that of the third MOS transistor 170
  • the third MOS transistor 170 is turned on; the capacitor 160 charges the drain terminal M of the first MOS transistor 113 through the third MOS transistor 170 to increase its voltage, and the first MOS transistor 113
  • the voltage of the gate terminal N of the first MOS transistor 113 drops after the charge distribution; the latch 110 further reduces the voltage of the gate terminal N of the first MOS transistor 113 to "0", and the voltage of the drain terminal M of the first MOS transistor 113 further rises To "1"; at this time, the output (Detection) signal of the threshold judgment module 120 is pulled up to "1", and the signal output module 130 updates the D flip-flop output state after detecting the rising edge of the Detection signal, That is, the target signal output by the signal output module 130 becomes "1
  • the target signal output by the signal output module 130 is used to indicate that glitch appears on the power supply voltage or the ground voltage.
  • the voltage at the source terminal of the third MOS transistor 170 (ie the gate terminal N of the first MOS transistor 113) remains unchanged, and the power supply voltage at the gate terminal drops, and the glitch amplitude is close to that of the third MOS transistor 170
  • the capacitor 160 charges the drain terminal M of the first MOS transistor 113 through the third MOS transistor 170 to increase its voltage, and at the same time, the gate terminal N of the first MOS transistor 113 has its voltage
  • the voltage at the drain terminal M of the first MOS tube 113 rises, so that the current passing through the third MOS tube 170 decreases, that is, the voltage at the drain terminal M of the first MOS tube 113 does not rise any further, the first The voltage of the gate terminal N of the MOS tube 113 does not drop any further; through the latch 110, the drain terminal M of the first MOS tube 113 will drop to "0" after a period of time, and the first MOS tube The voltage of the gate terminal N of the 113 will rise to “1”
  • the states of the voltage at the N and the voltage and the voltage at the M point can be as shown in FIG. 4; the threshold judgment module 120 can detect the first MOS transistor 113
  • the voltage of the drain terminal M is in a state of maintaining an increase for a period of time, and this state is determined as "1", that is, the output (Detection) signal is pulled up to "1".
  • the D flip-flop detects the rising edge of the Detection signal and updates the output state of the D flip-flop.
  • the target signal output by the signal output module 130 becomes "1", which is used to indicate that glitch appears on the power supply voltage or the ground voltage.
  • the target signal output by the signal output module 130 is used to indicate that glitch appears on the power supply voltage or the ground voltage.
  • the voltage at the source terminal of the third MOS transistor 170 increases, the voltage at the gate terminal remains unchanged, and the glitch amplitude is greater than that of the third MOS transistor 170
  • the third MOS transistor 170 is turned on, and the capacitor 160 charges the drain terminal M of the first MOS transistor 113 through the third MOS transistor 170 to increase its voltage, and the first MOS transistor 113
  • the voltage of the gate terminal N of the first MOS transistor 113 drops after the charge distribution; the latch 110 further reduces the voltage of the gate terminal N of the first MOS transistor 113 to "0", and the voltage of the drain terminal M of the first MOS transistor 113 further rises To "1"; at this time, the output (Detection) signal of the threshold judgment module 120 is pulled up to "1", and the signal output module 130 updates the D flip-flop output state after detecting the rising edge of the Detection signal, That is, the target signal output by the signal output module 130
  • the target signal output by the signal output module 130 is used to indicate that glitch appears on the power supply voltage or the ground voltage.
  • the voltage at the gate terminal N of the first MOS transistor 113 increases, and the voltage at the gate terminal remains unchanged.
  • the glitch amplitude is close to the threshold voltage of the third MOS transistor 170, the capacitor 160 passes through The third MOS transistor 170 charges the M point to increase the voltage at the M point, and at the same time, the voltage at the N point decreases through the charge distribution.
  • the third MOS transistor 170 When the glitch amplitude is close to the threshold voltage of the third MOS transistor 170, the third MOS transistor 170 is turned on; the capacitor 160 charges the drain terminal M of the first MOS transistor 113 through the third MOS transistor 170 to make Its voltage rises, and at the same time the voltage of the gate terminal N of the first MOS tube 113 drops after charge distribution; the rise of the voltage of the drain terminal M of the first MOS tube 113 causes the current passing through the third MOS tube 170 to fall, that is The voltage of the drain terminal M of the first MOS tube 113 does not rise any further, and the voltage of the gate terminal N of the first MOS tube 113 does not fall further; through the latch 110, the voltage of the first MOS tube 113 The drain terminal M will drop to "0" after a period of time, and the voltage of the gate terminal N of the first MOS transistor 113 will rise to "1" after a period of time.
  • the state of the voltage at N and the voltage at point M It can be as shown in Fig. 4; the threshold judgment module 120 can detect that the voltage of the drain terminal M of the first MOS transistor 113 is in a state of maintaining a rising state for a period of time, and judge this state as "1", that is, output (Detection ) The signal is pulled up to "1".
  • the D flip-flop detects the rising edge of the Detection signal and updates the output state of the D flip-flop.
  • the target signal output by the signal output module 130 becomes "1", which is used to indicate glitch on the power supply voltage or the ground voltage.
  • FIG. 5 is a schematic circuit diagram of the threshold judgment module 120 according to an embodiment of the present application.
  • the threshold judgment module 120 may include an eighth MOS transistor 1211, a ninth MOS transistor 1221, and a tenth MOS transistor 1212.
  • the source terminal of the eighth MOS transistor 1211 is connected to the power supply voltage.
  • the gate terminal of the eighth MOS tube 1211 is connected to the gate terminal of the tenth MOS tube 1212
  • the drain terminal of the eighth MOS tube 1211 is connected to the drain terminal of the tenth MOS tube 1212
  • the tenth MOS tube The source terminal of 1212 is connected to the ground voltage
  • the source terminal of the ninth MOS transistor 1221 is connected to the power supply voltage
  • the gate terminal of the ninth MOS transistor 1221 is connected to the gate of the eleventh MOS transistor 1222.
  • the drain terminal of the ninth MOS tube 1221 is connected to the drain terminal of the eleventh MOS tube 1222, the source terminal of the eleventh MOS tube 1222 is connected to the ground voltage, and the eighth MOS tube
  • the drain terminal of 1211 is connected to the gate terminal of the ninth MOS tube 1221, the gate terminal of the eighth MOS tube 1211 is connected to the drain terminal of the second MOS tube 111, and the drain terminal of the ninth MOS tube 1221 is connected to To the signal output module 130.
  • the aspect ratio of the eighth MOS tube 1211 is less than a first preset threshold
  • the aspect ratio of the ninth MOS tube 1221 is greater than a second preset threshold
  • the aspect ratio of the tenth MOS tube 1212 is The ratio is greater than the third preset threshold
  • the aspect ratio of the eleventh MOS transistor 1222 is less than the fourth preset threshold
  • the first preset threshold is less than or equal to the third preset threshold
  • the first The second preset threshold is greater than or equal to the fourth preset threshold, so as to improve the amplification effect of the threshold judgment module 120, and thereby improve the sensitivity of the glitch signal detection circuit 100.
  • the eighth MOS tube 1211 and the tenth MOS tube 1212 form a second inverter
  • the ninth MOS tube 1221 and the eleventh MOS tube 1222 form a third inverter
  • the The switching threshold of the second inverter is smaller than the switching threshold of the third inverter.
  • the flip threshold of the second inverter is 0.3
  • the flip threshold of the third inverter is 0.8, that is, the sensitivity of the glitch signal detection circuit 100 is improved by reducing the flip threshold of the second inverter.
  • the stability of the glitch signal detection circuit 100 is ensured.
  • This application also provides an electronic device, which may include the glitch signal detection circuit described above.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • NMOSFET N-type MOS tube
  • PMOSFET P-type MOS tube
  • the gate terminal of the "N-type” MOS tube (the MOS tube with the substrate PN junction pointing inward or the MOS tube with current flowing out) is connected to the high voltage It is usually turned on and turned off when connected to a low level; when the gate terminal of a "P-type” MOS tube (a MOS tube with a PN junction pointing outward or a MOS tube through which current flows) is turned off when it is connected to a high level, it is turned on when connected to a low level.
  • FIGS. 1 to 5 are only examples of the present application, and should not be construed as limiting the present application.
  • the drain terminal of the sixth MOS transistor 112 may also be connected to the signal output module 130.
  • circuits, branches, and modules may be implemented in other ways.
  • the branches described above are illustrative.
  • the division of the modules is only a logical function division, and there may be other divisions in actual implementation.
  • multiple modules can be combined or integrated into one branch. Road, or some features can be ignored or not implemented.
  • the integrated module is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • the technical solution of this application essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in each embodiment of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program code .

Abstract

A glitch signal detection circuit, a security chip, and an electronic device. The glitch signal detection circuit (100) comprises a voltage sampling module (210). The voltage sampling module (210) comprises a first metal oxide semiconductor (MOS) transistor (113) and a capacitor (160) for sampling a power supply voltage. The gate end of the first MOS transistor (113) is connected to the capacitor (160), and the source end of the first MOS transistor (113) is connected to a ground voltage. When no glitch signal appears on the power supply voltage and no glitch signal appears on the ground voltage, the voltage value of the drain end of the first MOS transistor (113) is the ground voltage, and the voltage value of the gate end of the first MOS transistor (113) is the power supply voltage sampled by the capacitor (160). The glitch signal detection circuit further comprises a second MOS transistor (111) and a signal output module (130). One end of the second MOS transistor (111) is connected to the gate end of the first MOS transistor (113), the other end of the second MOS transistor (111) is connected to the power supply voltage, and the drain end of the second MOS transistor (111) is connected to the drain end of the first MOS transistor (113). The glitch signal detection circuit (100) can detect the glitch on the power supply voltage or the ground voltage, and the glitch signal detection circuit (100) has the advantages of low power consumption, small area, high speed, high sensitivity, and strong portability.

Description

毛刺信号检测电路、安全芯片和电子设备Glitch signal detection circuit, security chip and electronic equipment 技术领域Technical field
本申请实施例涉及电子领域，并且更具体地，涉及毛刺信号检测电路、安全芯片和电子设备。The embodiments of the present application relate to the field of electronics, and more specifically, to glitch signal detection circuits, security chips, and electronic devices.
背景技术Background technique
安全芯片可以用于实现用户身份识别与关键数据存储等功能，其被广泛应用于金融领域，是攻击者的重点攻击对象。Security chips can be used to realize functions such as user identification and key data storage. They are widely used in the financial field and are a key target of attackers.
攻击者可以通过故障攻击(如毛刺(power glitch)攻击)，使芯片工作在非正常状态下，从而导致芯片发生错误行为；此时，攻击者可以利用故障分析技术轻易获取安全芯片中的机密数据。Attackers can use fault attacks (such as power glitch attacks) to make the chip work in an abnormal state, resulting in chip misbehavior; at this time, the attacker can easily obtain the confidential data in the security chip by using fault analysis technology .
通常情况下，可以通过毛刺信号检测电路检测电源电压(或地电压)上的毛刺，并及时给出报警信号，从而增加芯片系统的鲁棒性和安全性。具体而言，毛刺信号检测电路需要包括电阻电容(RC)采样结构和比较器结构。RC采样结构利用低通滤波器采样电源电压(或地电压)，比较器结构通过电阻分压设置判定阈值，并通过比较采样的电源电压(或地电压)与判定阈值确定是否触发报警信号。RC采样结构的优点在于可以检测毫微秒(ns)级的毛刺，但RC较大的RC采样结构一般要求较大的面积开销。比较器结构的优点在于可以精确设置判定阈值，但比较器结构中的静态偏置电流会使其存在静态偏置功耗。此外，现有的毛刺信号检测电路存在反应速度低、灵敏度低以及可移植性低等缺点。Under normal circumstances, the glitch on the power supply voltage (or ground voltage) can be detected by the glitch signal detection circuit, and an alarm signal can be given in time, thereby increasing the robustness and safety of the chip system. Specifically, the glitch signal detection circuit needs to include a resistance-capacitance (RC) sampling structure and a comparator structure. The RC sampling structure uses a low-pass filter to sample the power supply voltage (or ground voltage), and the comparator structure sets a judgment threshold through a resistor divider, and compares the sampled power supply voltage (or ground voltage) with the judgment threshold to determine whether to trigger an alarm signal. The advantage of the RC sampling structure is that it can detect nanosecond (ns)-level glitches, but the RC sampling structure with a larger RC generally requires a larger area overhead. The advantage of the comparator structure is that the determination threshold can be accurately set, but the static bias current in the comparator structure will cause static bias power consumption. In addition, the existing glitch signal detection circuit has disadvantages such as low response speed, low sensitivity, and low portability.
发明内容Summary of the invention
提供了一种毛刺信号检测电路、安全芯片和电子设备，不仅能够检测电源电压或地电压上的毛刺，并且所述毛刺信号检测电路具有功耗低、面积小、速度快、灵敏度高以及可移植性强等优点。A glitch signal detection circuit, security chip and electronic equipment are provided, which can not only detect glitches on power supply voltage or ground voltage, but also have low power consumption, small area, high speed, high sensitivity, and portability. Strong sex and other advantages.
第一方面，提供了一种毛刺信号检测电路，包括：In the first aspect, a glitch signal detection circuit is provided, including:
电压采样模块，所述电压采样模块包括：A voltage sampling module, the voltage sampling module includes:
第一金属氧化物半导体MOS管和用于采样电源电压的电容器，所述第一MOS管的栅端连接至所述电容器，所述第一MOS管的源端连接至地电 压，所述电源电压上未出现毛刺信号且所述地电压上未出现毛刺信号时，所述第一MOS管的漏端的电压值为所述地电压，所述第一MOS管的栅端的电压值为通过所述电容器采样的电源电压；A first metal oxide semiconductor MOS tube and a capacitor for sampling the power supply voltage, the gate terminal of the first MOS tube is connected to the capacitor, the source terminal of the first MOS tube is connected to the ground voltage, and the power supply voltage When there is no glitch signal on the ground voltage and no glitch signal appears on the ground voltage, the voltage value of the drain terminal of the first MOS tube is the ground voltage, and the voltage value of the gate terminal of the first MOS tube is passed through the capacitor Sampled power supply voltage;
所述毛刺信号检测电路还包括第二MOS管和信号输出模块；The glitch signal detection circuit also includes a second MOS tube and a signal output module;
所述第二MOS管的一端连接至所述第一MOS管的栅端，所述第二MOS管的另一端连接至所述电源电压，所述第二MOS管的漏端连接至所述第一MOS管的漏端；One end of the second MOS tube is connected to the gate terminal of the first MOS tube, the other end of the second MOS tube is connected to the power supply voltage, and the drain terminal of the second MOS tube is connected to the first MOS tube. The drain terminal of a MOS tube;
所述信号输出模块用于根据所述第二MOS管的漏端的电压值的变化生成并输出目标信号，所述目标信号用于指示所述电源电压或所述地电压是否出现毛刺信号。The signal output module is used to generate and output a target signal according to the change of the voltage value of the drain terminal of the second MOS tube, and the target signal is used to indicate whether a glitch signal occurs in the power supply voltage or the ground voltage.
通过将所述第一MOS管的栅端连接至所述电容器，可以采获取所述电容器采样的不受毛刺信号影响的电源电压，通过将所述第一MOS管连接至地电压，可以对所述第一MOS管的漏极的电压进行重置，避免所述第一MOS管漏端处于高阻悬空状态，由此可以使得所述电源电压上未出现毛刺信号且所述地电压上未出现毛刺信号时，所述第一MOS管的漏端的电压值为所述地电压，所述第一MOS管的栅端的电压值为通过所述电容器采样的电源电压。进一步地，通过将所述第二MOS管的一端连接至所述第一MOS管的栅端，将所述第二MOS管的另一端连接至所述电源电压，相当于通过毛刺信号控制所述第二MOS管的工作状态，由此所述信号输出模块可以根据所述第二MOS管的漏端的电压值的变化生成并输出所述目标信号。By connecting the gate terminal of the first MOS transistor to the capacitor, the power supply voltage sampled by the capacitor that is not affected by the glitch signal can be obtained. By connecting the first MOS transistor to the ground voltage, the The voltage of the drain of the first MOS tube is reset to prevent the drain terminal of the first MOS tube from being in a high-impedance floating state, so that no glitch signal appears on the power supply voltage and no glitch signal appears on the ground voltage. In the case of a glitch signal, the voltage value of the drain terminal of the first MOS tube is the ground voltage, and the voltage value of the gate terminal of the first MOS tube is the power supply voltage sampled by the capacitor. Further, by connecting one end of the second MOS transistor to the gate terminal of the first MOS transistor, and connecting the other end of the second MOS transistor to the power supply voltage, it is equivalent to controlling the The operating state of the second MOS transistor, whereby the signal output module can generate and output the target signal according to the change in the voltage value of the drain terminal of the second MOS transistor.
基于所述电容器采样电源电压区别于传统的电阻电容采样结构。具体而言，基于所述电容器采样电源电压不需要使用电阻，因此能够降低毛刺信号检测电路的面积以及硬件开销；此外，通过毛刺信号控制所述第二MOS管的工作状态，进而通过所述信号输出模块检测所述第二MOS管的漏端的电压，能够有效提高检测速度和灵敏度；毛刺信号检测电路的静态电流仅为所用器件的漏电电流，无静态偏置电流，能够降低毛刺信号检测电路的静态功耗；其次，上述毛刺信号检测电路可以兼容数字(Complementary Metal-Oxide-Semiconductor Transistor，CMOS)工艺，能够增强毛刺信号检测电路的可移植性。简而言之，上述毛刺信号检测电路不仅能够检测电源电压或地电压上的毛刺，并且所述毛刺信号检测电路具有功耗低、面积小、速度快、灵敏度高以及可移植性强等优点。Sampling the power supply voltage based on the capacitor is different from the traditional resistance-capacitance sampling structure. Specifically, sampling the power supply voltage based on the capacitor does not require the use of resistors, thereby reducing the area and hardware overhead of the glitch signal detection circuit; in addition, the working state of the second MOS transistor is controlled by the glitch signal, and then the signal The output module detects the voltage of the drain terminal of the second MOS tube, which can effectively improve the detection speed and sensitivity; the quiescent current of the glitch signal detection circuit is only the leakage current of the device used, and there is no static bias current, which can reduce the glitch signal detection circuit Static power consumption; secondly, the above-mentioned glitch signal detection circuit can be compatible with digital (Complementary Metal-Oxide-Semiconductor Transistor, CMOS) technology, which can enhance the portability of the glitch signal detection circuit. In short, the above-mentioned glitch signal detection circuit can not only detect glitches on the power supply voltage or ground voltage, but also has the advantages of low power consumption, small area, high speed, high sensitivity, and strong portability.
在一些可能实现的方式中，所述第二MOS管的栅端连接至所述第一MOS管的栅极，所述第二MOS管的源端连接至所述电源电压。In some possible implementation manners, the gate terminal of the second MOS transistor is connected to the gate of the first MOS transistor, and the source terminal of the second MOS transistor is connected to the power supply voltage.
在一些可能实现的方式中，所述电源电压上未出现毛刺信号且所述地电压上未出现毛刺信号时，所述第二MOS管的漏端的电压值的未发生变化，所述信号输出模块用于生成并输出第一信号，所述第一信号用于指示所述电源电压或所述地电压未出现毛刺信号；所述电源电压上出现毛刺信号和/或所述地电压上出现毛刺信号时，所述第二MOS管的漏端的电压值的发生变化，所述信号输出模块用于生成并输出第二信号，所述第二信号用于指示所述电源电压或所述地电压出现毛刺信号。In some possible implementation manners, when no glitch signal appears on the power supply voltage and no glitch signal appears on the ground voltage, the voltage value of the drain terminal of the second MOS tube does not change, and the signal output module For generating and outputting a first signal, the first signal is used to indicate that there is no glitch signal on the power supply voltage or the ground voltage; a glitch signal appears on the power supply voltage and/or a glitch signal appears on the ground voltage When the voltage value of the drain terminal of the second MOS tube changes, the signal output module is used to generate and output a second signal, and the second signal is used to indicate a glitch in the power supply voltage or the ground voltage signal.
例如，当所述电源电压上出现正方向的毛刺信号时，所述第二MOS管的源端电压增大，且栅端电压不变，进而导致漏端的电压增大；当地电压上出现负方向的毛刺信号时，由于电容耦合，所述第二MOS管的栅端的电压会下降，且源端的电压保持不变，进而导致所述第二MOS管的漏端的电压会上升。相当于通过毛刺信号控制所述第二MOS管的工作状态，即所述信号输出模块可以根据所述第二MOS管的漏端的电压值的变化生成并输出所述目标信号。For example, when a glitch signal in the positive direction appears on the power supply voltage, the source terminal voltage of the second MOS tube increases, and the gate terminal voltage remains unchanged, resulting in an increase in the drain terminal voltage; a negative direction appears on the local voltage Due to the capacitive coupling, the voltage at the gate terminal of the second MOS tube will drop, and the voltage at the source terminal will remain unchanged, which will cause the voltage at the drain terminal of the second MOS tube to rise. It is equivalent to controlling the working state of the second MOS transistor through a glitch signal, that is, the signal output module can generate and output the target signal according to the change of the voltage value of the drain terminal of the second MOS transistor.
在一些可能实现的方式中，所述毛刺信号检测电路还包括：In some possible implementation manners, the glitch signal detection circuit further includes:
第三MOS管，所述第三MOS管的栅端连接至所述电源电压，所述第三MOS管的源端连接至所述第二MOS管的栅端，所述第三MOS管的漏端连接至所述第一MOS管的漏端。A third MOS tube, the gate terminal of the third MOS tube is connected to the power supply voltage, the source terminal of the third MOS tube is connected to the gate terminal of the second MOS tube, and the drain terminal of the third MOS tube The terminal is connected to the drain terminal of the first MOS tube.
在一些可能实现的方式中，所述电源电压上未出现负方向上的毛刺信号且所述地电压上未出现正方向上的毛刺信号时，所述第三MOS管的漏端的电压值的未发生变化，所述信号输出模块用于生成并输出第三信号，所述第三信号用于指示所述电源电压或所述地电压未出现毛刺信号；所述电源电压上出现负方向上的毛刺信号和/或所述地电压上出现正方向上的的毛刺信号时，所述第三MOS管的漏端的电压值的发生变化，所述信号输出模块用于生成并输出第四信号，所述第四信号用于指示所述电源电压或所述地电压出现毛刺信号。In some possible implementation manners, when no glitch signal in the negative direction appears on the power supply voltage and no glitch signal in the positive direction appears on the ground voltage, the voltage value of the drain terminal of the third MOS tube does not occur. Change, the signal output module is used to generate and output a third signal, the third signal is used to indicate that the power supply voltage or the ground voltage does not have a glitch signal; a glitch signal in the negative direction appears on the power supply voltage And/or when a glitch signal in the positive direction appears on the ground voltage, the voltage value of the drain terminal of the third MOS tube changes, the signal output module is used to generate and output a fourth signal, and the fourth signal The signal is used to indicate that a glitch signal occurs in the power supply voltage or the ground voltage.
例如，当所述电源电压上出现负方向的毛刺信号时，所述第三MOS管的源端电压保持不变，且由于栅端电压会减小，进而导致其漏端电压增大，当所述地电压上出现正方向的毛刺信号时，所述第三MOS管的栅端电压保 持不变，由于电容耦合其源端的电压增大，进而导致所述第二MOS管的漏端的电压会上升，相当于通过毛刺信号控制所述第三MOS管的工作状态，由此所述信号输出模块可以根据所述第三MOS管的漏端的电压值的变化生成并输出所述目标信号。For example, when a glitch signal in the negative direction appears on the power supply voltage, the source terminal voltage of the third MOS tube remains unchanged, and the gate terminal voltage will decrease, which will cause the drain terminal voltage to increase. When a glitch signal in the positive direction appears on the ground voltage, the gate terminal voltage of the third MOS tube remains unchanged, and the voltage at the source terminal increases due to capacitive coupling, which in turn causes the drain terminal voltage of the second MOS tube to rise , Which is equivalent to controlling the working state of the third MOS transistor through a glitch signal, so that the signal output module can generate and output the target signal according to the change in the voltage value of the drain terminal of the third MOS transistor.
在一些可能实现的方式中，所述第二MOS管的源端连接至所述第一MOS管的栅极，所述第二MOS管的栅端连接至所述电源电压。In some possible implementation manners, the source terminal of the second MOS tube is connected to the gate of the first MOS tube, and the gate terminal of the second MOS tube is connected to the power supply voltage.
在一些可能实现的方式中，所述毛刺信号检测电路包括：In some possible implementation manners, the glitch signal detection circuit includes:
第四MOS管，所述电容器的与所述第一MOS管的栅端相连的一端通过所述第四MOS管连接至所述电源电压，所述电容器的另一端连接至所述地电压。In the fourth MOS transistor, one end of the capacitor connected to the gate terminal of the first MOS transistor is connected to the power supply voltage through the fourth MOS transistor, and the other end of the capacitor is connected to the ground voltage.
通过控制所述第四MOS管的导通和关断，可以实现利用所述电容器采样所述电源电压。By controlling the on and off of the fourth MOS tube, the capacitor can be used to sample the power supply voltage.
在一些可能实现的方式中，所述毛刺信号检测电路还包括：In some possible implementation manners, the glitch signal detection circuit further includes:
第五MOS管，所述第一MOS管的漏端通过所述第五MOS管连接至所述地电压。A fifth MOS transistor, the drain terminal of the first MOS transistor is connected to the ground voltage through the fifth MOS transistor.
通过控制所述第五MOS管的导通和关断，可以将所述第一MOS管漏端的电压进行重置，避免所述第一MOS管漏端处于高阻悬空状态，进而保证所述毛刺信号检测电路的性能。By controlling the turn-on and turn-off of the fifth MOS transistor, the voltage at the drain terminal of the first MOS transistor can be reset to prevent the drain terminal of the first MOS transistor from being in a high-impedance floating state, thereby ensuring the glitch The performance of the signal detection circuit.
在一些可能实现的方式中，所述毛刺信号检测电路还包括：In some possible implementation manners, the glitch signal detection circuit further includes:
第一反相器，所述第一MOS管的漏端通过所述第一反相器连接至所述第一MOS管的栅端。The first inverter, the drain terminal of the first MOS tube is connected to the gate terminal of the first MOS tube through the first inverter.
通过控制所述第一反相器，可以保证所述第一MOS管的漏端的电压处于“0”，进而保证所述毛刺信号检测电路的性能。而且，通过所述第一反相器，也可以避免所述电容器出现漏电，进而保证所述电容器的电压值保持在电源电压。由此，所述毛刺信号检测电路可以实时检测所述电源电压或地电压是否收到毛刺攻击。By controlling the first inverter, it can be ensured that the voltage of the drain terminal of the first MOS tube is at "0", thereby ensuring the performance of the glitch signal detection circuit. Moreover, through the first inverter, leakage of the capacitor can also be avoided, thereby ensuring that the voltage value of the capacitor remains at the power supply voltage. Therefore, the glitch signal detection circuit can detect in real time whether the power supply voltage or the ground voltage is attacked by a glitch.
此外，所述第一MOS管、所述第二MOS管和所述反相器可以用于形成锁存器。基于锁存器检测电源电压或地电压上的毛刺，区别于传统的电阻电容采样结构和比较器结构。具体而言，锁存器不需要使用电阻，因此能够降低毛刺信号检测电路的面积以及硬件开销；锁存器的正反馈特性可以提高毛刺信号检测电路的检测速度；相比于电阻电容结构，锁存器的负阻迟滞特 性，可以检测更低幅度的glitch信号，进而提升毛刺信号检测电路的灵敏度；锁存器的静态电流仅为所用器件的漏电电流，无静态偏置电流，能够降低毛刺信号检测电路的静态功耗；锁存器可以兼容数字(Complementary Metal-Oxide-Semiconductor Transistor，CMOS)工艺，能够增强毛刺信号检测电路的可移植性。简而言之，所述毛刺信号检测电路不仅能够检测电源电压或地电压上的毛刺，并且所述毛刺信号检测电路具有功耗低、面积小、速度快、灵敏度高以及可移植性强等优点。In addition, the first MOS transistor, the second MOS transistor and the inverter can be used to form a latch. Detecting burrs on the power supply voltage or ground voltage based on the latch is different from the traditional resistance capacitance sampling structure and the comparator structure. Specifically, the latch does not need to use a resistor, so it can reduce the area of the glitch signal detection circuit and the hardware overhead; the positive feedback characteristic of the latch can improve the detection speed of the glitch signal detection circuit; compared to the resistance-capacitance structure, the lock The negative resistance hysteresis of the register can detect glitch signals of lower amplitude, thereby improving the sensitivity of the glitch signal detection circuit; the quiescent current of the latch is only the leakage current of the device used, and there is no static bias current, which can reduce the glitch signal The static power consumption of the detection circuit; the latch can be compatible with digital (Complementary Metal-Oxide-Semiconductor Transistor, CMOS) technology, which can enhance the portability of the glitch signal detection circuit. In short, the glitch signal detection circuit can not only detect glitches on the power supply voltage or ground voltage, but also has the advantages of low power consumption, small area, fast speed, high sensitivity, and strong portability. .
在一些可能实现的方式中，所述反相器包括：In some possible implementation manners, the inverter includes:
第六MOS管和第七MOS管，所述第六MOS管的源端连接至所述电源电压，所述第六MOS管的栅端连接至所述第七MOS管的栅端，所述第六MOS管的漏端连接至所述第七MOS管的漏端，所述第七MOS管的源端连接至所述地电压，所述第六MOS管的漏端连接至所述第一MOS管的栅端。The sixth MOS transistor and the seventh MOS transistor, the source terminal of the sixth MOS transistor is connected to the power supply voltage, the gate terminal of the sixth MOS transistor is connected to the gate terminal of the seventh MOS transistor, and the The drain terminal of the six MOS tube is connected to the drain terminal of the seventh MOS tube, the source terminal of the seventh MOS tube is connected to the ground voltage, and the drain terminal of the sixth MOS tube is connected to the first MOS tube. The gate end of the tube.
在一些可能实现的方式中，所述信号输出模块为D触发器。In some possible implementation manners, the signal output module is a D flip-flop.
在一些可能实现的方式中，所述毛刺信号检测电路还包括：In some possible implementation manners, the glitch signal detection circuit further includes:
阈值判决模块，所述第二MOS管的漏端通过所述阈值判决模块连接至所述信号输出模块，所述阈值判决模块用于放大所述第二MOS管的漏端输出的信号，并将放大后的信号发送至所述信号输出模块。Threshold judgment module, the drain terminal of the second MOS tube is connected to the signal output module through the threshold judgment module, and the threshold judgment module is used to amplify the signal output by the drain terminal of the second MOS tube, and The amplified signal is sent to the signal output module.
通过所述阈值判决模块，可以检测更低幅度的glitch，进一步提升所述毛刺信号检测电路的灵敏度。Through the threshold judgment module, glitch of lower amplitude can be detected, which further improves the sensitivity of the glitch signal detection circuit.
在一些可能实现的方式中，所述阈值判决模块包括：In some possible implementation manners, the threshold judgment module includes:
第八MOS管、第九MOS管和第十MOS管，所述第八MOS管的源端连接至所述电源电压，所述第八MOS管的栅端连接至所述第十MOS管的栅端，所述第八MOS管的漏端连接至所述第十MOS管的漏端，所述第十MOS管的源端连接至所述地电压，所述第九MOS管的源端连接至所述电源电压，所述第九MOS管的栅端连接至所述第十一MOS管的栅端，所述第九MOS管的漏端连接至所述第十一MOS管的漏端，所述第十一MOS管的源端连接至所述地电压，所述第八MOS管的漏端连接所述第九MOS管的栅端，所述第八MOS管的栅端连接至所述第二MOS管的漏端，所述第九MOS管的漏端连接至所述信号输出模块。Eighth, ninth, and tenth MOS transistors, the source terminal of the eighth MOS transistor is connected to the power supply voltage, and the gate terminal of the eighth MOS transistor is connected to the gate of the tenth MOS transistor The drain terminal of the eighth MOS tube is connected to the drain terminal of the tenth MOS tube, the source terminal of the tenth MOS tube is connected to the ground voltage, and the source terminal of the ninth MOS tube is connected to For the power supply voltage, the gate terminal of the ninth MOS tube is connected to the gate terminal of the eleventh MOS tube, and the drain terminal of the ninth MOS tube is connected to the drain terminal of the eleventh MOS tube. The source terminal of the eleventh MOS tube is connected to the ground voltage, the drain terminal of the eighth MOS tube is connected to the gate terminal of the ninth MOS tube, and the gate terminal of the eighth MOS tube is connected to the first MOS tube. The drain terminal of the second MOS tube, and the drain terminal of the ninth MOS tube is connected to the signal output module.
在一些可能实现的方式中，所述第八MOS管的宽长比小于第一预设阈值，所述第九MOS管的宽长比大于第二预设阈值，所述第十MOS管的宽 长比大于第三预设阈值，所述第十一MOS管的宽长比小于第四预设阈值，其中，所述第一预设阈值小于或等于所述第三预设阈值，所述第二预设阈值大于或等于所述第四预设阈值。In some possible implementation manners, the aspect ratio of the eighth MOS transistor is less than a first preset threshold, the aspect ratio of the ninth MOS transistor is greater than a second preset threshold, and the width of the tenth MOS transistor is The aspect ratio is greater than a third preset threshold, and the aspect ratio of the eleventh MOS transistor is less than a fourth preset threshold, wherein the first preset threshold is less than or equal to the third preset threshold, and the first The second preset threshold is greater than or equal to the fourth preset threshold.
在一些可能实现的方式中，所述第八MOS管和所述第十MOS管形成第二反相器，所述第九MOS管和所述第十一MOS管形成第三反相器，所述第二反相器的翻转阈值小于所述第三反相器的翻转阈值。例如所述第二反相器的翻转阈值为0.3，所述第三反相器的翻转阈值为0.8，即通过降低所述第二反相器的翻转阈值提升所述毛刺信号检测电路100的灵敏度，进一步地，通过增大所述第三反相器的翻转阈值，保证所述毛刺信号检测电路100的稳定性。In some possible implementation manners, the eighth MOS transistor and the tenth MOS transistor form a second inverter, the ninth MOS transistor and the eleventh MOS transistor form a third inverter, so The switching threshold of the second inverter is smaller than the switching threshold of the third inverter. For example, the flip threshold of the second inverter is 0.3, and the flip threshold of the third inverter is 0.8, that is, the sensitivity of the glitch signal detection circuit 100 is improved by reducing the flip threshold of the second inverter. Further, by increasing the flip threshold of the third inverter, the stability of the glitch signal detection circuit 100 is ensured.
第二方面，提供了一种安全芯片，包括：In the second aspect, a security chip is provided, including:
第一方面或第一方面中任一可能实现的方式中所述的毛刺信号检测电路。The glitch signal detection circuit described in the first aspect or any possible implementation manner in the first aspect.
第三方面，提供了一种电子设备，包括：In a third aspect, an electronic device is provided, including:
第二方面所述的安全芯片芯片；和The security chip of the second aspect; and
处理器，所述处理器用于接收所述安全芯片发送的目标信号，所述目标信号用于指示电源电压或地电压是否出现毛刺信号。The processor is configured to receive a target signal sent by the security chip, and the target signal is used to indicate whether a glitch signal occurs in the power supply voltage or the ground voltage.
附图说明Description of the drawings
图1至图3是本申请实施例的毛刺信号检测电路的示意性结电路图。1 to 3 are schematic circuit diagrams of the glitch signal detection circuit of the embodiment of the present application.
图4是本申请实施例的电压采样模块中的第一MOS管的栅端N电压状态和第一MOS管的漏端M的电压状态的示意图。4 is a schematic diagram of the voltage state of the gate terminal N of the first MOS tube and the voltage state of the drain terminal M of the first MOS tube in the voltage sampling module of the embodiment of the present application.
图5是本申请实施例的阈值判决模块的示意性电路图。Fig. 5 is a schematic circuit diagram of a threshold judgment module of an embodiment of the present application.
具体实施方式Detailed ways
下面将结合附图，对本申请实施例中的技术方案进行描述。The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings.
电源毛刺(power glitch)攻击通过快速改变输入到芯片的电源电压(或地电压)，使得芯片的某些电路单元受到影响；继而引起一个或者多个电路单元进入错误状态，使得芯片的处理器跳过或者根据错误状态实施错误操作；进而暴露了芯片内隐藏的安全信息。A power glitch attack quickly changes the power supply voltage (or ground voltage) input to the chip, which affects certain circuit units of the chip; then causes one or more circuit units to enter an error state, causing the chip's processor to jump The wrong operation is performed or based on the error state; and the hidden security information in the chip is exposed.
图1是本申请实施例的毛刺信号检测电路100的示意性电路图。FIG. 1 is a schematic circuit diagram of a glitch signal detection circuit 100 according to an embodiment of the present application.
请参见图1，所述毛刺信号检测电路100可以包括电压采样模块210。所述电压采样模块130可以包括第一金属氧化物半导体(Metal-Oxide Semiconductor，MOS)管113和用于采样电源电压的电容器160，所述第一MOS管113的栅端连接至所述电容器160，所述第一MOS管113的源端连接至地电压，所述电源电压上未出现毛刺信号且所述地电压上未出现毛刺信号时，所述第一MOS管的漏端的电压值为所述地电压，所述第一MOS管的栅端的电压值为通过所述电容器采样的电源电压。Referring to FIG. 1, the glitch signal detection circuit 100 may include a voltage sampling module 210. The voltage sampling module 130 may include a first Metal-Oxide Semiconductor (MOS) tube 113 and a capacitor 160 for sampling the power supply voltage. The gate terminal of the first MOS tube 113 is connected to the capacitor 160 When the source terminal of the first MOS transistor 113 is connected to the ground voltage, when no glitch signal appears on the power supply voltage and no glitch signal appears on the ground voltage, the voltage value of the drain terminal of the first MOS transistor is equal to For the ground voltage, the voltage value of the gate terminal of the first MOS tube is the power supply voltage sampled by the capacitor.
即所述第一MOS管113的栅端通过连接至所述电容器160，可以获取所述电容器160采样的不受毛刺信号影响的电源电压，通过将所述第一MOS管113连接至地电压，可以对所述第一MOS管113的漏极的电压进行重置，避免所述第一MOS管113漏端处于高阻悬空状态，由此可以使得所述电源电压上未出现毛刺信号且所述地电压上未出现毛刺信号时，所述第一MOS管的漏端的电压值为所述地电压，所述第一MOS管的栅端的电压值为通过所述电容器采样的电源电压。That is, by connecting the gate terminal of the first MOS transistor 113 to the capacitor 160, the power supply voltage sampled by the capacitor 160 that is not affected by the glitch signal can be obtained. By connecting the first MOS transistor 113 to the ground voltage, The voltage of the drain of the first MOS transistor 113 can be reset to prevent the drain terminal of the first MOS transistor 113 from being in a high-impedance floating state, so that no glitch signal appears on the power supply voltage and the When there is no glitch signal on the ground voltage, the voltage value of the drain terminal of the first MOS tube is the ground voltage, and the voltage value of the gate terminal of the first MOS tube is the power supply voltage sampled by the capacitor.
其中，毛刺信号可以是电路的输入波形中包括有规律或没有规律的脉冲信号或尖峰信号。例如，电源电压上出现正方向的毛刺信号时的电压值等于所述电源电压上未出现毛刺信号时的电压值加所述毛刺信号的电压值。又例如，电源电压上出现负正方向的毛刺信号时的电压值等于所述电源电压上未出现毛刺信号时的电压值减去所述毛刺信号的电压值。Among them, the glitch signal may be a regular or irregular pulse signal or spike signal in the input waveform of the circuit. For example, the voltage value when a positive glitch signal appears on the power supply voltage is equal to the voltage value when no glitch signal appears on the power supply voltage plus the voltage value of the glitch signal. For another example, the voltage value when a negative and positive glitch signal appears on the power supply voltage is equal to the voltage value when there is no glitch signal on the power supply voltage minus the voltage value of the glitch signal.
类似地，地电压上也可以出现正方向的毛刺信号和负方向的毛刺信号。Similarly, a glitch signal in the positive direction and a glitch signal in the negative direction can also appear on the ground voltage.
针对不稳定的电源电压，其也可以认为是稳定的电源电压上叠加有一个毛刺信号后的电压。针对不稳定的地电压，其也可以认为是在稳定的地电压上叠加一个毛刺信号后的电压。Regarding the unstable power supply voltage, it can also be considered as the voltage after a glitch signal is superimposed on the stable power supply voltage. Regarding the unstable ground voltage, it can also be considered as the voltage after a glitch signal is superimposed on the stable ground voltage.
请继续参见图1，所述毛刺信号检测电路100还可以包括正方向毛刺检测模块220，例如所述正方向毛刺检测模块220可以包括第二MOS管111和信号输出模块130，所述第二MOS管111的一端连接至所述第一MOS管113的栅端，所述第二MOS管111的另一端连接至所述电源电压，所述第二MOS管111的漏端连接至所述第一MOS管113的漏端；所述信号输出模块130用于根据所述第二MOS管111的漏端的电压值的变化生成并输出目标信号，所述目标信号用于指示所述电源电压或所述地电压是否出现毛刺信号。Please continue to refer to FIG. 1, the glitch signal detection circuit 100 may further include a positive direction glitch detection module 220. For example, the positive direction glitch detection module 220 may include a second MOS tube 111 and a signal output module 130. The second MOS One end of the tube 111 is connected to the gate terminal of the first MOS tube 113, the other end of the second MOS tube 111 is connected to the power supply voltage, and the drain terminal of the second MOS tube 111 is connected to the first The drain terminal of the MOS tube 113; the signal output module 130 is used to generate and output a target signal according to the change in the voltage value of the drain terminal of the second MOS tube 111, and the target signal is used to indicate the power supply voltage or the Whether there is a glitch signal in the ground voltage.
通过将所述第二MOS管111的一端连接至所述第一MOS管113的栅端，将所述第二MOS管111的另一端连接至所述电源电压，相当于通过毛刺信号控制所述第二MOS管111的工作状态，由此所述信号输出模块130可以根据所述第二MOS管111的漏端的电压值的变化生成并输出所述目标信号。By connecting one end of the second MOS transistor 111 to the gate terminal of the first MOS transistor 113, and connecting the other end of the second MOS transistor 111 to the power supply voltage, it is equivalent to controlling the The operating state of the second MOS transistor 111, whereby the signal output module 130 can generate and output the target signal according to the change in the voltage value of the drain terminal of the second MOS transistor 111.
例如，所述电源电压上未出现毛刺信号且所述地电压上未出现毛刺信号时，所述第二MOS管111的漏端的电压值未发生变化，所述信号输出模块130用于生成并输出第一信号，所述第一信号用于指示所述电源电压或所述地电压未出现毛刺信号；所述电源电压上出现毛刺信号和/或所述地电压上出现毛刺信号时，所述第二MOS管111的漏端的电压值的发生变化，所述信号输出模块130用于生成并输出第二信号，所述第二信号用于指示所述电源电压或所述地电压出现毛刺信号。For example, when no glitch signal appears on the power supply voltage and no glitch signal appears on the ground voltage, the voltage value of the drain terminal of the second MOS tube 111 does not change, and the signal output module 130 is used to generate and output The first signal, the first signal is used to indicate that there is no glitch signal on the power supply voltage or the ground voltage; when a glitch signal appears on the power supply voltage and/or a glitch signal appears on the ground voltage, the first signal When the voltage value of the drain terminal of the second MOS tube 111 changes, the signal output module 130 is used to generate and output a second signal, and the second signal is used to indicate that a glitch signal occurs in the power supply voltage or the ground voltage.
此外，通过将所述第二MOS管111的漏端连接至所述第一MOS管113的漏端，可以对所述第二MOS管111的漏极的电压进行重置，避免所述第二MOS管111漏端处于高阻悬空状态，由此可以使得所述电源电压上未出现毛刺信号且所述地电压上未出现毛刺信号时，所述第二MOS管111的漏端的电压值为所述地电压。In addition, by connecting the drain terminal of the second MOS transistor 111 to the drain terminal of the first MOS transistor 113, the voltage of the drain of the second MOS transistor 111 can be reset, avoiding the second The drain terminal of the MOS transistor 111 is in a high-impedance floating state, so that when no glitch signal appears on the power supply voltage and no glitch signal appears on the ground voltage, the voltage value of the drain terminal of the second MOS transistor 111 is as follows The ground voltage.
基于所述电容器采样电源电压区别于传统的电阻电容采样结构，具体而言，基于所述电容器采样电源电压不需要使用电阻，因此能够降低毛刺信号检测电路的面积以及硬件开销；此外，通过毛刺信号控制所述第二MOS管111的工作状态，进而通过所述信号输出模块130检测所述第二MOS管111的漏端的电压，能够有效提高检测速度和灵敏度；其次，毛刺信号检测电路100的静态电流仅为所用器件的漏电电流，无静态偏置电流，能够降低毛刺信号检测电路的静态功耗；上述毛刺信号检测电路100还可以兼容数字(Complementary Metal-Oxide-Semiconductor Transistor，CMOS)工艺，能够增强毛刺信号检测电路的可移植性。The sampling of the power supply voltage based on the capacitor is different from the traditional resistance-capacitance sampling structure. Specifically, the sampling of the power supply voltage based on the capacitor does not require the use of resistors, so the area and hardware overhead of the glitch signal detection circuit can be reduced; in addition, the glitch signal Controlling the working state of the second MOS tube 111, and then detecting the voltage of the drain terminal of the second MOS tube 111 through the signal output module 130, can effectively improve the detection speed and sensitivity; secondly, the static state of the glitch signal detection circuit 100 The current is only the leakage current of the device used, and there is no static bias current, which can reduce the static power consumption of the glitch signal detection circuit; the glitch signal detection circuit 100 is also compatible with digital (Complementary Metal-Oxide-Semiconductor Transistor, CMOS) technology, and can Enhance the portability of the glitch signal detection circuit.
简而言之，所述毛刺信号检测电路100不仅能够检测电源电压或地电压上的毛刺，并且所述毛刺信号检测电路具有功耗低、面积小、速度快、灵敏度高以及可移植性强等优点。In short, the glitch signal detection circuit 100 can not only detect glitches on the power supply voltage or ground voltage, but also has the advantages of low power consumption, small area, high speed, high sensitivity, and strong portability. advantage.
请继续参见图1，所述第二MOS管111的栅端连接至所述第一MOS管113的栅极，所述第二MOS管111的源端连接至所述电源电压。Please continue to refer to FIG. 1, the gate terminal of the second MOS transistor 111 is connected to the gate of the first MOS transistor 113, and the source terminal of the second MOS transistor 111 is connected to the power supply voltage.
例如，所述电源电压上未出现正方向上的毛刺信号且所述地电压上未出 现负方向上的毛刺信号时，所述第二MOS管111的漏端的电压值不会发生变化，所述信号输出模块130用于生成并输出第一信号，所述第一信号用于指示所述电源电压或所述地电压未出现毛刺信号；所述电源电压上出现正方向上的毛刺信号和/或所述地电压上出现负方向上的的毛刺信号时，所述第二MOS管111的漏端的电压值的发生变化，所述信号输出模块130用于生成并输出第二信号，所述第二信号用于指示所述电源电压或所述地电压出现毛刺信号。For example, when no glitch signal in the positive direction appears on the power supply voltage and no glitch signal in the negative direction appears on the ground voltage, the voltage value of the drain terminal of the second MOS tube 111 will not change, and the signal The output module 130 is used to generate and output a first signal, the first signal is used to indicate that there is no glitch signal in the power supply voltage or the ground voltage; a glitch signal in the positive direction appears on the power supply voltage and/or the When a glitch signal in the negative direction appears on the ground voltage, the voltage value of the drain terminal of the second MOS tube 111 changes, and the signal output module 130 is used to generate and output a second signal. It indicates that a glitch signal appears on the power supply voltage or the ground voltage.
例如，当所述电源电压上出现正方向的毛刺信号时，所述第二MOS管111的源端电压增大，且栅端电压不变，进而导致漏端的电压增大；当地电压上出现负方向的毛刺信号时，由于电容耦合，所述第二MOS管111的栅端的电压会下降，且源端的电压保持不变，进而导致所述第二MOS管111的漏端的电压会上升。例如，当地电压上出现负方向的毛刺信号时，由于所述第二MOS管111的漏端，会导致所述第二MOS管111的栅端的电压下降，而所述第二MOS管111的栅端的源端的电压保持不变，进而导致所述第二MOS管111的漏端的电压会上升。For example, when a glitch signal in the positive direction appears on the power supply voltage, the source terminal voltage of the second MOS tube 111 increases, and the gate terminal voltage remains unchanged, which in turn causes the drain terminal voltage to increase; the local voltage appears negative. In the case of a glitch signal in the direction, due to capacitive coupling, the voltage at the gate terminal of the second MOS tube 111 will drop, and the voltage at the source terminal will remain unchanged, which in turn causes the voltage at the drain terminal of the second MOS tube 111 to rise. For example, when a negative glitch signal appears on the local voltage, the drain terminal of the second MOS transistor 111 will cause the voltage of the gate terminal of the second MOS transistor 111 to drop, and the gate of the second MOS transistor 111 The voltage at the source terminal of the second MOS transistor 111 remains unchanged, which in turn causes the voltage at the drain terminal of the second MOS transistor 111 to rise.
相当于通过毛刺信号控制所述第二MOS管111的工作状态，即所述信号输出模块130可以根据所述第二MOS管111的漏端的电压值的变化生成并输出所述目标信号。It is equivalent to controlling the working state of the second MOS transistor 111 through a glitch signal, that is, the signal output module 130 can generate and output the target signal according to the change of the voltage value of the drain terminal of the second MOS transistor 111.
即所述毛刺信号检测电路100可以通过所述第二MOS管111，检测所述电源电压上是否出现正方向的毛刺信号以及所述地电压上是否出现负方向的毛刺信号。That is, the glitch signal detection circuit 100 can detect whether a glitch signal in a positive direction appears on the power supply voltage and whether a glitch signal in a negative direction appears on the ground voltage through the second MOS tube 111.
请继续参见图1，所述毛刺信号检测电路100还可以包括负方向毛刺检测模块230，例如所述正方向毛刺检测模块230可以为第三MOS管170，所述第三MOS管170的栅端连接至所述电源电压，所述第三MOS管170的源端连接至所述第二MOS管111的栅端，所述第三MOS管170的漏端连接至所述第一MOS管113的漏端。Please continue to refer to FIG. 1, the glitch signal detection circuit 100 may also include a negative direction glitch detection module 230. For example, the positive direction glitch detection module 230 may be a third MOS tube 170, and the gate terminal of the third MOS tube 170 Connected to the power supply voltage, the source terminal of the third MOS transistor 170 is connected to the gate terminal of the second MOS transistor 111, and the drain terminal of the third MOS transistor 170 is connected to the gate terminal of the first MOS transistor 113 Drain end.
例如，所述电源电压上未出现负方向上的毛刺信号且所述地电压上未出现正方向上的毛刺信号时，所述第三MOS管170的漏端的电压值的未发生变化，所述信号输出模块130用于生成并输出第三信号，所述第三信号用于指示所述电源电压或所述地电压未出现毛刺信号；所述电源电压上出现负方向上的毛刺信号和/或所述地电压上出现正方向上的的毛刺信号时，所述第三 MOS管170的漏端的电压值的发生变化，所述信号输出模块130用于生成并输出第四信号，所述第四信号用于指示所述电源电压或所述地电压出现毛刺信号。For example, when no glitch signal in the negative direction appears on the power supply voltage and no glitch signal in the positive direction appears on the ground voltage, the voltage value of the drain terminal of the third MOS transistor 170 does not change, and the signal The output module 130 is used to generate and output a third signal, the third signal is used to indicate that the power supply voltage or the ground voltage does not have a glitch signal; the power supply voltage has a negative glitch signal and/or When a glitch signal in the positive direction appears on the ground voltage, the voltage value of the drain terminal of the third MOS tube 170 changes, and the signal output module 130 is used to generate and output a fourth signal. It indicates that a glitch signal appears on the power supply voltage or the ground voltage.
例如，当所述电源电压上出现负方向的毛刺信号时，所述第三MOS管170的源端电压保持不变，且由于栅端电压会减小，进而导致其漏端电压增大，当所述地电压上出现正方向的毛刺信号时，所述第三MOS管170的栅端电压保持不变，由于电容耦合其源端的电压增大，进而导致所述第二MOS管的漏端的电压会上升，相当于通过毛刺信号控制所述第三MOS管170的工作状态，由此所述信号输出模块130可以根据所述第三MOS管170的漏端的电压值的变化生成并输出所述目标信号。For example, when a glitch signal in the negative direction appears on the power supply voltage, the source terminal voltage of the third MOS transistor 170 remains unchanged, and the gate terminal voltage will decrease, which will cause the drain terminal voltage to increase. When a glitch signal in the positive direction appears on the ground voltage, the gate terminal voltage of the third MOS transistor 170 remains unchanged, and the voltage at the source terminal increases due to capacitive coupling, which in turn causes the voltage at the drain terminal of the second MOS transistor Will rise, which is equivalent to controlling the working state of the third MOS transistor 170 through a glitch signal, whereby the signal output module 130 can generate and output the target according to the change in the voltage value of the drain terminal of the third MOS transistor 170 signal.
即所述毛刺信号检测电路100可以通过所述第二MOS管111，检测所述电源电压上是否出现正方向的毛刺信号以及所述地电压上是否出现负方向的毛刺信号。进一步地，可以通过所述第三MOS管170检测所述电源电压上是否出现负方向的毛刺信号以及所述地电压上是否出现正方向的毛刺信号。换句话说，所述第二MOS管111和所述第三MOS管170可以用于形成双向检测模块240，其可以实现双向glitch的检测。例如可以实现电源电压上的正方向毛刺信号和负方向毛刺信号的检测，又例如可以实现地电压上的正方向毛刺信号和负方向毛刺信号的检测。That is, the glitch signal detection circuit 100 can detect whether a glitch signal in a positive direction appears on the power supply voltage and whether a glitch signal in a negative direction appears on the ground voltage through the second MOS tube 111. Further, the third MOS transistor 170 can be used to detect whether a negative glitch signal appears on the power supply voltage and whether a positive glitch signal appears on the ground voltage. In other words, the second MOS transistor 111 and the third MOS transistor 170 can be used to form a bidirectional detection module 240, which can realize bidirectional glitch detection. For example, the detection of the positive direction burr signal and the negative direction burr signal on the power supply voltage can be realized, and for example, the detection of the positive direction burr signal and the negative direction burr signal on the ground voltage can be realized.
应理解，在一些实施例中，所述毛刺信号检测电路还可以仅包括所述电压采样模块210、第三MOS管170和所述信号输出模块130，即仅用于检测所述电源电压上是否出现负方向的毛刺信号以及所述地电压上是否出现正方向的毛刺信号。It should be understood that, in some embodiments, the glitch signal detection circuit may also only include the voltage sampling module 210, the third MOS transistor 170, and the signal output module 130, that is, it is only used to detect whether the power supply voltage is A glitch signal in a negative direction appears and whether a glitch signal in a positive direction appears on the ground voltage.
图2是图1所示的毛刺信号检测电路100在本发明一个实施例中的变形电路的示意图。2 is a schematic diagram of a modified circuit of the glitch signal detection circuit 100 shown in FIG. 1 in an embodiment of the present invention.
请参见图2，所述毛刺信号检测电路100还可以包括第四MOS管140，所述电容器160的与所述第一MOS管113的栅端相连的一端通过所述第四MOS管140连接至所述电源电压，所述电容器160的另一端连接至所述地电压。Referring to FIG. 2, the glitch signal detection circuit 100 may further include a fourth MOS transistor 140, and one end of the capacitor 160 connected to the gate terminal of the first MOS transistor 113 is connected to the fourth MOS transistor 140 through the fourth MOS transistor 140. For the power supply voltage, the other end of the capacitor 160 is connected to the ground voltage.
通过控制所述第四MOS管140的导通和关断，可以实现利用所述电容器采样所述电源电压。例如，所述第四MOS管140的栅端接收低电平控制信号时，导通所述第四MOS管140，通过所述电源电压为所述电容器160 进行充电，直至所述电容器160的电压充电至所述电源电压时，所述第四MOS管140的栅端接收高电平控制信号，关断所述第四MOS管140，使得所述电容器160的电压维持在电源电压。By controlling the on and off of the fourth MOS transistor 140, the capacitor can be used to sample the power supply voltage. For example, when the gate terminal of the fourth MOS transistor 140 receives a low-level control signal, the fourth MOS transistor 140 is turned on, and the capacitor 160 is charged by the power supply voltage until the voltage of the capacitor 160 is reached. When charged to the power supply voltage, the gate terminal of the fourth MOS transistor 140 receives a high-level control signal, and the fourth MOS transistor 140 is turned off, so that the voltage of the capacitor 160 is maintained at the power supply voltage.
请继续参见图2，所述毛刺信号检测电路100还可以包括第五MOS管150，所述第一MOS管113的漏端通过所述第五MOS管150连接至所述地电压。Please continue to refer to FIG. 2, the glitch signal detection circuit 100 may further include a fifth MOS transistor 150, and the drain terminal of the first MOS transistor 113 is connected to the ground voltage through the fifth MOS transistor 150.
通过控制所述第五MOS管150的导通和关断，可以将所述第一MOS管113漏端的电压进行重置，避免所述第一MOS管113漏端处于高阻悬空状态，进而保证所述毛刺信号检测电路100的性能。By controlling the turn-on and turn-off of the fifth MOS transistor 150, the voltage at the drain terminal of the first MOS transistor 113 can be reset to prevent the drain terminal of the first MOS transistor 113 from being in a high-impedance floating state, thereby ensuring The performance of the glitch signal detection circuit 100.
在一些实施例中，用于控制所述第四MOS管140的控制信号和用于控制第五MOS管150的控制信号可以是一组反向信号。In some embodiments, the control signal used to control the fourth MOS transistor 140 and the control signal used to control the fifth MOS transistor 150 may be a set of reverse signals.
例如，所述第五MOS管150的栅端用于接收第一信号R，所述第四MOS管140的栅端用于接收第一信号R的反向信号R_b。For example, the gate terminal of the fifth MOS transistor 150 is used to receive the first signal R, and the gate terminal of the fourth MOS transistor 140 is used to receive the reverse signal R_b of the first signal R.
例如，所述第一信号R为高电平时，所述第四MOS管140和第五MOS管150均导通，即电源电压通过所述第四MOS管140对所述电容器160进行充电，使得所述第一MOS管113的栅端N的第一电压为“1”，且所述第一MOS管113的漏端M通过第五MOS管150连接至地，以使得所述第一MOS管113的漏端M的第二电压为“0”。然后，所述第一信号R为低电平时，所述第四MOS管140和第五MOS管150均断开，使得所述第一MOS管113的栅端N的第一电压维持在“1”，所述第一MOS管113的漏端M的第二电压维持在“0”。For example, when the first signal R is at a high level, the fourth MOS transistor 140 and the fifth MOS transistor 150 are both turned on, that is, the power supply voltage charges the capacitor 160 through the fourth MOS transistor 140, so that The first voltage of the gate terminal N of the first MOS transistor 113 is "1", and the drain terminal M of the first MOS transistor 113 is connected to the ground through the fifth MOS transistor 150, so that the first MOS transistor The second voltage of the drain terminal M of 113 is "0". Then, when the first signal R is at a low level, the fourth MOS transistor 140 and the fifth MOS transistor 150 are both disconnected, so that the first voltage of the gate terminal N of the first MOS transistor 113 is maintained at "1". ", the second voltage of the drain terminal M of the first MOS transistor 113 is maintained at "0".
即通过所述控制信号能够使得所述第一MOS管113的栅端N被拉高至VDD，并使得所述第一MOS管113的漏端M被拉低至GND。That is, the gate terminal N of the first MOS transistor 113 can be pulled up to VDD through the control signal, and the drain terminal M of the first MOS transistor 113 can be pulled down to GND.
请继续参见图2，所述毛刺信号检测电路100还可以包括第一反相器211，所述第一MOS管113的漏端通过所述第一反相器211连接至所述第一MOS管113的栅端。Please continue to refer to FIG. 2, the glitch signal detection circuit 100 may also include a first inverter 211, and the drain terminal of the first MOS transistor 113 is connected to the first MOS transistor through the first inverter 211. 113's gate end.
通过控制所述第一反相器211，可以保证所述第一MOS管113的漏端的电压处于“0”，进而保证所述毛刺信号检测电路100的性能。即使所述第一MOS管113的漏端的电压升高，所述第一反相器211也可以保证所述第一MOS管113的漏端的电压恢复至“0”。而且，通过所述第一反相器，也可以避免所述电容器160出现漏电，进而保证所述电容器的电压值保持在电 源电压。由此，所述毛刺信号检测电路可以实时检测所述电源电压或地电压是否收到毛刺攻击。By controlling the first inverter 211, it can be ensured that the voltage of the drain terminal of the first MOS transistor 113 is at "0", and thus the performance of the glitch signal detection circuit 100 can be ensured. Even if the voltage of the drain terminal of the first MOS transistor 113 increases, the first inverter 211 can ensure that the voltage of the drain terminal of the first MOS transistor 113 is restored to "0". Moreover, through the first inverter, leakage of the capacitor 160 can also be avoided, thereby ensuring that the voltage value of the capacitor remains at the power supply voltage. Therefore, the glitch signal detection circuit can detect in real time whether the power supply voltage or the ground voltage is attacked by a glitch.
图3是图2所述的电路结构的另一示意图。FIG. 3 is another schematic diagram of the circuit structure described in FIG. 2.
请参见图3，所述第一反相器可以包括第六MOS管112和第七MOS管114，所述第六MOS管112的源端连接至所述电源电压，所述第六MOS管112的栅端连接至所述第七MOS管114的栅端，所述第六MOS管112的漏端连接至所述第七MOS管114的漏端，所述第七MOS管114的源端连接至所述地电压，所述第六MOS管112的漏端连接至所述第一MOS管113的栅端。3, the first inverter may include a sixth MOS transistor 112 and a seventh MOS transistor 114, the source terminal of the sixth MOS transistor 112 is connected to the power supply voltage, and the sixth MOS transistor 112 The gate terminal of the seventh MOS transistor 114 is connected to the gate terminal of the seventh MOS transistor 114, the drain terminal of the sixth MOS transistor 112 is connected to the drain terminal of the seventh MOS transistor 114, and the source terminal of the seventh MOS transistor 114 is connected To the ground voltage, the drain terminal of the sixth MOS transistor 112 is connected to the gate terminal of the first MOS transistor 113.
换句话说，所述毛刺信号检测电路100可以包括锁存器100，所述锁存器110可以包括第二MOS管111、第一MOS管113、第六MOS管112和第七MOS管114；所述第二MOS管111的源端连接至所述电源电压，所述第二MOS管111的栅端连接至所述第六MOS管112的栅端，所述第二MOS管111的漏端连接至所述第六MOS管112的漏端，所述第六MOS管112的源端连接至所述地电压，所述第一MOS管113的源端连接至所述电源电压，所述第一MOS管113的栅端连接至所述第七MOS管114的栅端，所述第一MOS管113的漏端连接至所述第七MOS管114的漏端，所述第七MOS管114的源端连接至所述地电压，所述第二MOS管111的栅端连接所述第一MOS管113的漏端，所述第一MOS管113的栅端连接至所述第二MOS管111的漏端。In other words, the glitch signal detection circuit 100 may include a latch 100, and the latch 110 may include a second MOS tube 111, a first MOS tube 113, a sixth MOS tube 112, and a seventh MOS tube 114; The source terminal of the second MOS transistor 111 is connected to the power supply voltage, the gate terminal of the second MOS transistor 111 is connected to the gate terminal of the sixth MOS transistor 112, and the drain terminal of the second MOS transistor 111 Connected to the drain terminal of the sixth MOS transistor 112, the source terminal of the sixth MOS transistor 112 is connected to the ground voltage, the source terminal of the first MOS transistor 113 is connected to the power supply voltage, and the The gate terminal of a MOS tube 113 is connected to the gate terminal of the seventh MOS tube 114, the drain terminal of the first MOS tube 113 is connected to the drain terminal of the seventh MOS tube 114, and the seventh MOS tube 114 The source terminal of the second MOS tube 111 is connected to the ground voltage, the gate terminal of the second MOS tube 111 is connected to the drain terminal of the first MOS tube 113, and the gate terminal of the first MOS tube 113 is connected to the second MOS tube The drain of 111.
基于锁存器检测电源电压或地电压上的毛刺，区别于传统的电阻电容采样结构和比较器结构。具体而言，锁存器不需要使用电阻，因此能够降低毛刺信号检测电路的面积以及硬件开销；锁存器的正反馈特性可以提高毛刺信号检测电路的检测速度；相比于电阻电容结构，锁存器的负阻迟滞特性，可以检测更低幅度的glitch信号，进而提升毛刺信号检测电路的灵敏度；锁存器的静态电流仅为所用器件的漏电电流，无静态偏置电流，能够降低毛刺信号检测电路的静态功耗；锁存器可以兼容数字(Complementary Metal-Oxide-Semiconductor Transistor，CMOS)工艺，能够增强毛刺信号检测电路的可移植性。简而言之，所述毛刺信号检测电路不仅能够检测电源电压或地电压上的毛刺，并且所述毛刺信号检测电路具有功耗低、面积小、速度快、灵敏度高以及可移植性强等优点。Detecting burrs on the power supply voltage or ground voltage based on the latch is different from the traditional resistance capacitance sampling structure and the comparator structure. Specifically, the latch does not need to use a resistor, so it can reduce the area of the glitch signal detection circuit and the hardware overhead; the positive feedback characteristic of the latch can improve the detection speed of the glitch signal detection circuit; compared to the resistance-capacitance structure, the lock The negative resistance hysteresis of the register can detect glitch signals of lower amplitude, thereby improving the sensitivity of the glitch signal detection circuit; the quiescent current of the latch is only the leakage current of the device used, and there is no static bias current, which can reduce the glitch signal The static power consumption of the detection circuit; the latch can be compatible with digital (Complementary Metal-Oxide-Semiconductor Transistor, CMOS) technology, which can enhance the portability of the glitch signal detection circuit. In short, the glitch signal detection circuit can not only detect glitches on the power supply voltage or ground voltage, but also has the advantages of low power consumption, small area, fast speed, high sensitivity, and strong portability. .
请继续参见图3，所述信号输出模块130可以为D触发器。Please continue to refer to FIG. 3, the signal output module 130 may be a D flip-flop.
此时，所述D触发器的重置(RESET)端B连接至重置信号W，例如所述重置信号W可以是上述第一信号R；所述D触发器的D端连接至VDD；所述D触发器的检测端A连接至所述第一MOS管113的漏端)，用于接收检测信号，所述D触发器的输出端Q输出目标信号(即预警(ALARM)信号)。当然，所述信号输出模块130还可以是其他器件，例如比较器。At this time, the reset (RESET) terminal B of the D flip-flop is connected to the reset signal W, for example, the reset signal W may be the above-mentioned first signal R; the D terminal of the D flip-flop is connected to VDD; The detection terminal A of the D flip-flop is connected to the drain terminal of the first MOS transistor 113) for receiving a detection signal, and the output terminal Q of the D flip-flop outputs a target signal (ie, an early warning (ALARM) signal). Of course, the signal output module 130 may also be other devices, such as a comparator.
请继续参见图3，所述毛刺信号检测电路100还可以包括阈值判决模块120，所述第一MOS管113的漏端通过所述阈值判决模块120连接至所述信号输出模块130，所述阈值判决模块120用于放大所述第一MOS管113的漏端输出的信号，并将放大后的信号发送至所述信号输出模块130。Please continue to refer to FIG. 3, the glitch signal detection circuit 100 may further include a threshold judgment module 120, the drain terminal of the first MOS transistor 113 is connected to the signal output module 130 through the threshold judgment module 120, and the threshold The judgment module 120 is used to amplify the signal output by the drain terminal of the first MOS transistor 113 and send the amplified signal to the signal output module 130.
通过所述阈值判决模块120的配合，可以检测更低幅度的glitch，进一步提升所述毛刺信号检测电路100的灵敏度。With the cooperation of the threshold judgment module 120, glitch with a lower amplitude can be detected, which further improves the sensitivity of the glitch signal detection circuit 100.
下面结合附图对所述毛刺信号检测电路100的工作原理进行详细说明。The working principle of the glitch signal detection circuit 100 will be described in detail below in conjunction with the drawings.
当VDD、GND上没有毛刺(glitch)信号出现时，经锁存器110作用，所述第一MOS管113的栅端N通过所述第四MOS管140拉高保持“1”状态，所述第一MOS管113的漏端M被所述第五MOS管150拉低保持“0”状态。When there is no glitch signal on VDD and GND, the gate terminal N of the first MOS transistor 113 is pulled high by the fourth MOS transistor 140 to maintain the "1" state through the action of the latch 110. The drain terminal M of the first MOS transistor 113 is pulled down by the fifth MOS transistor 150 to maintain a "0" state.
此时，所述毛刺信号检测电路100的静态功耗仅为所用器件的漏电功耗。At this time, the static power consumption of the glitch signal detection circuit 100 is only the leakage power consumption of the used device.
当VDD上出现正方向glitch，并且glitch幅度大于所述第二MOS管111阈值电压时，所述信号输出模块130输出的目标信号用于指示电源电压或地电压上出现glitch。When a positive glitch appears on VDD, and the glitch amplitude is greater than the threshold voltage of the second MOS transistor 111, the target signal output by the signal output module 130 is used to indicate that glitch appears on the power supply voltage or the ground voltage.
结合图3来说，所述第二MOS管111栅端(即第一MOS管113的栅端N)的电压保持不变，其源端的电压增大；glitch幅度大于所述第二MOS管111阈值电压时，所述第二MOS管111导通，并对所述第一MOS管113的漏端M进行充电，使其电压上升；锁存器110触发所述第一MOS管113的栅端N的电压下降至“0”，所述第一MOS管113的漏端M的电压进一步上升至“1”，此时阈值判决模块120输出的检测(Detection)信号被拉高至“1”。所述信号输出模块130检测到Detection信号的上升沿后，更新D触发器输出状态，即所述信号输出模块130输出的目标信号变为“1”，用于指示电源电压或地电压上出现glitch。3, the voltage at the gate terminal of the second MOS transistor 111 (that is, the gate terminal N of the first MOS transistor 113) remains unchanged, and the voltage at the source terminal increases; the glitch amplitude is greater than that of the second MOS transistor 111 When the threshold voltage is reached, the second MOS transistor 111 is turned on and charges the drain terminal M of the first MOS transistor 113 to increase its voltage; the latch 110 triggers the gate terminal of the first MOS transistor 113 The voltage of N drops to "0", and the voltage of the drain terminal M of the first MOS transistor 113 further rises to "1". At this time, the detection signal output by the threshold judgment module 120 is pulled up to "1". After the signal output module 130 detects the rising edge of the Detection signal, it updates the output state of the D flip-flop, that is, the target signal output by the signal output module 130 becomes "1", which is used to indicate the presence of glitch on the power supply voltage or the ground voltage. .
当VDD上出现正方向glitch，并且glitch幅度接近所述第二MOS管111 阈值电压时，所述信号输出模块130输出的目标信号用于指示电源电压或地电压上出现glitch。When a positive glitch appears on VDD and the magnitude of glitch is close to the threshold voltage of the second MOS transistor 111, the target signal output by the signal output module 130 is used to indicate that glitch appears on the power supply voltage or the ground voltage.
结合图3来说，所述第二MOS管111栅端(即第一MOS管113的栅端N)的电压保持不变，其源端的电压增大，glitch幅度接近所述第二MOS管111阈值电压时，VDD通过所述第二MOS管111的漏电电压对所述第一MOS管113的漏端M充电，使其电压上升；通过所述第七MOS管114对所述第一MOS管113的栅端N放电，使其电压下降；由于所述第一MOS管113的漏端M的电压上升会使得经过所述第二MOS管111的电流下降，即所述第一MOS管113的漏端M电压不再进一步上升，所述第一MOS管113的栅端N的电压不再进一步下降；通过锁存器110的作用，所述第一MOS管113的漏端M经过一段时间后会下降至“0”，所述第一MOS管113的栅端N的电压经过一段时间后会上升至“1”。例如，N和电压和M点电压的状态可以如图4所示；阈值判决模块120可以检测到第一MOS管113的漏端M的电压在一段时间内处于维持上升的状态，并将这种状态判定为“1”，即输出(Detection)信号被拉高至“1”。例如，阈值判决模块120检测到第一MOS管113的漏端M的电压V(M)与所述地电压GND的差值V(M)-GND的最大值大于或等于所述阈值判决模块120的第一阈值电压Vthn时，所述阈值判决模块120发生信号翻转(从0到1)。所述D触发器检测到Detection信号上升沿，更新D触发器输出状态，信号输出模块130输出的目标信号变为“1”，用于指示电源电压或地电压上出现glitch。With reference to FIG. 3, the voltage at the gate terminal of the second MOS transistor 111 (that is, the gate terminal N of the first MOS transistor 113) remains unchanged, and the voltage at the source terminal increases, and the glitch amplitude is close to that of the second MOS transistor 111. At the threshold voltage, VDD charges the drain terminal M of the first MOS transistor 113 through the leakage voltage of the second MOS transistor 111, causing its voltage to rise; The gate terminal N of the first MOS tube 113 discharges, causing its voltage to drop; because the voltage of the drain terminal M of the first MOS tube 113 rises, the current passing through the second MOS tube 111 decreases, that is, the voltage of the first MOS tube 113 The voltage at the drain terminal M does not rise any further, and the voltage at the gate terminal N of the first MOS transistor 113 does not fall any further; through the latch 110, the drain terminal M of the first MOS transistor 113 passes a period of time Will drop to “0”, and the voltage of the gate terminal N of the first MOS transistor 113 will rise to “1” after a period of time. For example, the states of N and voltage and M point voltage can be as shown in Figure 4; the threshold judgment module 120 can detect that the voltage of the drain terminal M of the first MOS transistor 113 is in a state of maintaining a rising state for a period of time, and then The status is judged as "1", that is, the output (Detection) signal is pulled up to "1". For example, the threshold judgment module 120 detects that the maximum value of the difference V(M)-GND between the voltage V(M) of the drain terminal M of the first MOS transistor 113 and the ground voltage GND is greater than or equal to the threshold judgment module 120 When the first threshold voltage Vthn is Vthn, the threshold judgment module 120 has a signal inversion (from 0 to 1). The D flip-flop detects the rising edge of the Detection signal and updates the output state of the D flip-flop. The target signal output by the signal output module 130 becomes "1", which is used to indicate that glitch appears on the power supply voltage or the ground voltage.
应理解，图3仅为本申请的示例，不应理解为对本申请的限制。It should be understood that FIG. 3 is only an example of this application, and should not be understood as a limitation to this application.
例如，如果所述阈值判决模块120与所述锁存器110的第一MOS管113的栅端N相连，此时，所述阈值判决模块120检测到第一MOS管113的栅端N的电压在一段时间内处于维持下升的状态时，将这种状态判定为“1”，即输出(Detection)信号被拉高至“1”。例如，阈值判决模块120检测到第一MOS管113的栅端N的电压V(N)与所述地电压GND的差值小于或等于电源电压VDD与所述阈值判决模块120的第二阈值电压Vthp的差值VDD-|Vthp|时，所述阈值判决模块120发生信号翻转(从0到1)。所述信号输出模块130中的D触发器检测到Detection信号下降沿，更新D触发器输出状态，信号输出模块130输出的目标信号变为“1”，用于指示电源电压或地电压上出现glitch。For example, if the threshold determination module 120 is connected to the gate terminal N of the first MOS transistor 113 of the latch 110, at this time, the threshold determination module 120 detects the voltage of the gate terminal N of the first MOS transistor 113 When in a state of maintaining a downward rise for a period of time, this state is judged as "1", that is, the output (Detection) signal is pulled up to "1". For example, the threshold judgment module 120 detects that the difference between the voltage V(N) of the gate terminal N of the first MOS transistor 113 and the ground voltage GND is less than or equal to the power supply voltage VDD and the second threshold voltage of the threshold judgment module 120 When the difference of Vthp is VDD-|Vthp|, the threshold judgment module 120 has a signal inversion (from 0 to 1). The D flip-flop in the signal output module 130 detects the falling edge of the Detection signal and updates the output state of the D flip-flop. The target signal output by the signal output module 130 becomes "1", which is used to indicate the presence of glitch on the power supply voltage or the ground voltage. .
当GND上出现负方向glitch，并且glitch幅度大于所述第二MOS管111阈值电压时，所述信号输出模块130输出的目标信号用于指示电源电压或地电压上出现glitch。When a negative glitch appears on the GND and the glitch amplitude is greater than the threshold voltage of the second MOS transistor 111, the target signal output by the signal output module 130 is used to indicate that glitch appears on the power supply voltage or the ground voltage.
结合图3来说，电容耦合导致所述第二MOS管111栅端的电压下降，其源端的电压保持不变，glitch幅度大于所述第二MOS管111阈值电压时，所述第二MOS管111导通，并对第一MOS管113的漏端M进行充电，使其电压上升；锁存器110使得第一MOS管113的栅端N的电压下降至“0”，所述第一MOS管113的漏端M的电压进一步上升至“1”。此时，所述阈值判决模块120输出(Detection)信号被拉高至“1”，信号输出模块130检测到Detection信号的上升沿后，更新D触发器的输出状态，即信号输出模块130输出的目标信号变为“1”，用于指示电源电压或地电压上出现glitch。3, capacitive coupling causes the voltage at the gate terminal of the second MOS tube 111 to drop, and the voltage at the source terminal remains unchanged. When the glitch amplitude is greater than the threshold voltage of the second MOS tube 111, the second MOS tube 111 Turn on and charge the drain terminal M of the first MOS transistor 113 to increase its voltage; the latch 110 causes the voltage of the gate terminal N of the first MOS transistor 113 to drop to "0", and the first MOS transistor 113 The voltage of the drain terminal M of 113 further rises to "1". At this time, the detection signal output by the threshold judgment module 120 is pulled up to "1", and the signal output module 130 updates the output state of the D flip-flop after detecting the rising edge of the Detection signal, that is, the output state of the signal output module 130 The target signal becomes "1", which is used to indicate glitch on the power supply voltage or ground voltage.
当GND上出现负方向glitch，并且glitch幅度接近所述第二MOS管111阈值电压时，所述信号输出模块130输出的目标信号用于指示电源电压或地电压上出现glitch。When a negative glitch appears on GND, and the magnitude of glitch is close to the threshold voltage of the second MOS transistor 111, the target signal output by the signal output module 130 is used to indicate that glitch appears on the power supply voltage or the ground voltage.
结合图3来说，电容耦合导致所述第二MOS管111栅端的电压下降，其源端的电压保持不变；glitch幅度接近所述第二MOS管111阈值电压时，所述电源电压通过所述第二MOS管111对第一MOS管113的漏端M进行充电，使其电压上升；经所述第七MOS管114对所述第一MOS管113的栅端N进行放电，使其电压下降；所述第一MOS管113的漏端M的电压上升使得经过所述第二MOS管111的电流下降，即所述第一MOS管113的漏端M的电压不再进一步上升，第一MOS管113的栅端N的电压不再进一步下降；通过锁存器110的作用，所述第一MOS管113的漏端M经过一段时间后会下降至“0”，所述第一MOS管113的栅端N的电压经过一段时间后会上升至“1”，具体地，N和电压和M点电压的状态可以如图4所示；阈值判决模块120可以检测到第一MOS管113的漏端M的电压在一段时间内处于维持上升的状态，并将这种状态判定为“1”，即输出(Detection)信号被拉高至“1”。所述D触发器检测到Detection信号上升沿，更新D触发器输出状态，信号输出模块130输出的目标信号变为“1”，用于指示电源电压或地电压上出现glitch。3, capacitive coupling causes the voltage at the gate terminal of the second MOS transistor 111 to drop, while the voltage at the source terminal remains unchanged; when the glitch amplitude is close to the threshold voltage of the second MOS transistor 111, the power supply voltage passes through the The second MOS tube 111 charges the drain terminal M of the first MOS tube 113 to increase its voltage; the seventh MOS tube 114 discharges the gate terminal N of the first MOS tube 113 to decrease its voltage The rise of the voltage at the drain terminal M of the first MOS tube 113 causes the current through the second MOS tube 111 to drop, that is, the voltage at the drain terminal M of the first MOS tube 113 no longer rises, the first MOS tube 113 The voltage at the gate terminal N of the tube 113 does not drop further; through the function of the latch 110, the drain terminal M of the first MOS tube 113 will drop to "0" after a period of time, and the first MOS tube 113 The voltage at the gate terminal N will rise to "1" after a period of time. Specifically, the states of the N and voltage and the voltage at point M can be as shown in FIG. 4; the threshold judgment module 120 can detect the leakage of the first MOS transistor 113 The voltage of the terminal M is in a state of maintaining a rising state for a period of time, and this state is judged as "1", that is, the output (Detection) signal is pulled up to "1". The D flip-flop detects the rising edge of the Detection signal and updates the output state of the D flip-flop. The target signal output by the signal output module 130 becomes "1", which is used to indicate that glitch appears on the power supply voltage or the ground voltage.
下面结合图3对第三MOS管170的工作原理进行说明。The working principle of the third MOS transistor 170 will be described below in conjunction with FIG. 3.
当VDD上出现负方向glitch，并且glitch幅度大于所述第三MOS管170 阈值电压时，所述信号输出模块130输出的目标信号用于指示电源电压或地电压上出现glitch。When a negative glitch appears on VDD, and the glitch amplitude is greater than the threshold voltage of the third MOS transistor 170, the target signal output by the signal output module 130 is used to indicate that glitch appears on the power supply voltage or the ground voltage.
结合图3来说，所述第三MOS管170源端(即第一MOS管113的栅端N)的电压保持不变，其栅端的电源电压下降，glitch幅度大于所述第三MOS管170阈值电压时，所述第三MOS管170导通；所述电容器160通过所述第三MOS管170对第一MOS管113的漏端M进行充电，使其电压上升，同时第一MOS管113的栅端N经过电荷分配后其电压下降；锁存器110进一步使得所述第一MOS管113的栅端N的电压下降至“0”，第一MOS管113的漏端M的电压进一步上升至“1”；此时，所述阈值判决模块120的输出(Detection)信号被拉高至“1”，所述信号输出模块130检测到Detection信号的上升沿后，更新D触发器输出状态，即信号输出模块130输出的目标信号变为“1”，用于指示电源电压或地电压上出现glitch。3, the voltage of the source terminal of the third MOS transistor 170 (that is, the gate terminal N of the first MOS transistor 113) remains unchanged, and the power supply voltage of the gate terminal drops, and the glitch amplitude is greater than that of the third MOS transistor 170 At the threshold voltage, the third MOS transistor 170 is turned on; the capacitor 160 charges the drain terminal M of the first MOS transistor 113 through the third MOS transistor 170 to increase its voltage, and the first MOS transistor 113 The voltage of the gate terminal N of the first MOS transistor 113 drops after the charge distribution; the latch 110 further reduces the voltage of the gate terminal N of the first MOS transistor 113 to "0", and the voltage of the drain terminal M of the first MOS transistor 113 further rises To "1"; at this time, the output (Detection) signal of the threshold judgment module 120 is pulled up to "1", and the signal output module 130 updates the D flip-flop output state after detecting the rising edge of the Detection signal, That is, the target signal output by the signal output module 130 becomes "1", which is used to indicate the occurrence of glitch on the power supply voltage or the ground voltage.
当VDD上出现负方向glitch，并且glitch幅度接近所述第三MOS管170阈值电压时，所述信号输出模块130输出的目标信号用于指示电源电压或地电压上出现glitch。When a negative glitch appears on VDD and the magnitude of glitch is close to the threshold voltage of the third MOS transistor 170, the target signal output by the signal output module 130 is used to indicate that glitch appears on the power supply voltage or the ground voltage.
结合图3来说，所述第三MOS管170源端(即第一MOS管113的栅端N)的电压保持不变，其栅端的电源电压下降，glitch幅度接近所述第三MOS管170阈值电压时，所述电容器160通过所述第三MOS管170对第一MOS管113的漏端M进行充电，使其电压上升，同时第一MOS管113的栅端N经过电荷分配后其电压下降；所述第一MOS管113的漏端M的电压上升使得经过所述第三MOS管170的电流下降，即所述第一MOS管113的漏端M的电压不再进一步上升，第一MOS管113的栅端N的电压不再进一步下降；通过锁存器110的作用，所述第一MOS管113的漏端M经过一段时间后会下降至“0”，所述第一MOS管113的栅端N的电压经过一段时间后会上升至“1”，具体地，N和电压和M点电压的状态可以如图4所示；阈值判决模块120可以检测到第一MOS管113的漏端M的电压在一段时间内处于维持上升的状态，并将这种状态判定为“1”，即输出(Detection)信号被拉高至“1”。所述D触发器检测到Detection信号上升沿，更新D触发器输出状态，信号输出模块130输出的目标信号变为“1”，用于指示电源电压或地电压上出现glitch。With reference to FIG. 3, the voltage at the source terminal of the third MOS transistor 170 (ie the gate terminal N of the first MOS transistor 113) remains unchanged, and the power supply voltage at the gate terminal drops, and the glitch amplitude is close to that of the third MOS transistor 170 At the threshold voltage, the capacitor 160 charges the drain terminal M of the first MOS transistor 113 through the third MOS transistor 170 to increase its voltage, and at the same time, the gate terminal N of the first MOS transistor 113 has its voltage The voltage at the drain terminal M of the first MOS tube 113 rises, so that the current passing through the third MOS tube 170 decreases, that is, the voltage at the drain terminal M of the first MOS tube 113 does not rise any further, the first The voltage of the gate terminal N of the MOS tube 113 does not drop any further; through the latch 110, the drain terminal M of the first MOS tube 113 will drop to "0" after a period of time, and the first MOS tube The voltage of the gate terminal N of the 113 will rise to “1” after a period of time. Specifically, the states of the voltage at the N and the voltage and the voltage at the M point can be as shown in FIG. 4; the threshold judgment module 120 can detect the first MOS transistor 113 The voltage of the drain terminal M is in a state of maintaining an increase for a period of time, and this state is determined as "1", that is, the output (Detection) signal is pulled up to "1". The D flip-flop detects the rising edge of the Detection signal and updates the output state of the D flip-flop. The target signal output by the signal output module 130 becomes "1", which is used to indicate that glitch appears on the power supply voltage or the ground voltage.
当GND上出现正方向glitch，并且glitch幅度大于所述第三MOS管170 阈值电压时，所述信号输出模块130输出的目标信号用于指示电源电压或地电压上出现glitch。When a positive glitch appears on the GND and the glitch amplitude is greater than the threshold voltage of the third MOS transistor 170, the target signal output by the signal output module 130 is used to indicate that glitch appears on the power supply voltage or the ground voltage.
结合图3来说，所述第三MOS管170源端(即第一MOS管113的栅端N)的电压增大，其栅端的电压保持不变，glitch幅度大于所述第三MOS管170阈值电压时，所述第三MOS管170导通，所述电容器160通过所述第三MOS管170对第一MOS管113的漏端M进行充电，使其电压上升，同时第一MOS管113的栅端N经过电荷分配后其电压下降；锁存器110进一步使得所述第一MOS管113的栅端N的电压下降至“0”，第一MOS管113的漏端M的电压进一步上升至“1”；此时，所述阈值判决模块120的输出(Detection)信号被拉高至“1”，所述信号输出模块130检测到Detection信号的上升沿后，更新D触发器输出状态，即信号输出模块130输出的目标信号变为“1”，用于指示电源电压或地电压上出现glitch。With reference to FIG. 3, the voltage at the source terminal of the third MOS transistor 170 (that is, the gate terminal N of the first MOS transistor 113) increases, the voltage at the gate terminal remains unchanged, and the glitch amplitude is greater than that of the third MOS transistor 170 At the threshold voltage, the third MOS transistor 170 is turned on, and the capacitor 160 charges the drain terminal M of the first MOS transistor 113 through the third MOS transistor 170 to increase its voltage, and the first MOS transistor 113 The voltage of the gate terminal N of the first MOS transistor 113 drops after the charge distribution; the latch 110 further reduces the voltage of the gate terminal N of the first MOS transistor 113 to "0", and the voltage of the drain terminal M of the first MOS transistor 113 further rises To "1"; at this time, the output (Detection) signal of the threshold judgment module 120 is pulled up to "1", and the signal output module 130 updates the D flip-flop output state after detecting the rising edge of the Detection signal, That is, the target signal output by the signal output module 130 becomes "1", which is used to indicate the occurrence of glitch on the power supply voltage or the ground voltage.
当VDD上出现负方向glitch，并且glitch幅度接近所述第三MOS管170阈值电压时，所述信号输出模块130输出的目标信号用于指示电源电压或地电压上出现glitch。When a negative glitch appears on VDD and the magnitude of glitch is close to the threshold voltage of the third MOS transistor 170, the target signal output by the signal output module 130 is used to indicate that glitch appears on the power supply voltage or the ground voltage.
结合图3来说，(即第一MOS管113的栅端N)的电压增大，其栅端的电压保持不变，glitch幅度接近所述第三MOS管170阈值电压时，所述电容器160经所述第三MOS管170对M点充电使M点电压上升，同时N点经电荷分配电压下降。glitch幅度接近所述第三MOS管170阈值电压时，所述第三MOS管170导通；所述电容器160通过所述第三MOS管170对第一MOS管113的漏端M进行充电，使其电压上升，同时第一MOS管113的栅端N经过电荷分配后其电压下降；所述第一MOS管113的漏端M的电压上升使得经过所述第三MOS管170的电流下降，即所述第一MOS管113的漏端M的电压不再进一步上升，第一MOS管113的栅端N的电压不再进一步下降；通过锁存器110的作用，所述第一MOS管113的漏端M经过一段时间后会下降至“0”，所述第一MOS管113的栅端N的电压经过一段时间后会上升至“1”，具体地，N和电压和M点电压的状态可以如图4所示；阈值判决模块120可以检测到第一MOS管113的漏端M的电压在一段时间内处于维持上升的状态，并将这种状态判定为“1”，即输出(Detection)信号被拉高至“1”。所述D触发器检测到Detection信号上升沿，更新D触发器输出状态，信号输出模块130输出的目标信号变为“1”，用于指示电源电 压或地电压上出现glitch。With reference to FIG. 3, the voltage at the gate terminal N of the first MOS transistor 113 increases, and the voltage at the gate terminal remains unchanged. When the glitch amplitude is close to the threshold voltage of the third MOS transistor 170, the capacitor 160 passes through The third MOS transistor 170 charges the M point to increase the voltage at the M point, and at the same time, the voltage at the N point decreases through the charge distribution. When the glitch amplitude is close to the threshold voltage of the third MOS transistor 170, the third MOS transistor 170 is turned on; the capacitor 160 charges the drain terminal M of the first MOS transistor 113 through the third MOS transistor 170 to make Its voltage rises, and at the same time the voltage of the gate terminal N of the first MOS tube 113 drops after charge distribution; the rise of the voltage of the drain terminal M of the first MOS tube 113 causes the current passing through the third MOS tube 170 to fall, that is The voltage of the drain terminal M of the first MOS tube 113 does not rise any further, and the voltage of the gate terminal N of the first MOS tube 113 does not fall further; through the latch 110, the voltage of the first MOS tube 113 The drain terminal M will drop to "0" after a period of time, and the voltage of the gate terminal N of the first MOS transistor 113 will rise to "1" after a period of time. Specifically, the state of the voltage at N and the voltage at point M It can be as shown in Fig. 4; the threshold judgment module 120 can detect that the voltage of the drain terminal M of the first MOS transistor 113 is in a state of maintaining a rising state for a period of time, and judge this state as "1", that is, output (Detection ) The signal is pulled up to "1". The D flip-flop detects the rising edge of the Detection signal and updates the output state of the D flip-flop. The target signal output by the signal output module 130 becomes "1", which is used to indicate glitch on the power supply voltage or the ground voltage.
图5是本申请实施例的阈值判决模块120的示意性电路图。FIG. 5 is a schematic circuit diagram of the threshold judgment module 120 according to an embodiment of the present application.
请参见图5，所述阈值判决模块120可以包括第八MOS管1211、第九MOS管1221和第十MOS管1212，所述第八MOS管1211的源端连接至所述电源电压，所述第八MOS管1211的栅端连接至所述第十MOS管1212的栅端，所述第八MOS管1211的漏端连接至所述第十MOS管1212的漏端，所述第十MOS管1212的源端连接至所述地电压，所述第九MOS管1221的源端连接至所述电源电压，所述第九MOS管1221的栅端连接至所述第十一MOS管1222的栅端，所述第九MOS管1221的漏端连接至所述第十一MOS管1222的漏端，所述第十一MOS管1222的源端连接至所述地电压，所述第八MOS管1211的漏端连接所述第九MOS管1221的栅端，所述第八MOS管1211的栅端连接至所述第二MOS管111的漏端，所述第九MOS管1221的漏端连接至所述信号输出模块130。Referring to FIG. 5, the threshold judgment module 120 may include an eighth MOS transistor 1211, a ninth MOS transistor 1221, and a tenth MOS transistor 1212. The source terminal of the eighth MOS transistor 1211 is connected to the power supply voltage. The gate terminal of the eighth MOS tube 1211 is connected to the gate terminal of the tenth MOS tube 1212, the drain terminal of the eighth MOS tube 1211 is connected to the drain terminal of the tenth MOS tube 1212, and the tenth MOS tube The source terminal of 1212 is connected to the ground voltage, the source terminal of the ninth MOS transistor 1221 is connected to the power supply voltage, and the gate terminal of the ninth MOS transistor 1221 is connected to the gate of the eleventh MOS transistor 1222. The drain terminal of the ninth MOS tube 1221 is connected to the drain terminal of the eleventh MOS tube 1222, the source terminal of the eleventh MOS tube 1222 is connected to the ground voltage, and the eighth MOS tube The drain terminal of 1211 is connected to the gate terminal of the ninth MOS tube 1221, the gate terminal of the eighth MOS tube 1211 is connected to the drain terminal of the second MOS tube 111, and the drain terminal of the ninth MOS tube 1221 is connected to To the signal output module 130.
可选地，所述第八MOS管1211的宽长比小于第一预设阈值，所述第九MOS管1221的宽长比大于第二预设阈值，所述第十MOS管1212的宽长比大于第三预设阈值，所述第十一MOS管1222的宽长比小于第四预设阈值，其中，所述第一预设阈值小于或等于所述第三预设阈值，所述第二预设阈值大于或等于所述第四预设阈值，以提升所述阈值判决模块120的放大效果，进而提升毛刺信号检测电路100的灵敏度。Optionally, the aspect ratio of the eighth MOS tube 1211 is less than a first preset threshold, the aspect ratio of the ninth MOS tube 1221 is greater than a second preset threshold, and the aspect ratio of the tenth MOS tube 1212 is The ratio is greater than the third preset threshold, the aspect ratio of the eleventh MOS transistor 1222 is less than the fourth preset threshold, wherein the first preset threshold is less than or equal to the third preset threshold, and the first The second preset threshold is greater than or equal to the fourth preset threshold, so as to improve the amplification effect of the threshold judgment module 120, and thereby improve the sensitivity of the glitch signal detection circuit 100.
或者说，所述第八MOS管1211和所述第十MOS管1212形成第二反相器，所述第九MOS管1221和所述第十一MOS管1222形成第三反相器，所述第二反相器的翻转阈值小于所述第三反相器的翻转阈值。例如所述第二反相器的翻转阈值为0.3，所述第三反相器的翻转阈值为0.8，即通过降低所述第二反相器的翻转阈值提升所述毛刺信号检测电路100的灵敏度，进一步地，通过增大所述第三反相器的翻转阈值，保证所述毛刺信号检测电路100的稳定性。In other words, the eighth MOS tube 1211 and the tenth MOS tube 1212 form a second inverter, the ninth MOS tube 1221 and the eleventh MOS tube 1222 form a third inverter, and the The switching threshold of the second inverter is smaller than the switching threshold of the third inverter. For example, the flip threshold of the second inverter is 0.3, and the flip threshold of the third inverter is 0.8, that is, the sensitivity of the glitch signal detection circuit 100 is improved by reducing the flip threshold of the second inverter. Further, by increasing the flip threshold of the third inverter, the stability of the glitch signal detection circuit 100 is ensured.
应理解，上述0.3和0.8仅为示例，本申请对所述第二反相器的翻转阈值和所述第三反相器的翻转阈值不做具体限定。It should be understood that the foregoing 0.3 and 0.8 are only examples, and the application does not specifically limit the switching threshold of the second inverter and the switching threshold of the third inverter.
本申请还提供了一种电子设备，所述电子设备可以包括上文所述的毛刺信号检测电路。This application also provides an electronic device, which may include the glitch signal detection circuit described above.
应理解，上文涉及的MOS管可以是金属氧化物半导体场效应晶体管 (Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)。例如“N型”MOS管(NMOSFET)与“P型”MOS管(PMOSFET)。其中，“N型”MOS管和“P型”MOS管当作开关使用时，“N型”MOS管(衬底PN结指向内的MOS管或电流流出的MOS管)的栅端接高电平时导通，接低电平时关断；“P型”MOS管(PN结指向外的MOS管或电流流入的MOS管)的栅端接高电平时关断，接低电平时导通。It should be understood that the MOS transistor mentioned above may be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). For example, "N-type" MOS tube (NMOSFET) and "P-type" MOS tube (PMOSFET). Among them, when the "N-type" MOS tube and the "P-type" MOS tube are used as switches, the gate terminal of the "N-type" MOS tube (the MOS tube with the substrate PN junction pointing inward or the MOS tube with current flowing out) is connected to the high voltage It is usually turned on and turned off when connected to a low level; when the gate terminal of a "P-type" MOS tube (a MOS tube with a PN junction pointing outward or a MOS tube through which current flows) is turned off when it is connected to a high level, it is turned on when connected to a low level.
还应理解，图1至图5仅为本申请的示例，不应理解为对本申请的限制。It should also be understood that FIGS. 1 to 5 are only examples of the present application, and should not be construed as limiting the present application.
例如，可替代地，也可以将所述第六MOS管112的漏端连接至所述信号输出模块130。For example, alternatively, the drain terminal of the sixth MOS transistor 112 may also be connected to the signal output module 130.
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及电路，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。A person of ordinary skill in the art may be aware that the units and circuits of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether these functions are executed by hardware or software depends on the specific application and design constraint conditions of the technical solution. Professionals and technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered beyond the scope of this application.
在本申请所提供的几个实施例中，应该理解到，所揭露的电路、支路和模块，可以通过其它的方式实现。例如，以上所描述的支路是示意性的，例如，该模块的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个模块可以结合或者可以集成到一个支路，或一些特征可以忽略，或不执行。In the several embodiments provided in this application, it should be understood that the disclosed circuits, branches, and modules may be implemented in other ways. For example, the branches described above are illustrative. For example, the division of the modules is only a logical function division, and there may be other divisions in actual implementation. For example, multiple modules can be combined or integrated into one branch. Road, or some features can be ignored or not implemented.
所述集成的模块如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。If the integrated module is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solution of this application essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program code .
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护 范围应以该权利要求的保护范围为准。The above are only specific implementations of this application, but the protection scope of this application is not limited to this. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this application. Should be covered within the scope of protection of this application. Therefore, the protection scope of this application shall be subject to the protection scope of the claims.

Claims (16)

  1. 一种毛刺信号检测电路，其特征在于，包括：A glitch signal detection circuit is characterized in that it comprises:
    电压采样模块，所述电压采样模块包括：A voltage sampling module, the voltage sampling module includes:
    用于采样电源电压的电容器；和Capacitors for sampling the supply voltage; and
    第一金属氧化物半导体MOS管，所述第一MOS管的栅端连接至所述电容器，所述第一MOS管的源端连接至地电压，所述电源电压上未出现毛刺信号且所述地电压上未出现毛刺信号时，所述第一MOS管的漏端的电压值为所述地电压，所述第一MOS管的栅端的电压值为通过所述电容器采样的电源电压；A first metal oxide semiconductor MOS tube, the gate terminal of the first MOS tube is connected to the capacitor, the source terminal of the first MOS tube is connected to the ground voltage, no glitch signal appears on the power supply voltage and the When there is no glitch signal on the ground voltage, the voltage value of the drain terminal of the first MOS tube is the ground voltage, and the voltage value of the gate terminal of the first MOS tube is the power supply voltage sampled by the capacitor;
    所述毛刺信号检测电路还包括第二MOS管和信号输出模块，其中：The glitch signal detection circuit further includes a second MOS tube and a signal output module, wherein:
    所述第二MOS管的一端连接至所述第一MOS管的栅端，所述第二MOS管的另一端连接至所述电源电压，所述第二MOS管的漏端连接至所述第一MOS管的漏端；One end of the second MOS tube is connected to the gate terminal of the first MOS tube, the other end of the second MOS tube is connected to the power supply voltage, and the drain terminal of the second MOS tube is connected to the first MOS tube. The drain terminal of a MOS tube;
    所述信号输出模块用于根据所述第二MOS管的漏端的电压值的变化生成并输出目标信号，所述目标信号用于指示所述电源电压或所述地电压是否出现毛刺信号。The signal output module is used to generate and output a target signal according to the change of the voltage value of the drain terminal of the second MOS tube, and the target signal is used to indicate whether a glitch signal occurs in the power supply voltage or the ground voltage.
  2. 根据权利要求1所述的毛刺信号检测电路，其特征在于，所述第二MOS管的栅端连接至所述第一MOS管的栅极，所述第二MOS管的源端连接至所述电源电压。The glitch signal detection circuit according to claim 1, wherein the gate terminal of the second MOS tube is connected to the gate of the first MOS tube, and the source terminal of the second MOS tube is connected to the voltage.
  3. 根据权利要求2所述的毛刺信号检测电路，其特征在于，所述电源电压上未出现正方向上的毛刺信号且所述地电压上未出现负方向上的毛刺信号时，所述第二MOS管的漏端的电压值的未发生变化，所述信号输出模块用于生成并输出第一信号，所述第一信号用于指示所述电源电压或所述地电压未出现毛刺信号；所述电源电压上出现正方向上的毛刺信号和/或所述地电压上出现负方向上的的毛刺信号时，所述第二MOS管的漏端的电压值的发生变化，所述信号输出模块用于生成并输出第二信号，所述第二信号用于指示所述电源电压或所述地电压出现毛刺信号。The glitch signal detection circuit according to claim 2, wherein when there is no glitch signal in the positive direction on the power supply voltage and the glitch signal in the negative direction does not appear on the ground voltage, the second MOS transistor The voltage value of the drain terminal has not changed, the signal output module is used to generate and output a first signal, and the first signal is used to indicate that there is no glitch signal in the power supply voltage or the ground voltage; the power supply voltage When a glitch signal in the positive direction appears on the upper side and/or a glitch signal in the negative direction appears on the ground voltage, the voltage value of the drain terminal of the second MOS tube changes, and the signal output module is used to generate and output The second signal, the second signal is used to indicate that a glitch signal occurs in the power supply voltage or the ground voltage.
  4. 根据权利要求2或3所述的毛刺信号检测电路，其特征在于，所述毛刺信号检测电路还包括：The glitch signal detection circuit according to claim 2 or 3, wherein the glitch signal detection circuit further comprises:
    第三MOS管，所述第三MOS管的栅端连接至所述电源电压，所述第 三MOS管的源端连接至所述第二MOS管的栅端，所述第三MOS管的漏端连接至所述第一MOS管的漏端。A third MOS tube, the gate terminal of the third MOS tube is connected to the power supply voltage, the source terminal of the third MOS tube is connected to the gate terminal of the second MOS tube, and the drain terminal of the third MOS tube The terminal is connected to the drain terminal of the first MOS tube.
  5. 根据权利要求4所述的毛刺信号检测电路，其特征在于，所述电源电压上未出现负方向上的毛刺信号且所述地电压上未出现正方向上的毛刺信号时，所述第三MOS管的漏端的电压值的未发生变化，所述信号输出模块用于生成并输出第三信号，所述第三信号用于指示所述电源电压或所述地电压未出现毛刺信号；所述电源电压上出现负方向上的毛刺信号和/或所述地电压上出现正方向上的的毛刺信号时，所述第三MOS管的漏端的电压值的发生变化，所述信号输出模块用于生成并输出第四信号，所述第四信号用于指示所述电源电压或所述地电压出现毛刺信号。The glitch signal detection circuit according to claim 4, wherein when no glitch signal in the negative direction appears on the power supply voltage and no glitch signal in the positive direction appears on the ground voltage, the third MOS transistor The voltage value of the drain terminal has not changed, the signal output module is used to generate and output a third signal, and the third signal is used to indicate that there is no glitch signal in the power supply voltage or the ground voltage; the power supply voltage When a glitch signal in the negative direction appears on the upper side and/or a glitch signal in the positive direction appears on the ground voltage, the voltage value of the drain terminal of the third MOS tube changes, and the signal output module is used to generate and output The fourth signal is used to indicate that a glitch signal occurs in the power supply voltage or the ground voltage.
  6. 根据权利要求1所述的毛刺信号检测电路，其特征在于，所述第二MOS管的源端连接至所述第一MOS管的栅极，所述第二MOS管的栅端连接至所述电源电压。The glitch signal detection circuit according to claim 1, wherein the source terminal of the second MOS tube is connected to the gate of the first MOS tube, and the gate terminal of the second MOS tube is connected to the gate of the first MOS tube. voltage.
  7. 根据权利要求1至6中任一项所述的毛刺信号检测电路，其特征在于，所述毛刺信号检测电路包括：The glitch signal detection circuit according to any one of claims 1 to 6, wherein the glitch signal detection circuit comprises:
    第四MOS管，所述电容器的与所述第一MOS管的栅端相连的一端通过所述第四MOS管连接至所述电源电压，所述电容器的另一端连接至所述地电压。In the fourth MOS transistor, one end of the capacitor connected to the gate terminal of the first MOS transistor is connected to the power supply voltage through the fourth MOS transistor, and the other end of the capacitor is connected to the ground voltage.
  8. 根据权利要求1至7中任一项所述的毛刺信号检测电路，其特征在于，所述毛刺信号检测电路还包括：The glitch signal detection circuit according to any one of claims 1 to 7, wherein the glitch signal detection circuit further comprises:
    第五MOS管，所述第一MOS管的漏端通过所述第五MOS管连接至所述地电压。A fifth MOS transistor, the drain terminal of the first MOS transistor is connected to the ground voltage through the fifth MOS transistor.
  9. 根据权利要求1至8中任一项所述的毛刺信号检测电路，其特征在于，所述毛刺信号检测电路还包括：The glitch signal detection circuit according to any one of claims 1 to 8, wherein the glitch signal detection circuit further comprises:
    第一反相器，所述第一MOS管的漏端通过所述第一反相器连接至所述第一MOS管的栅端。The first inverter, the drain terminal of the first MOS tube is connected to the gate terminal of the first MOS tube through the first inverter.
  10. 根据权利要求9所述的毛刺信号检测电路，其特征在于，所述反相器包括：The glitch signal detection circuit according to claim 9, wherein the inverter comprises:
    第六MOS管和第七MOS管，所述第六MOS管的源端连接至所述电源电压，所述第六MOS管的栅端连接至所述第七MOS管的栅端，所述第六MOS管的漏端连接至所述第七MOS管的漏端，所述第七MOS管的源端连 接至所述地电压，所述第六MOS管的漏端连接至所述第一MOS管的栅端。The sixth MOS transistor and the seventh MOS transistor, the source terminal of the sixth MOS transistor is connected to the power supply voltage, the gate terminal of the sixth MOS transistor is connected to the gate terminal of the seventh MOS transistor, and the The drain terminal of the six MOS tube is connected to the drain terminal of the seventh MOS tube, the source terminal of the seventh MOS tube is connected to the ground voltage, and the drain terminal of the sixth MOS tube is connected to the first MOS tube. The gate end of the tube.
  11. 根据权利要求1至10中任一项所述的毛刺信号检测电路，其特征在于，所述信号输出模块为D触发器。The glitch signal detection circuit according to any one of claims 1 to 10, wherein the signal output module is a D flip-flop.
  12. 根据权利要求1至11中任一项所述的毛刺信号检测电路，其特征在于，所述毛刺信号检测电路还包括：The glitch signal detection circuit according to any one of claims 1 to 11, wherein the glitch signal detection circuit further comprises:
    阈值判决模块，所述第二MOS管的漏端通过所述阈值判决模块连接至所述信号输出模块，所述阈值判决模块用于放大所述第二MOS管的漏端输出的信号，并将放大后的信号发送至所述信号输出模块。Threshold judgment module, the drain terminal of the second MOS tube is connected to the signal output module through the threshold judgment module, and the threshold judgment module is used to amplify the signal output by the drain terminal of the second MOS tube, and The amplified signal is sent to the signal output module.
  13. 根据权利要求12所述的毛刺信号检测电路，其特征在于，所述阈值判决模块包括：The glitch signal detection circuit according to claim 12, wherein the threshold judgment module comprises:
    第八MOS管、第九MOS管和第十MOS管，所述第八MOS管的源端连接至所述电源电压，所述第八MOS管的栅端连接至所述第十MOS管的栅端，所述第八MOS管的漏端连接至所述第十MOS管的漏端，所述第十MOS管的源端连接至所述地电压，所述第九MOS管的源端连接至所述电源电压，所述第九MOS管的栅端连接至所述第十一MOS管的栅端，所述第九MOS管的漏端连接至所述第十一MOS管的漏端，所述第十一MOS管的源端连接至所述地电压，所述第八MOS管的漏端连接所述第九MOS管的栅端，所述第八MOS管的栅端连接至所述第二MOS管的漏端，所述第九MOS管的漏端连接至所述信号输出模块。Eighth, ninth, and tenth MOS transistors, the source terminal of the eighth MOS transistor is connected to the power supply voltage, and the gate terminal of the eighth MOS transistor is connected to the gate of the tenth MOS transistor The drain terminal of the eighth MOS tube is connected to the drain terminal of the tenth MOS tube, the source terminal of the tenth MOS tube is connected to the ground voltage, and the source terminal of the ninth MOS tube is connected to For the power supply voltage, the gate terminal of the ninth MOS tube is connected to the gate terminal of the eleventh MOS tube, and the drain terminal of the ninth MOS tube is connected to the drain terminal of the eleventh MOS tube. The source terminal of the eleventh MOS tube is connected to the ground voltage, the drain terminal of the eighth MOS tube is connected to the gate terminal of the ninth MOS tube, and the gate terminal of the eighth MOS tube is connected to the first MOS tube. The drain terminal of the second MOS tube, and the drain terminal of the ninth MOS tube is connected to the signal output module.
  14. 根据权利要求13所述的毛刺信号检测电路，其特征在于，所述第八MOS管和所述第十MOS管形成第二反相器，所述第九MOS管和所述第十一MOS管形成第三反相器，所述第二反相器的翻转阈值小于所述第三反相器的翻转阈值。The glitch signal detection circuit according to claim 13, wherein the eighth MOS tube and the tenth MOS tube form a second inverter, and the ninth MOS tube and the eleventh MOS tube form a second inverter. A third inverter is formed, and the inversion threshold of the second inverter is smaller than the inversion threshold of the third inverter.
  15. 一种安全芯片，其特征在于，包括：A security chip, characterized in that it comprises:
    权利要求1至14中任一项所述的毛刺信号检测电路。The glitch signal detection circuit according to any one of claims 1 to 14.
  16. 一种电子设备，其特征在于，包括：An electronic device, characterized in that it comprises:
    权利要求15所述的安全芯片；和The security chip of claim 15; and
    处理器，所述处理器用于接收所述安全芯片发送的目标信号，所述目标信号用于指示电源电压或地电压是否出现毛刺信号。The processor is configured to receive a target signal sent by the security chip, and the target signal is used to indicate whether a glitch signal occurs in the power supply voltage or the ground voltage.
PCT/CN2019/092499 2019-06-24 2019-06-24 Glitch signal detection circuit, security chip, and electronic device WO2020257958A1 (en)

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CN110462410B (en) 2022-03-08
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