CN105306023B - Pulse delay circuit - Google Patents
Pulse delay circuit Download PDFInfo
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- CN105306023B CN105306023B CN201410268440.5A CN201410268440A CN105306023B CN 105306023 B CN105306023 B CN 105306023B CN 201410268440 A CN201410268440 A CN 201410268440A CN 105306023 B CN105306023 B CN 105306023B
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Abstract
A kind of pulse delay circuit, including：One drop-down unit, there is a control terminal to receive an input pulse signal, a first end is connected to a node b, and one second end is connected to a first voltage；One first pull-up unit, there is a control terminal to be connected to a node c, a first end is connected to a second voltage, and one second end is connected to node b；First delay cell, have one to reset end, an input is connected to node b, and an output end is connected to node c；One second delay cell, there is an input to be connected to node c, an output end is connected to a node d；One second pull-up unit, there is a control terminal to be connected to node d, a first end is connected to the second voltage, and one second end is connected to node c；And an inverter buffer, there is an input to be connected to node c, an output end is connected to the replacement end of first delay cell, and the output end of the inverter buffer produces the pulse signal of a delay.
Description
Technical field
The present invention relates to a kind of delay circuit, and more particularly to a kind of pulse delay circuit.
Background technology
It is well known that delay circuit turns into output signal after input signal being postponed into a special time.Therefore, Jiang Yimai
After rushing signal (pulse signal) input delay circuit, its delayed pulse signal exported (delayed pulse
Signal delay (the delay time, t of the special time) can be produced between the pulse signal of inputd)。
However, as pulse width (pulse width, t in pulse signalwidth) very narrow (be too narrow to less than special time
Section, such as 5ns) when, in the delayed pulse signal exported using in general delay circuit, the waveform (wave of its pulse
Form) will serious distortion (distortion).
Fig. 1 is refer to, it is depicted for known pulse delay circuit.Pulse delay circuit 100 includes rising trigger
(rising trigger) 102, first delay cell 104, decline the delay list of trigger (falling trigger) 106, second
Member 108.
Rise trigger 102 and receive input pulse signal Pin with declining trigger 106.Rising edge flip-flops 102 are inputting
Pulse signal Pin rising edge (rising edge) produces the first trigger signal Tr and inputs the first delay cell 104；Decline
Trigger 106 produces the second trigger signal Tf and input second in input pulse signal Pin trailing edge (falling edge)
Delay cell 108.
Furthermore the first delay cell 104 and the second delay cell 108 respectively believe the triggerings of the first trigger signal Tr and second
After number Tf delay special time of identical one, you can synthesize the pulse signal Pout of delay.
Fig. 2 is refer to, it is depicted for known another pulse delay circuit.Pulse delay circuit 200 includes delay cell
202nd, monostable flip-flop (monostable multivibrator) 204.Wherein, delay cell 202 receives input signal Pin
The input signal Pin_d of delay is produced afterwards.And the input signal Pin_d postponed can be produced after inputting monostable flip-flop 204 again
The pulse signal Pout of raw delay.
Substantially, the input signal Pin_d of delay may cause wave distortion.Furthermore according to the input signal of delay
Pin_d triggering, monostable flip-flop 204 can produce the pulse signal Pout of the undistorted delay of waveform.
However, in the field of IC designs, it is known that the circuit of monostable flip-flop 204 is complicated, has layout area
The shortcomings that (layout size) is excessive.
The content of the invention
It is a primary object of the present invention to propose a kind of new architecture and the less pulse delay circuit of circuit layout area.
The present invention relates to a kind of pulse delay circuit, including：One drop-down unit, there is a control terminal to receive an input pulse
Signal, a first end are connected to a node b, and one second end is connected to a first voltage；One first pull-up unit, there is a control
End is connected to a node c, and a first end is connected to a second voltage, and one second end is connected to node b；First delay cell,
End is reset with one, an input is connected to node b, and an output end is connected to node c；One second delay cell, has
One input is connected to node c, and an output end is connected to a node d；One second pull-up unit, there is a control terminal to be connected to
Node d, a first end are connected to the second voltage, and one second end is connected to node c；And an inverter buffer, have
One input is connected to node c, and an output end is connected to the replacement end of first delay cell, and the inverter buffer
The output end produces the pulse signal of a delay.
More preferably understand to have to the above-mentioned and other aspect of the present invention, preferred embodiment cited below particularly, and coordinate attached
Figure, is described in detail below：
Brief description of the drawings
Fig. 1 is depicted for known pulse delay circuit.
Fig. 2 is depicted for known another pulse delay circuit.
It is pulse delay circuit of the present invention and its coherent signal schematic diagram that Fig. 3 A and Fig. 3 B are depicted.
It is the first delay cell schematic diagram that Fig. 4 A and Fig. 4 B are depicted.
It is the second delay cell schematic diagram that Fig. 5 A and Fig. 5 B are depicted.
【Symbol description】
100、200：Pulse delay circuit
102：Rise trigger
104：First delay cell
106：Decline trigger
108：Second delay cell
202：Delay cell
204：Monostable flip-flop
300：Pulse delay circuit
302：First pull-up element
304：Drop down element
306：First delay cell
308：Second delay cell
310：Second pull-up element
312、402、502：Phase inverter
Embodiment
Fig. 3 A and Fig. 3 B are refer to, is pulse delay circuit of the present invention and its coherent signal schematic diagram depicted in it.Pulse
Delay circuit 300 includes the first pull-up element (pull up element) 302, drop down element (pull down element)
304th, the first delay cell 306, the second delay cell 308, second pull-up element 310, a phase inverter 312.
There is drop-down unit 304 control terminal to receive input pulse signal Pin, and first end is connected to node b, and the second end connects
It is connected to ground voltage GND.There is first pull-up unit 302 control terminal to be connected to node c, and first end is connected to a supply voltage
Vcc, the second end are connected to node b.First delay cell 306 has one to reset end (R), and its input is connected to node b, defeated
Go out end and be connected to node c.There is second delay cell 308 input to be connected to node c, and output end is connected to node d.Second
There is pull-up unit 310 control terminal to be connected to node d, and first end is connected to a power source voltage Vcc, and the second end is connected to node
c.There is phase inverter 312 input to be connected to node c, and output end is connected to the replacement end (R) of the first delay cell, and anti-phase
The output end of device 312 produces the pulse signal Pout of delay.Furthermore above-mentioned phase inverter 312 can be considered an inverter buffer
(inverted buffer).In addition, in order to improve the pulse signal Pout of delay slope, inverter buffer can also be via
Odd number (such as 3 or 5) phase inverter is concatenated to realize.
According to an embodiment of the invention, drop-down unit 304 is a N-type transistor Mn1, and its grid is drop-down unit 304
Control terminal, it is the second end of drop-down unit 304 to drain as the first end of drop-down unit 304, source electrode.First pull-up unit 302 is
One P-type transistor Mp1, its grid are the control terminal of the first pull-up unit 302, and source electrode is the first end of the first pull-up unit 302,
Drain as the second end of the first pull-up unit 302.Second pull-up unit 310 is a P-type transistor Mp2, and its grid is on second
The control terminal of unit 310 is drawn, source electrode is the first end of the second pull-up unit 310, is drained as the second of the second pull-up unit 310
End.
When the replacement end (R) of first delay cell 306 receives high level, the first delay cell 306 be reset and can not be just
Often running；And when receiving low level, the first delay cell 306 can normal operation.Furthermore normally transported in the first delay cell 306
When making, the delay time of signal delay first (td1) on node b is turned into the signal on node c afterwards.
Second delay cell 308 without resetting end, can constantly normal operation, it is by the signal delay second on node c
Delay time (td2) turns into the signal on node d afterwards.
As shown in Figure 3 B, when input pulse signal Pin is low level time point t0, node b, node c, on node d
Signal be high level, the pulse signal Pout of delay is low level.Wherein, high level can be power source voltage Vcc, and low level can
For ground voltage GND.
In time point t1, input pulse signal Pin is become by low level turns to high level.Now, drop down element 304 acts simultaneously
Signal on node b is pulled down to low level by high level, and the signal on node c, node d maintains high level, delay
Pulse signal Pout maintains low level.
In time point t2, input pulse signal Pin is become by high level turns to low level, the stopping of drop down element 304 action, and
Node b, node c, the signal on node d remain unchanged, and the pulse signal Pout of delay maintains low level.
Because the signal trailing edge on node b can be postponed the first delay time (td1) by the first delay cell 306.Therefore,
In the 3rd time point t3 after time point t1 passes through the first delay time (td1), the signal on node c is changed into from high level
Low level.Simultaneously as the signal on node c is changed into low level, the first pull-up element 302 will be caused to act, by node b
Signal is pulled to high level by low level；Also, the pulse signal Pout for the delay that phase inverter 312 exports is become by low level to be turned to
High level, and reset the first delay cell 306.Furthermore the signal on node d maintains high level.
Because the signal trailing edge on node c can be postponed the second delay time (td2) by the second delay cell 308.Therefore,
In the 4th time point t4 after time point t3 passes through the second delay time (td2), the signal on node d is changed into from high level
Low level.Simultaneously as the signal on node d is changed into low level, the second pull-up element 310 will be caused to act, by node c
Signal is pulled to high level by low level；Also, the pulse signal Pout for the delay that phase inverter 312 exports is become by high level to be turned to
Low level so that the first delay cell 306 can normal operation.Furthermore the signal on node b maintains high level.
Signal on time point t5, node d is changed to high level by low level, and the voltage on node b, node c is tieed up
Hold and maintain low level in high level, the pulse signal Pout of delay.
In time point t6, input pulse signal Pin is become again by low level turns to high level.Its operating principle and time
Point t1 is identical, repeats no more.
From more than explanation, pulse delay circuit 300 of the invention using input pulse signal Pin rising edge come
Drop down element 304 is acted, and pulse delay circuit 300 is come into operation, to produce the pulse signal Pout of delay.
Furthermore the first time delay (td1) is differed between input pulse signal Pin and the pulse signal Pout of delay.This
First time delay (td1) is controlled by the first delay cell 306.
In addition, the pulse signal Pout of delay pulse width (pulse width) is the second time delay (td2).Change
Sentence is talked about, and the pulse signal Pout of delay pulse width is controlled by the second delay cell 308.
Fig. 4 A and Fig. 4 B are refer to, is the first delay cell and its coherent signal schematic diagram depicted in it.First delay is single
Member 306 includes a phase inverter 402, resistance R1, capacitor C1, N-type transistor Mn2 and Mn3, P-type transistor Mp3 and Mp4.Its
In, the size of the first time delay is may decide that by resistance R1 and capacitor C1 numerical value.
The input of phase inverter 402 is connected to node b, and resistance R1 is connected between the output end of phase inverter 402 and node e.N-type is brilliant
Body pipe Mn2 drain electrode is connected to node e, and grid is connected to node b, and source electrode is connected to ground voltage GND.Capacitor C1 is connected to
Between node e and ground voltage GND.P-type transistor Mp3 source electrodes are connected to power source voltage Vcc, and grid is connected to node e；P-type
Transistor Mp4 source electrodes are connected to P-type transistor Mp3 drain electrodes, and grid is the replacement end (R) of the first delay cell 306, and drain electrode connects
To node c；N-type transistor Mn3 drain electrodes are connected to node c, and grid is connected to node e, and source electrode is connected to ground voltage GND.
As shown in Figure 4 B, in time point t1, the normal operation of the first delay cell 306.Now, the signal on node b is by height
Level is reduced to low level, and N-type transistor Mn2 is failure to actuate (turn off) and the output end of phase inverter 402 is converted to high level.Separately
Outside, the output end of phase inverter 402 produces a charging current via resistance R1 toward capacitor C1 so that node e voltage is by ground connection electricity
Pressure GND starts to be gradually increasing.Now, P-type transistor Mp4 acts (turn on), and N-type transistor Mn3 is failure to actuate (turn
Off), the signal on node c maintains high level.
In time point t3, node e voltage rises to power source voltage Vcc so that N-type transistor Mn3 acts (turn
On), P-type transistor Mp4 is failure to actuate (turn off), and the signal on node c is converted to low level by high level.Further, since
Signal on node b changes into high level by low level so that N-type transistor Mn2 acts (turn on) and causes node e's
Voltage is down to ground voltage GND.In other words, according to the signal intensity on node b, the signal on node e can be in ground voltage
Change between GND and power source voltage Vcc.
Furthermore input pulse signal Pin, node b, node c, the signal on node d, the clock signal Pout of delay all with
Fig. 3 B are identical, repeat no more.
Fig. 5 A and Fig. 5 B are refer to, is the second delay cell and its coherent signal schematic diagram depicted in it.Second delay is single
Member 308 includes a phase inverter 502, resistance R2, capacitor C2, N-type transistor Mn5, P-type transistor Mp5.Wherein, by resistance R2
The size of the second time delay is may decide that with capacitor C2 numerical value.
The input of phase inverter 502 is connected to node c, and resistance R2 is connected between the output end of phase inverter 502 and node f.Electric capacity
Device C2 is connected between node f and ground voltage GND.P-type transistor Mp5 source electrodes are connected to power source voltage Vcc, and grid is connected to
Node f, drain electrode are connected to node d.N-type transistor Mn5 drain electrodes are connected to node d, and grid is connected to node f, and source electrode is connected to
Ground voltage GND.
As shown in Figure 5 B, the signal on time point t3, node c is reduced to low level, the output end of phase inverter 502 by high level
Be converted to high level.In addition, the output end of phase inverter 502 produces a charging current via resistance R2 toward capacitor C2 so that node f
Voltage start to be gradually increasing.Now, P-type transistor Mp5 acts (turn on), and N-type transistor Mn5 is failure to actuate (turn
Off), the signal on node d maintains high level.
In time point t4, node f voltage rises to power source voltage Vcc so that N-type transistor Mn5 acts (turn
On), P-type transistor Mp5 is failure to actuate (turn off), and the signal on node d is converted to low level by high level.Further, since
Signal on node c changes into high level by low level, and the output end of phase inverter 502 is changed into low level, and capacitor C2 produces one and put
Electric current is via resistance R2 toward the output end of phase inverter 502 so that node f voltage starts to be gradually reduced.
In time point t5, node f voltage drops to ground voltage GND so that P-type transistor Mp5 acts (turn
On), N-type transistor Mn5 is failure to actuate (turn off), and the signal on node d is high level by low transition.In other words,
According to the signal intensity on node c, the signal on node f can change between power source voltage Vcc and ground voltage GND.
Furthermore input pulse signal Pin, node b, node c, node d, the signal on node e, the clock signal of delay
Pout is all identical with Fig. 4 B, repeats no more.
Therefore, the advantage of the invention is that proposing a kind of pulse delay circuit, its simple structure and circuit layout area is non-
It is often small.And it is possible to adjust the first delay via the numerical value of the resistance R1 and capacitor C1 in the first delay cell 306 of control
Time；And adjusted for the second time delay via the numerical value of the resistance R2 and capacitor C2 in the second delay cell 308 of control.Its
In, input pulse signal Pin after postponing for the first time delay, can produce delay via the control of the first delay cell 306
Pulse signal Pout.The pulse signal Pout of delay via the second delay cell 308 control so that the pulse signal of delay
Pout pulse width was the second time delay.
In summary, although the present invention is disclosed as above with preferred embodiment, so it is not limited to the present invention.This hair
Bright one of ordinary skill in the art without departing from the spirit and scope of the present invention, when can be used for a variety of modifications and variations.Therefore, originally
The protection domain of invention is worked as to be defined depending on appended claims confining spectrum.
Claims (9)
1. a kind of pulse delay circuit, including：
Drop-down unit, there is control terminal to receive input pulse signal, first end is connected to first node (b), and the second end is connected to
First voltage；
First pull-up unit, there is control terminal to be connected to section point (c), and first end is connected to second voltage, the connection of the second end
To the first node (b)；
First delay cell, have and reset end, input is connected to the first node (b), and output end is connected to the section point
(c)；
Second delay cell, there is input to be connected to the section point (c), output end is connected to the 3rd node (d)；
Second pull-up unit, there is control terminal to be connected to the 3rd node (d), first end is connected to the second voltage, the second end
It is connected to the section point (c)；And
Inverter buffer, there is input to be connected to the section point (c), output end be connected to first delay cell this is heavy
End is put, and the output end of the inverter buffer produces the pulse signal of delay.
2. pulse delay circuit as claimed in claim 1, wherein drop-down unit are the first N-type transistor, it is defeated that grid receives this
Enter pulse signal, source electrode is connected to the first voltage, and drain electrode is connected to the first node (b).
3. pulse delay circuit as claimed in claim 2, wherein the first pull-up unit is the first P-type transistor, grid connection
To the section point (c), source electrode is connected to the second voltage, and drain electrode is connected to the first node (b).
4. pulse delay circuit as claimed in claim 3, wherein the second pull-up unit is the second P-type transistor, grid connection
To the 3rd node (d), source electrode is connected to the second voltage, and drain electrode is connected to the section point (c), and the first voltage is to connect
Ground voltage, the second voltage are supply voltage.
5. pulse delay circuit as claimed in claim 1, wherein first delay cell are by the signal on the first node (b)
Trailing edge postponed for the first time delay, and the signal trailing edge on the section point (c) is postponed second by second delay cell
Time delay.
6. pulse delay circuit as claimed in claim 5, wherein first delay cell include：
Phase inverter, there is output end to be connected to the first node (b) with input；
Resistance, it is connected between the output end of the phase inverter and fourth node (e)；
First N-type transistor, there is drain electrode to be connected to the fourth node (e), grid is connected to the first node (b), and source electrode connects
It is connected to first voltage；
Capacitor, it is connected between the fourth node (e) and the first voltage；
First P-type transistor, there is source electrode to be connected to the second voltage, grid is connected to the fourth node (e)；
Second P-type transistor, has the drain electrode that source electrode is connected to first P-type transistor, and grid connects as the replacement end, drain electrode
It is connected to the section point (c)；And
Second N-type transistor, there is drain electrode to be connected to the section point (c), grid is connected to the fourth node (e), and source electrode connects
It is connected to the first voltage.
7. pulse delay circuit as claimed in claim 6, wherein, the first voltage is ground voltage, and the second voltage is electricity
Source voltage；And change the numerical value of the resistance and the capacitor to adjust first time delay.
8. pulse delay circuit as claimed in claim 5, wherein second delay cell include：
Phase inverter, there is output end to be connected to the section point (c) with input；
Resistance, it is connected between the output end of the phase inverter and the 5th node (f)；
Capacitor, it is connected between the 5th node (f) and the first voltage；
P-type transistor, there is source electrode to be connected to the second voltage, grid is connected to the 5th node (f), drain electrode be connected to this
Three nodes (d)；And
N-type transistor, there is drain electrode to be connected to the 3rd node (d), grid is connected to the 5th node (f), and source electrode is connected to
The first voltage.
9. pulse delay circuit as claimed in claim 8, wherein, the first voltage is ground voltage, and the second voltage is electricity
Source voltage；And change the numerical value of the resistance and the capacitor to adjust second time delay.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410268440.5A CN105306023B (en) | 2014-06-16 | 2014-06-16 | Pulse delay circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410268440.5A CN105306023B (en) | 2014-06-16 | 2014-06-16 | Pulse delay circuit |
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| Publication Number | Publication Date |
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| CN105306023A CN105306023A (en) | 2016-02-03 |
| CN105306023B true CN105306023B (en) | 2017-12-01 |
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| CN201410268440.5A Active CN105306023B (en) | 2014-06-16 | 2014-06-16 | Pulse delay circuit |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112825479A (en) * | 2019-11-20 | 2021-05-21 | 合肥格易集成电路有限公司 | Delay circuit and chip |
| CN114545807B (en) * | 2020-11-25 | 2024-03-26 | 长鑫存储技术有限公司 | Control circuit and delay circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1459683A (en) * | 2002-05-24 | 2003-12-03 | 三星电子株式会社 | Circuit and method for producing internal clock signal |
| CN101641931A (en) * | 2006-12-18 | 2010-02-03 | 艾利森电话股份有限公司 | Pulse width modulator |
| CN102111148A (en) * | 2009-12-29 | 2011-06-29 | 海力士半导体有限公司 | Delay locked loop and method for driving the same |
| CN102347761A (en) * | 2010-07-27 | 2012-02-08 | 中兴通讯股份有限公司 | Dynamic delay, and phase-frequency detector (PFD) and phase lock loop adopting same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7504896B2 (en) * | 2006-09-06 | 2009-03-17 | International Business Machines Corporation | Methods and apparatus for inline measurement of switching delay history effects in PD-SOI technology |
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2014
- 2014-06-16 CN CN201410268440.5A patent/CN105306023B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1459683A (en) * | 2002-05-24 | 2003-12-03 | 三星电子株式会社 | Circuit and method for producing internal clock signal |
| CN101641931A (en) * | 2006-12-18 | 2010-02-03 | 艾利森电话股份有限公司 | Pulse width modulator |
| CN102111148A (en) * | 2009-12-29 | 2011-06-29 | 海力士半导体有限公司 | Delay locked loop and method for driving the same |
| CN102347761A (en) * | 2010-07-27 | 2012-02-08 | 中兴通讯股份有限公司 | Dynamic delay, and phase-frequency detector (PFD) and phase lock loop adopting same |
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| CN105306023A (en) | 2016-02-03 |
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