CN102946185B - Improve the control circuit of switch power source output voltage transient response - Google Patents

Improve the control circuit of switch power source output voltage transient response Download PDF

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Publication number
CN102946185B
CN102946185B CN201210487369.0A CN201210487369A CN102946185B CN 102946185 B CN102946185 B CN 102946185B CN 201210487369 A CN201210487369 A CN 201210487369A CN 102946185 B CN102946185 B CN 102946185B
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pmos
nmos tube
grid
output
signal
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CN102946185A (en
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周泽坤
刘德尚
张晓敏
黄建刚
吴传奎
谢海武
石跃
王卓
明鑫
张波
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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Abstract

The present invention relates to switch power technology.The invention discloses a kind of control circuit improving switch power source output voltage transient response, comprise divider unit, memory cell, comparator unit; Described divider unit is connected with the drive singal of Switching Power Supply high-end switch pipe, controls described memory cell for producing control signal according to this drive singal; Described memory cell is connected with feedback voltage, under described control signal controls on the maximum of one-period feedback voltage gather and store; Described comparator unit is connected with memory cell, the instantaneous value of feedback voltage and described maximum is compared, when the instantaneous value of feedback voltage is greater than maximum, and the upset of described comparator unit output signal, shutdown switch power supply high side power pipe.Present invention achieves good output to recover, shorten recovery time and reduce overshoot voltage.The present invention can be widely used in Switching Power Supply, DC-DC converter etc.

Description

Improve the control circuit of switch power source output voltage transient response
Technical field
The present invention relates to switch power technology, particularly DC-DC (DC-to-DC) dc-dc converter output voltage transient response control circuit.
Background technology
DC-DC dc-dc converter is the time ratio that modern power electronics technology field utilizes the unlatching of the modulation system control switch pipe such as PWM (pulse width modulation) or PFM (pulse frequency modulated) and turns off, and maintains the converter of regulated output voltage.At present, conventional control mode has voltage mode to control, Controlled in Current Mode and Based and constant on-time (COT) control, and COT control model is simple with its control loop structure in recent years, advantages such as system response time is fast and being widely used, but based on the Switching Power Supply of COT control model when its load jumps to underloading by heavy duty, the transient response of output voltage is very poor.
In COT control model, when load jumps to underloading by heavy duty, output voltage can make corresponding adjustment.If circuit is desirable, so output voltage adjusts very fast, transient response can complete in a short period of time, but the reason causing output transient response not adjust very is soon that now output voltage overshoot is very large, the output current of adding at this moment is smaller, so the time of output voltage adjustment just becomes very long, the performance of Switching Power Supply transient response difference that Here it is.
Summary of the invention
Technical problem to be solved by this invention, exactly for Switching Power Supply when load jumps to underloading by heavy duty, output voltage can not complete adjustment in time, the shortcoming of transient response difference, a kind of control circuit improving switch power source output voltage transient response is provided, improves the transient response of Switching Power Supply.
The present invention solve the technical problem, and the technical scheme of employing is, improves the control circuit of switch power source output voltage transient response, it is characterized in that, comprises divider unit, memory cell, comparator unit;
Described divider unit is connected with the drive singal of Switching Power Supply high-end switch pipe, controls described memory cell for producing control signal according to this drive singal;
Described memory cell is connected with feedback voltage, under described control signal controls on the maximum of one-period feedback voltage gather and store;
Described comparator unit is connected with memory cell, the instantaneous value of feedback voltage and described maximum is compared, when the instantaneous value of feedback voltage is greater than maximum, and the upset of described comparator unit output signal, shutdown switch power supply high-end switch pipe.
Concrete, described control signal is a pair inversion signal.
Further, described divider unit has Competitive assays mechanism, occurs race hazard for avoiding.
Concrete, described divider unit comprises electrical level shift units, D flip-flop, NAND gate and 3 inverters.
Concrete, described memory cell comprises current mirror, amplifier unit, a storage capacitance and a transmission gate unit of two cascodes.
Concrete, described comparator unit comprises a comparator and a NAND gate.
The invention has the beneficial effects as follows, the shortcoming that when to overcome the load of traditional C OT control model Switching Power Supply be underloading by heavily loaded saltus step, transient response is very poor, achieve good output and recover, shorten recovery time and reduce overshoot voltage.It is simple that the present invention also has circuit structure, and the advantages such as load response is fast, can improve the transient response process of Switching Power Supply when heavily loaded saltus step is underloading.
Accompanying drawing explanation
Fig. 1 is prior art Switching Power Supply structural representation;
Fig. 2 is structural representation of the present invention;
Fig. 3 is the divider unit structural representation of embodiment;
Fig. 4 is the memory unit schematic diagram of embodiment;
Fig. 5 is the comparator unit structural representation of embodiment;
Fig. 6 is prior art switch power source output voltage waveform schematic diagram;
Fig. 7 is the switch power source output voltage waveform schematic diagram adopting control circuit of the present invention.
Signal label symbol in figure: SW, HSD, LSD represent correspondence position signal voltage in figure respectively; SW is the source voltage of high-end switch pipe HS-FET; HSD is the drive singal of high-end switch pipe HS-FET, and LSD is the drive singal of low-end switch pipe LS-FET; BST is bootstrap voltage mode; Vdd is digital power; VSS is digitally; Vin is input voltage; Vout is output voltage; VFB is feedback voltage; VFBmax is the maximum of one-period feedback voltage; Ctro1 and Ctro2 is the control signal that divider unit exports, and is two anti-phase signals; Vsoft is switch power soft-start signal; LOG is comparator unit output signal; The bias current that IB provides for switch power supply system.
Embodiment
Below in conjunction with drawings and Examples, describe technical scheme of the present invention in detail.
Switching Power Supply basic structure as shown in Figure 1, comprises control unit, Logical processing unit, drive circuit, high-end switch pipe HS-FET, low-end switch pipe LS-FET, and NMOS tube M1, diode D1 and bootstrap capacitor C bSTthe boostrap circuit etc. formed.Drive circuit is followed the output logic that Logical processing unit provides and is carried out corresponding action, high-end switch pipe HS-FET drive singal HSD drive circuit being exported when Logical processing unit is effective, when drive singal LSD is invalid, high-end switch pipe HS-FET conducting, low-end switch pipe LS-FET turns off, power supply charges to inductance L, and inductive current flows on output capacitance Cout simultaneously, makes output voltage Vout produce the ripple of following inductive current rising; Otherwise, when Logical processing unit makes the drive singal HSD of drive circuit invalid, when drive singal LSD is effective, high-end switch pipe HS-FET turns off, low-end switch pipe LS-FET opens, and Switching Power Supply is in freewheeling period, and inductance L carries out afterflow by the parasitic diode of low-end switch pipe LS-FET, electric current declines gradually, and corresponding output voltage produces and follows the downward ripple of inductive current.In this process, the sample circuit that resistance Rf1 and Rf2 is formed is also continuous samples to output voltage, and its output voltage is feedback voltage V FB.NMOS tube M1, diode D1 and bootstrap capacitor C in figure bSTthe boostrap circuit formed, its function is when making high-end switch pipe HS-FETHSD unlatching and shutoff, voltage (voltage namely in Fig. 1 between HSD and SW) between its grid and source electrode can remain in a more rational scope, is unlikely to make the driving voltage of high-end switch pipe HS-FETHSD excessive.
The present invention improves the control circuit structure of switch power source output voltage transient response as shown in Figure 2, comprises divider unit, memory cell, comparator unit.Divider unit is connected with the drive singal HSD of Switching Power Supply high-end switch pipe HS-FET, produces a pair anti-phase control signal control memory cell according to drive singal HSD.Memory cell is connected with feedback voltage V FB, under control signal controls on the maximum VFBmax of one-period feedback voltage gather and store.Comparator unit is connected with memory cell, the instantaneous value of feedback voltage V FB and this maximum VFBmax are compared, when the instantaneous value of feedback voltage V FB is greater than this maximum VFBmax, the upset of comparator unit output signal, by Logical processing unit and drive circuit shutdown switch power supply high-end switch pipe HS-FET.
The effect of divider unit does two frequency divisions to the drive singal HSD of high-end switch pipe HS-FET, two fractional frequency signals again after follow-up digital processing as the control signal of memory cell, carry out the storage operation to VFB.The signal that memory cell stores is the maximum VFBmax of feedback voltage V FB at upper one-period, it is as the input end signal of comparator unit, meanwhile feedback voltage V FB is also sent to the input of comparator unit, the instantaneous value of feedback voltage V FB and this maximum VFBmax are compared, because VFB is periodically variable with drive singal HSD, and the storage signal of feedback voltage V FB (VFBmax) each cycle replaces once, what that is comparator unit compared is the situation of change of VFB signal between adjacent two cycles.During normal work, because the VFB between the adjacent work period is consistent, so, comparator unit would not overturn, only have when output loading is underloading by heavily loaded saltus step, because output voltage there will be overshoot, so also can there is overshoot in VFB, now, because VFB has reached the comparison upper limit of comparator unit, so comparator unit output level overturns, this level, through the Logical processing unit of rear class and drive circuit, turns off high-end switch pipe HS-FET.Control circuit of the present invention is exactly shortened by such mode to export recovery time and overshoot voltage, reaches the object improved and export transient response.
Embodiment
Fig. 3, Fig. 4 and Fig. 5 respectively illustrate the structure of the divider unit of this example, memory cell and comparator unit.
Divider unit shown in Fig. 3 comprises electrical level shift units, D flip-flop, the first NAND gate NAND1 and the first inverter INV1, the second inverter INV2 and the 3rd inverter INV3, and wherein D flip-flop is connected into frequency divider (two-divider).The drive singal HSD of an input termination switch power supply high-end switch pipe HS-FET of electrical level shift units, other four inputs meet BST, SW, Vdd and VSS respectively.Its effect the square-wave signal of scope between SW and BST (drive singal HSD) is displaced to digital power Vdd and digitally on VSS, drive singal HSD is through just becoming the square-wave signal of scope between VSS and Vdd, the clock signal of this signal as frequency divider and the input signal of the first inverter after shift unit.The output of electrical level shift units connects the clock signal terminal CLK of frequency divider and the input of the first inverter, and the RD of frequency divider is its clear terminal, starts be associated with system, and often upon power-up of the system, RD carries out initialization to frequency divider.The input D of frequency divider is connected with output QN, Vdd and VSS provides VDD-to-VSS for frequency divider.The output of the first inverter INV1 connects the input of the second inverter INV2 and one end of electric capacity Cdelay, the other end ground connection of electric capacity Cdelay.Signal after displacement produces a very little time delay through the first inverter INV1 and electric capacity Cdelay, and the signal after time delay is input to the first NAND gate NAND1 again and carries out NAND operation after the second inverter INV2 together with the output Q of frequency divider.The object done like this is in order to avoid race hazard appears in signal, because HSD has a rising edge in practice after displacement, so this signal is by carrying out NAND operation with the output of frequency divider again after the process of the first inverter INV1, electric capacity Cdelay and the second inverter INV2, so just avoid two signals all in the possibility of rising edge, thus avoid race hazard, ensure that circuit normally works, Competitive assays mechanism of the present invention that Here it is.The output of the first NAND gate NAND1 is control signal Ctro1, and this signal exports control signal Ctro2 after the 3rd inverter INV3 is anti-phase.
Two anti-phase control signal Ctro1 and Ctro2 are used for the course of work of control storage unit.This routine memory cell is by the current mirror of two cascodes, amplifier unit A0, a memory cell C rEF(being in fact exactly an electric capacity) and a transmission gate unit composition.NMOS current mirror (current mirror be made up of NMOS tube) is used for processing external biasing current IB, for amplifier A0 provides biased after the electric current of PMOS current mirror (current mirror that PMOS is formed) mirror image NMOS current mirror.Amplifier A0 is connected into the degenerative form of unit gain, such structure makes the voltage of end of oppisite phase and output be clamped on VFB, when certain cycle H SD signal is high, control signal Ctro1 and Ctro2 is respectively low level and high level, such transmission gate unit is opened, and within this cycle, the maximum VFBmax of VFB is stored in memory cell C rEFon, C here rEFvery little, the object done like this is to ensure sampling precision, because the reverse input end of comparator unit is the maximum VFBmax of feedback voltage V FB in last cycle of obtaining of sampling, consider the offset voltage Vos that comparator unit is introduced simultaneously, so just be provided with one to VFB and compare the upper limit, its value is: VFBmax+Vos.This upper limit is real-time variable, and such control circuit just can realize the function of Real-Time Monitoring output voltage ripple.
This routine memory cell circuits structure as shown in Figure 4, comprises 5 NMOS tube: MN1 ~ 5,5 PMOS: MP1 ~ 5, an electric capacity CREF and amplifier A0.Wherein MN1 ~ 4 form the NMOS current mirror of cascodes, and MP1 ~ 4 form the PMOS current mirror of cascodes, MP5 and MN5 forms transmission gate unit.In Fig. 4, grid and the drain electrode of the first NMOS tube MN1 meet electric current I B, the grid of the 3rd NMOS tube MN3 and drain electrode connect the source electrode of the first NMOS tube MN1, the grid of the 3rd NMOS tube MN3 connects the grid of the 4th NMOS tube, the source ground VSS of the 3rd NMOS tube MN3 and the 4th NMOS tube MN4, the drain electrode of the 4th NMOS tube MN4 connects the source electrode of the second NMOS tube MN2, the grid of the second NMOS tube MN2 connects the grid of the first NMOS tube MN1, the drain electrode of the second NMOS tube MN2 connects grid and the drain electrode of the 3rd PMOS MP3, the source electrode of the 3rd PMOS MP3 connects grid and the drain electrode of the first PMOS MP1, the source electrode of the first PMOS MP1 and the second PMOS MP2 meets power supply Vdd, the grid of the second PMOS MP2 connects the grid of the first PMOS MP1, the drain electrode of the second PMOS MP2 connects the source electrode of the 4th PMOS MP4, the source electrode of the 4th PMOS MP4 connects the current offset point of amplifier A0, the grid of the 4th PMOS MP4 connects the grid of the 3rd PMOS MP3, the homophase termination feedback voltage V FB of amplifier A0, end of oppisite phase is connected with the output of amplifier, and be connected on the drain electrode of the 5th NMOS tube MN5 and the source electrode of the 5th PMOS MP5, the source electrode of the 5th NMOS tube MN5 and the drain electrode of the 5th PMOS MP5 are connected to VFBmax and electric capacity C rEFone end, electric capacity C rEFother end ground connection.
This routine comparator unit structure as shown in Figure 5, comprises comparator COMP and the second NAND gate NAND2.The homophase termination feedback voltage V FB of comparator COMP, anti-phase termination VFBmax, export the input meeting the second NAND gate NAND2, the soft-start signal Vsoft of another input termination switch power supply of the second NAND gate NAND2, the output signal of the second NAND gate is LOG.Like this, just Logical processing unit can be outputted to after the output signal of comparator and the soft-start signal Vsoft of Switching Power Supply carry out NAND operation.Underloading is jumped to by heavy duty when certain cycle exports, so output voltage just has a larger overshoot, at this moment VFB can trigger the comparison higher limit VFBmax+Vos of setting, thus make the output generation upset of comparator become high level (to it is worthy of note, here Vsoft is a signal relevant to system soft start, when system soft start, its value is low level, be used for initialization comparator unit, when soft start completes, its value becomes high level, so just decontrol comparator, now, the function of the second NAND gate NAND2 of rear end is just equivalent to an inverter), corresponding, signal LOG overturns as low level, then this signal function is in drive circuit, high-end switch pipe HS-FET is closed, thus reach the overshoot of improvement system under heavily loaded saltus step is underloading situation, raise the efficiency, reduce the generation of electromagnetic interference.
Fig. 6 and Fig. 7 shows prior art Switching Power Supply and have employed the Switching Power Supply of control circuit of the present invention, the waveform of output current Iout and output voltage waveforms Vout when output is underloading by heavily loaded saltus step.
Visible by the contrast of Fig. 6 and Fig. 7, prior art Switching Power Supply is when output loading generation saltus step, and overshoot voltage is larger, is Δ V, and be subject to the impact that restoring current is little, make output voltage long for recovery time, be Δ t, recovery process is slower, and the Switching Power Supply that have employed control circuit of the present invention is owing to have turned off high-end switch pipe HS-FET in time, so output can be made when load jump, overshoot value is reduced to Δ V1, and shortens to Δ t1 recovery time.In addition, it is evident that, due to output voltage generation overshoot, so ON time Ton increases, the peak value of output voltage Vout also increases to some extent, this is because Ton and Vout is directly proportional, the overshoot of Vout makes Ton have a small change, finally makes the peak value of the cycle after saltus step and output voltage increase all to some extent.
To sum up, the control circuit that the present invention improves switch electricity kind switch source output transient response overcomes the traditional C OT control circuit transient response very poor when heavily loaded saltus step is underloading, achieve good output to recover, shorten recovery time and reduce overshoot voltage.
Those of ordinary skill in the art will appreciate that, the embodiments described herein is to help reader understanding's principle of the present invention, should be understood to that protection scope of the present invention is not limited to so special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combination of not departing from essence of the present invention according to these technology enlightenment disclosed by the invention, and these distortion and combination are still in protection scope of the present invention.Particularly electrical level shift units and frequency divider can have a variety of implementation method, and certainly, the current-mirror structure in memory cell also can adopt other forms, the conventional substitute mode that these those skilled in the art adopt, all in protection scope of the present invention.

Claims (4)

1. improve the control circuit of switch power source output voltage transient response, it is characterized in that, comprise divider unit, memory cell, comparator unit;
Described divider unit is connected with the drive singal of Switching Power Supply high-end switch pipe, controls described memory cell for producing control signal according to this drive singal;
Described memory cell is connected with feedback voltage, under described control signal controls on the maximum of one-period feedback voltage gather and store;
Described comparator unit is connected with memory cell, the instantaneous value of feedback voltage and described maximum is compared, when the instantaneous value of feedback voltage is greater than maximum, and the upset of described comparator unit output signal, shutdown switch power supply high-end switch pipe;
Described control signal is a pair inversion signal;
Described divider unit has Competitive assays mechanism, occurs race hazard for avoiding.
2. the control circuit improving switch power source output voltage transient response according to claim 1, is characterized in that, described divider unit comprises electrical level shift units, D flip-flop, NAND gate and 3 inverters;
The drive singal HSD of an input termination switch power supply high-end switch pipe HS-FET of electrical level shift units, other four inputs meet bootstrap voltage mode BST, source voltage SW, the digital power Vdd of high-end switch pipe HS-FET and digitally VSS respectively; The output of electrical level shift units connects the clock signal terminal CLK of D flip-flop and the input of the first inverter, the RD of D flip-flop is its clear terminal, start with system and be associated, the input D of D flip-flop is connected with output QN, the output of the first inverter INV1 connects the input of the second inverter INV2 and one end of electric capacity Cdelay, the other end ground connection of electric capacity Cdelay; Signal after displacement produces a time delay through the first inverter INV1 and electric capacity Cdelay, and the signal after time delay is input to the first NAND gate NAND1 again and carries out NAND operation after the second inverter INV2 together with the output Q of D flip-flop; The output of the first NAND gate NAND1 is control signal Ctro1, and this signal exports control signal Ctro2 after the 3rd inverter INV3 is anti-phase.
3. the control circuit improving switch power source output voltage transient response according to claim 1, is characterized in that, described memory cell comprises:
5 NMOS tube: MN1 ~ 5,5 PMOS: MP1 ~ 5, an electric capacity and an amplifier, wherein MN1 ~ 4 form the NMOS current mirror of cascodes, and MP1 ~ 4 form the PMOS current mirror of cascodes, MP5 and MN5 forms transmission gate unit, grid and the drain electrode of the first NMOS tube MN1 meet electric current I B, the grid of the 3rd NMOS tube MN3 and drain electrode connect the source electrode of the first NMOS tube MN1, the grid of the 3rd NMOS tube MN3 connects the grid of the 4th NMOS tube, the source ground VSS of the 3rd NMOS tube MN3 and the 4th NMOS tube MN4, the drain electrode of the 4th NMOS tube MN4 connects the source electrode of the second NMOS tube MN2, the grid of the second NMOS tube MN2 connects the grid of the first NMOS tube MN1, the drain electrode of the second NMOS tube MN2 connects grid and the drain electrode of the 3rd PMOS MP3, the source electrode of the 3rd PMOS MP3 connects grid and the drain electrode of the first PMOS MP1, the source electrode of the first PMOS MP1 and the second PMOS MP2 meets power supply Vdd, the grid of the second PMOS MP2 connects the grid of the first PMOS MP1, the drain electrode of the second PMOS MP2 connects the source electrode of the 4th PMOS MP4, the source electrode of the 4th PMOS MP4 connects the current offset point of amplifier, the grid of the 4th PMOS MP4 connects the grid of the 3rd PMOS MP3, the homophase termination feedback voltage V FB of amplifier, the end of oppisite phase of amplifier is connected with the output of amplifier, and be connected on the drain electrode of the 5th NMOS tube MN5 and the source electrode of the 5th PMOS MP5, the source electrode of the 5th NMOS tube MN5 and the drain electrode of the 5th PMOS MP5 are connected to maximum VFBmax and electric capacity one end of feedback voltage, the other end ground connection of electric capacity.
4. the control circuit improving switch power source output voltage transient response according to claim 1, is characterized in that, described comparator unit comprises:
Comparator and the second NAND gate NAND2; The homophase termination feedback voltage V FB of comparator, the maximum VFBmax of anti-phase termination feedback voltage, export the input meeting the second NAND gate NAND2, the output signal of the soft-start signal Vsoft of another input termination switch power supply of the second NAND gate NAND2, the second NAND gate NAND2 is LOG signal.
CN201210487369.0A 2012-11-26 2012-11-26 Improve the control circuit of switch power source output voltage transient response Expired - Fee Related CN102946185B (en)

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