CN101510721B - Single inductance switch DC voltage converter and three mode control method - Google Patents
Single inductance switch DC voltage converter and three mode control method Download PDFInfo
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Abstract
本发明的目的是提供一种单电感开关直流电压变换器的三模式控制方法及一种实现三模式控制的单电感开关直流电压变换器,该单电感开关直流电压变换器包括PWM控制模块、PFM控制模块、逻辑转换控制模块、过零电流检测模块和PWM/PFM跳变点电流与PFM峰值电流检测模块。本发明通过系统集成的方式,通过逻辑控制方式将PWM、PFM模式和休眠模式控制模块集成到一起,实现宽负载电流条件下的模式自动切换,扩大了开关直流电压变换器的负载使用范围,提高了电能转化效率。
The object of the present invention is to provide a three-mode control method for a single-inductance switch DC voltage converter and a single-inductance switch DC voltage converter for realizing three-mode control. The single-inductance switch DC voltage converter includes a PWM control module, a PFM Control module, logic conversion control module, zero-crossing current detection module, PWM/PFM trip point current and PFM peak current detection module. The present invention integrates PWM, PFM mode and dormancy mode control modules together by means of system integration and logic control mode, realizes automatic mode switching under wide load current conditions, expands the load application range of switching DC voltage converters, and improves power conversion efficiency.
Description
技术领域 technical field
本发明涉及一种开关直流电压变换器,具体地说是一种单电感开关直流电压变换器。The invention relates to a switching DC voltage converter, in particular to a single-inductance switching DC voltage converter.
背景技术 Background technique
直流电压变换器是便携式设备通用的电源管理芯片。在应用中的要求是在各种负载电流的条件下输出电压需要稳定,纹波电压低,噪声低,而且输入电源与输出电源的变换效率高。DC voltage converters are common power management chips for portable devices. The requirements in the application are that the output voltage needs to be stable under various load current conditions, the ripple voltage is low, the noise is low, and the conversion efficiency between the input power supply and the output power supply is high.
目前,市场上的直流电压变换器主要有脉冲宽度调制(PWM)模式和脉冲频率调制(PFM)。PWM和PFM的控制方式和具体电路各不相同,在其对应负载范围内,都能保证有较高的电源转换效率。Currently, the DC voltage converters on the market mainly include pulse width modulation (PWM) mode and pulse frequency modulation (PFM). The control methods and specific circuits of PWM and PFM are different, and they can both guarantee high power conversion efficiency within the corresponding load range.
发明内容 Contents of the invention
本发明的目的是提供一种单电感开关直流电压变换器的三模式控制方法及一种实现模式控制的单电感开关直流电压变换器,实现了单电感开关直流电压变换器的PWM模式控制、PFM模式控制、休眠模式控制的自动切换。The object of the present invention is to provide a three-mode control method of a single-inductance switch DC voltage converter and a single-inductance switch DC voltage converter for realizing mode control, realizing PWM mode control and PFM mode control of the single-inductance switch DC voltage converter. Automatic switching between mode control and sleep mode control.
本发明的三模式控制方法,包括对单电感开关直流电压变换器进行PWM模式控制、PFM模式控制或休眠模式控制;在单电感开关直流电压变换器内设置过零检测模块对开关直流电压变换器的电感电流进行检测,并设置反馈电路取得单电感开关直流电压变换器的输出反馈电压;The three-mode control method of the present invention includes performing PWM mode control, PFM mode control or sleep mode control on the single-inductance switch DC voltage converter; setting a zero-crossing detection module in the single-inductance switch DC voltage converter The inductance current is detected, and the feedback circuit is set to obtain the output feedback voltage of the single-inductance switching DC voltage converter;
各种模式切换如下:Various mode switches are as follows:
开关直流电压变换器起动后,对单电感开关直流电压变换器进行PWM模式控制;After the switching DC voltage converter is started, PWM mode control is performed on the single-inductance switching DC voltage converter;
在PWM模式控制下,若检测到的电感电流不连续,对单电感开关直流电压变换器进行PFM模式控制;Under PWM mode control, if the detected inductor current is discontinuous, PFM mode control is performed on the single-inductance switching DC voltage converter;
在PFM模式控制下,若检测到的输出反馈电压小于第一基准电压或是检测到的电感电流连续,则对单电感开关直流电压变换器进行PWM模式控制;Under PFM mode control, if the detected output feedback voltage is less than the first reference voltage or the detected inductor current is continuous, then PWM mode control is performed on the single inductor switching DC voltage converter;
在PFM模式控制下,若检测到的输出反馈电压大于第二基准电压,则停止PFM模式控制,对单电感开关直流电压变换器进行休眠模式控制;Under the PFM mode control, if the detected output feedback voltage is greater than the second reference voltage, the PFM mode control is stopped, and the single-inductance switching DC voltage converter is controlled in a sleep mode;
在休眠模式控制下,若检测到的输出反馈电压小于第三基准电压,则对单电感开关直流电压变换器进行PFM模式控制;Under the dormant mode control, if the detected output feedback voltage is less than the third reference voltage, the PFM mode control is performed on the single-inductance switching DC voltage converter;
所述的第一基准电压小于第三基准电压,第三基准电压小于第二基准电压。The first reference voltage is smaller than the third reference voltage, and the third reference voltage is smaller than the second reference voltage.
在单电感开关直流电压变换器内设置跳变点电流检测模块,在PWM模式控制下,当单电感开关直流电压变换器内的开关晶体管的峰值电流小于跳变点电流时,对单电感开关直流电压变换器进行PFM模式控制。A trip point current detection module is set in the single-inductance switch DC voltage converter. Under PWM mode control, when the peak current of the switching transistor in the single-inductance switch DC voltage converter is less than the trip point current, the single-inductance switch DC The voltage converter is controlled in PFM mode.
在休眠模式下关闭单电感开关直流电压变换器的开关晶体管。The switching transistor of the single-inductor switching DC voltage converter is turned off in sleep mode.
本发明的单电感开关直流电压变换器,包括控制模块,所述的单电感开关直流电压变换器包括一个PMOS晶体管和一个NMOS晶体管,PMOS晶体管的源极连接输入电源,漏极连接NMOS晶体管的漏极,NMOS晶体管的源极接地,在PMOS晶体管的漏极和NMOS晶体管的源极之间设置有输出支路,所述单电感开关直流电压变换器的电感串联在该输出支路中;The single-inductance switching DC voltage converter of the present invention includes a control module, the single-inductance switching DC voltage converter includes a PMOS transistor and an NMOS transistor, the source of the PMOS transistor is connected to the input power supply, and the drain is connected to the drain of the NMOS transistor pole, the source of the NMOS transistor is grounded, and an output branch is provided between the drain of the PMOS transistor and the source of the NMOS transistor, and the inductance of the single-inductance switch DC voltage converter is connected in series in the output branch;
所述的控制模块包括PWM模式控制模块、PFM模式控制模块、用于切换PWM模式控制和PFM控制并进行休眠模式控制的逻辑转换控制模块、用于检测所述电感电流的过零电流检测模块、用于取得输出反馈电压的分压反馈电路;The control module includes a PWM mode control module, a PFM mode control module, a logic conversion control module for switching PWM mode control and PFM control and performing sleep mode control, a zero-crossing current detection module for detecting the inductor current, A voltage-dividing feedback circuit for obtaining an output feedback voltage;
过零电流检测模块和分压反馈电路将得到反馈信号发送给逻辑转换控制模块;The zero-crossing current detection module and the voltage division feedback circuit send the obtained feedback signal to the logic conversion control module;
逻辑转换控制模块根据反馈信号,向PWM模式控制模块和PFM模式控制模块发送模式选择信号;The logic conversion control module sends a mode selection signal to the PWM mode control module and the PFM mode control module according to the feedback signal;
PWM模式控制模块和PFM模式控制模块根据模式选择信号,向逻辑控制模块发送相应的控制信号;The PWM mode control module and the PFM mode control module send corresponding control signals to the logic control module according to the mode selection signal;
逻辑转换控制模块连接PMOS晶体管和NMOS晶体管的栅极,对单电感开关直流电压变换器进行模式控制。The logic conversion control module is connected to the gates of the PMOS transistor and the NMOS transistor, and performs mode control on the single-inductance switching DC voltage converter.
在控制模块内设置有用于检测开关晶体管电流的跳变点电流检测模块。A trip point current detection module for detecting the current of the switching transistor is arranged in the control module.
所述的逻辑转换控制模块包括接收电感输出端电压和第四基准电压的过零负载比较器、接收电感输入端电压和跳变点基准电压的跳变点电流比较器、接收输出反馈电压和第一基准电压的第一低电压比较器、接收输出反馈电压和第二基准电压的第一高电压比较器、接收输出反馈电压和第三基准电压的第二低电压比较器,过零负载比较器、跳变点电流比较器、第一低电压比较器、第一高电压比较器、第二低电压比较器的输出端通过逻辑门电路输出模式切换信号和休眠信号。The logic conversion control module includes a zero-crossing load comparator receiving the inductor output voltage and the fourth reference voltage, a trip point current comparator receiving the inductor input voltage and the trip point reference voltage, and receiving the output feedback voltage and the fourth reference voltage. A first low-voltage comparator for a reference voltage, a first high-voltage comparator for receiving an output feedback voltage and a second reference voltage, a second low-voltage comparator for receiving an output feedback voltage and a third reference voltage, and a zero-crossing load comparator , the trip point current comparator, the first low voltage comparator, the first high voltage comparator, and the output terminals of the second low voltage comparator output a mode switching signal and a dormancy signal through a logic gate circuit.
所述的PWM模式控制模块接收输出反馈电压、基准电压和模式切换信号,并通过逻辑转换模块向PMOS晶体管和NMOS晶体管的栅极发送控制信号。The PWM mode control module receives the output feedback voltage, the reference voltage and the mode switching signal, and sends control signals to the gates of the PMOS transistor and the NMOS transistor through the logic conversion module.
所述的PFM模式控制模块基准电流和电感输出端电流的峰值电流比较器、接收第二基准电压和输出反馈电压的第二高电压比较器、接收输出反馈电压和第三基准电压的第三低电压比较器、接收电感输出端近似为0时对应的基准电压和电感输出端电流的过零负载电流比较器,PFM模式控制模块根据模式切换信号,通过逻辑转换模块向PMOS晶体管和NMOS晶体管的栅极发送控制信号。The PFM mode control module reference current and the peak current comparator of the inductor output terminal current, the second high voltage comparator receiving the second reference voltage and the output feedback voltage, the third low voltage comparator receiving the output feedback voltage and the third reference voltage The voltage comparator, the zero-crossing load current comparator that receives the corresponding reference voltage when the output terminal of the inductor is approximately 0 and the current at the output terminal of the inductor, the PFM mode control module sends the gate of the PMOS transistor and the NMOS transistor through the logic conversion module according to the mode switching signal Pole sends a control signal.
本发明的优点是:本发明通过系统集成的方式,通过逻辑控制方式将PWM、PFM模式和休眠模式控制模块集成到一起,实现宽负载电流条件下的模式自动切换,扩大了开关直流电压变换器的负载使用范围,提高了电能转化效率。The advantages of the present invention are: the present invention integrates the PWM, PFM mode and dormancy mode control modules together by means of system integration and logic control, so as to realize automatic switching of modes under wide load current conditions and expand the range of switching DC voltage converters. The range of load usage improves the power conversion efficiency.
附图说明 Description of drawings
图1是本发明的单电感开关直流电压变换器的结构示意图;Fig. 1 is the structural representation of the single inductance switch DC voltage converter of the present invention;
图2是PWM、PFM和休眠模式的逻辑控制单元电路图;Fig. 2 is a logic control unit circuit diagram of PWM, PFM and sleep mode;
图3是PWM模式控制模块的电路图;Fig. 3 is a circuit diagram of a PWM mode control module;
图4是PFM模式控制模块的电路图。FIG. 4 is a circuit diagram of a PFM mode control module.
具体实施方式 Detailed ways
如图1所示,本实施例的三模式控制的直流电压转换器芯片电路由控制模块和片内输出级电路组成。控制模块包括由逻辑控制模块、PWM控制模块、PFM控制模块、PWM/PFM跳变点电流检测和PFM峰值电流检测模块、过零电流检测模块组成。各个模块的电源电压,即为从片外向片内输入的电压Vin。EN信号是片外输入的使能信号,当EN为“1”时,芯片正常工作;为“0”时,芯片不工作。片内输出级电路的SW节点和地(GND)之间外接片外由电感L和电容Cout组成的滤波电路,其中的RESR为电容寄生电阻。Rf1和Rf2组成了输出电压Vout的反馈电路,VFB反馈信号输入到PWM控制模块、PFM控制模块、逻辑控制模块。电阻RL是负载电阻。As shown in FIG. 1 , the three-mode control DC voltage converter chip circuit of this embodiment is composed of a control module and an on-chip output stage circuit. The control module includes a logic control module, a PWM control module, a PFM control module, a PWM/PFM trip point current detection module, a PFM peak current detection module, and a zero-crossing current detection module. The power supply voltage of each module is the voltage V in input from the off-chip to the on-chip. The EN signal is an enable signal input outside the chip. When EN is "1", the chip works normally; when it is "0", the chip does not work. An off-chip filter circuit consisting of an inductor L and a capacitor C out is connected between the SW node of the on-chip output stage circuit and the ground (GND), where R ESR is the parasitic resistance of the capacitor. R f1 and R f2 form the feedback circuit of the output voltage V out , and the V FB feedback signal is input to the PWM control module, the PFM control module, and the logic control module. Resistor RL is the load resistance.
当上电启动开始时,由于输出电压Vout低,系统工作在PWM模式下,逻辑控制模块输出Mode_select信号为“1”,PFM控制模块不工作。这时PWM/PFM跳变点电流检测和PFM峰值电流检测模块检测PWM/PFM跳变点电流。When power-on starts, because the output voltage V out is low, the system works in PWM mode, the logic control module outputs the Mode_select signal as "1", and the PFM control module does not work. At this time, the PWM/PFM trip point current detection and PFM peak current detection modules detect the PWM/PFM trip point current.
当上电启动完成后时,控制电路开始判定输出电流的大小,有以下两种状态可以使电路从PWM模式转换到PFM模式:(1)当过零电流检测模块检测到PWM模式控制中有电感电流不连续的情况存在,即电感电流中有零电流出现,输出Vsw_load信号给逻辑控制模块;(2)PWM/FPM跳变点电流模块当检测到芯片片内输出级电路中的PMOS管SP的开关电流的峰值小于一个设定值Iskip时,输出Vskip信号给逻辑控制模块。When the power-on start-up is completed, the control circuit begins to determine the magnitude of the output current. There are the following two states that can switch the circuit from PWM mode to PFM mode: (1) When the zero-crossing current detection module detects that there is an inductance in the PWM mode control The current discontinuity exists, that is, there is zero current in the inductor current, and the V sw_load signal is output to the logic control module; (2) When the PWM/FPM trip point current module detects that the PMOS transistor SP in the on-chip output stage circuit When the peak value of the switching current is less than a set value I skip , a V skip signal is output to the logic control module.
如果不满足上述条件,系统维持原来的PWM模式的工作状态。如果上述两个条件中的任何一个情况出现,那么系统将转换到PFM模式的工作状态。这时Vmode_select信号为“0”,PFM控制模块工作。PWM/PFM跳变点电流检测/PFM峰值电流检测模块的PFM峰值电流检测模块工作。If the above conditions are not met, the system maintains the original PWM mode working state. If any one of the above two conditions occurs, the system will switch to the working state of PFM mode. At this time, the Vmode_select signal is "0", and the PFM control module works. The PFM peak current detection module of the PWM/PFM trip point current detection/PFM peak current detection module works.
在PFM模式下,如果PFM峰值电流检测模块检测到电感电流的平均值大于设置的限制电流点Ipeak时,片内输出级电路中的PMOS管SP关断,NMOS管SN开通,降低输出的电压值,以保证输出电流不大于设定的限流点。In PFM mode, if the PFM peak current detection module detects that the average value of the inductor current is greater than the set limit current point I peak , the PMOS transistor SP in the on-chip output stage circuit is turned off, and the NMOS transistor SN is turned on to reduce the output voltage. value to ensure that the output current is not greater than the set current limit point.
PWM控制模块和PFM控制模块的输出信号分别为pwm_ctr和pfm_ctr。在PWM或PFM模式下工作时,上述信号输入到逻辑控制模块,并通过驱动电路输出sp_g和sn_g信号。sp_g和sn_g信号分别连接到片内输出级电路的PMOS管SP和NMOS管SN的栅极。当Vin(VDD)通过SP管对SW节点充电时,sp_g为“0”,P管开通,同时sn_g为“0”,SN管断开;片外电感通过SW节点放电时;sp_g为“1”,SP管断开,同时sn_g为“1”,SN管开通。The output signals of the PWM control module and the PFM control module are pwm_ctr and pfm_ctr respectively. When working in PWM or PFM mode, the above signals are input to the logic control module, and the sp_g and sn_g signals are output through the drive circuit. The sp_g and sn_g signals are respectively connected to the gates of the PMOS transistor SP and the NMOS transistor SN of the on-chip output stage circuit. When V in (V DD ) charges the SW node through the SP tube, sp_g is "0", the P tube is turned on, and at the same time sn_g is "0", the SN tube is turned off; when the off-chip inductor is discharged through the SW node; sp_g is "1", the SP tube is disconnected, and at the same time sn_g is "1", the SN tube is turned on.
如图2所示的逻辑控制模块电路,由过零负载电流比较器3、跳变点电流比较器4、高电压比较器5、低电压比较器1、低电压比较器2、或门、与门、反相器组成。过零负载电流比较器3的正端连接电感电流近似为零时对应的基准电压Vload_comp_vip,负端连接对应于输出级的电感电流IL的电压Vsw_load。跳变点电流比较器4的正端连接基准电压Vskip_comp_vip,该电压对应的输出电流为80mA,正端连接反应SW节点电流,即输出电流对应的电压信号Vsw_skip。低电压比较器2的正端连接输出电压的分压反馈电压Vfb,负端连接基准电压Vlow_ref2。高电压比较器5的正端连接输出电压的分压反馈电压Vfb,负端连接基准电压Vhigh_ref。低电压比较器1的正端连接输出电压的分压反馈电压Vfb,负端连接基准电压Vlow_ref。逻辑转换控制模块的输出信号有Mode_select,以及Sleep_mode_en。The logic control module circuit shown in Figure 2 consists of a zero-crossing
当片外的电感电流为零时,Vsw_load比Vload_comp_vip的值小,因此过零负载电流比较器的输出为“0”,经过门电路后,Mode_select信号为“0”,并输出,使系统电路转换到PFM模式。同样,当Vsw_skip信号值较Vskip_comp_vip信号值大时,跳变点电流比较器输出为“0”,这样,Mode_select信号为“0”,并输出,使系统电路转换到PFM模式。如果Vfb较Vlow_ref2的电压值,那么,低电压比较器2输出“0”,并通过门电路使Vmode_select信号为“1”,并输出,使系统电路转换到PWM模式。When the off-chip inductor current is zero, V sw_load is smaller than V load_comp_vip , so the output of the zero-crossing load current comparator is "0". After passing through the gate circuit, the Mode_select signal is "0" and output, making the system circuit transitions to PFM mode. Similarly, when the value of the V sw_skip signal is greater than the value of the V skip_comp_vip signal, the output of the trip point current comparator is "0", so that the Mode_select signal is "0" and output, so that the system circuit switches to the PFM mode. If V fb is higher than the voltage value of V low_ref2 , then the
另外,当Vfb电压值大于Vhigh_ref时,Vsleep_mode_on信号为“1”,并输出给PFM控制模块,并通过PFM控制模块的输出信号,以及逻辑控制电路模块使SP管和SN管都关闭,这样系统进入休眠模式。同理,如果VFB电压值低于Vlow_ref时,Sleep_mode_on信号为“0”,电路系统退出休眠模式。基准电压值Vhigh_ref最大,Vlow_ref次之,Vlow_ref2最小。In addition, when the V fb voltage value is greater than V high_ref , the V sleep_mode_on signal is "1", and is output to the PFM control module, and through the output signal of the PFM control module and the logic control circuit module, both the SP tube and the SN tube are turned off, This will put the system into hibernation mode. Similarly, if the V FB voltage value is lower than V low_ref , the Sleep_mode_on signal is "0", and the circuit system exits the sleep mode. The reference voltage value V high_ref is the largest, followed by V low_ref , and V low_ref2 is the smallest.
如图3所示的PWM控制模块,由跨导放大器Gm、PWM比较器6、D触发器、或非门和反相器组成。跨导放大器Gm的输入负端接收Vfb信号,它是输出电压的分压反馈电压;正端接收基准电压Vref。PWM比较器6的正端接收Vcomp信号,它是与功率管的导通时间成比例的电压信号;PWM比较器6的负端与跨导放大器Gm的输出端以及电容C和NMOS管M1的漏端相连。D触发器的CLK端口与外接的时钟信号CLK相连接。The PWM control module shown in Figure 3 is composed of transconductance amplifier Gm, PWM comparator 6, D flip-flop, NOR gate and inverter. The input negative terminal of the transconductance amplifier Gm receives the V fb signal, which is the divided feedback voltage of the output voltage; the positive terminal receives the reference voltage V ref . The positive terminal of the PWM comparator 6 receives the V comp signal, which is a voltage signal proportional to the conduction time of the power tube; the negative terminal of the PWM comparator 6 is connected to the output terminal of the transconductance amplifier Gm and the capacitor C and the NMOS tube M1 Drain connected. The CLK port of the D flip-flop is connected to the external clock signal CLK.
PWM的控制环路工作过程如下:在每个时钟周期开始时,CLK产生一个时钟上升沿,D触发器触发,QB端输出为低电平,因此SP管导通,SN管断开,流过电感上的电流IL增加,当IL大于Iout时,Vout开始上升。在这个过程中,M1管的栅极信号为“0”,M1管断开,跨导放大器(GM)的输出电流对C1电容进行充电,该充电电流与Vfb和Vref电压的差值成正比,这样使PWM比较器6的负端电压上升,当该电压大于Vcom时,PWM比较器输出为“0”,D触发器复位,QB端输出为高电平“1”,使SN管导通,SP管断开,电感上的电流下降。当IL小于Iout时,Vout开始下降。这时,M1管的栅电压为“1”,M1管导通,电容C1对地放电,当C1上的电压低于Vcomp时,PWM比较器6输出翻转为高电平。至此完成一个时钟周期的PWM控制并等待下一周期的CLK上升沿到来。The working process of the PWM control loop is as follows: at the beginning of each clock cycle, CLK generates a clock rising edge, the D flip-flop triggers, and the output of the QB terminal is low, so the SP tube is turned on, the SN tube is turned off, and the flow The current I L on the inductance increases, and when I L is greater than I out , V out starts to rise. In this process, the gate signal of the M1 tube is "0", the M1 tube is disconnected, and the output current of the transconductance amplifier (GM) charges the C1 capacitor, and the charging current is proportional to the difference between the voltages of V fb and V ref Proportional, so that the negative terminal voltage of the PWM comparator 6 rises, when the voltage is greater than Vcom, the output of the PWM comparator is "0", the D flip-flop is reset, and the output of the QB terminal is a high level "1", so that the SN tube When it is turned on, the SP tube is disconnected, and the current on the inductor drops. When IL is less than I out , V out starts to drop. At this time, the gate voltage of the M1 tube is "1", the M1 tube is turned on, and the capacitor C1 is discharged to the ground. When the voltage on the C1 is lower than V comp , the output of the PWM comparator 6 is reversed to a high level. At this point, the PWM control of one clock cycle is completed and the CLK rising edge of the next cycle is waiting for the arrival.
如图4所示的PFM控制模块,由峰值电流比较器7、高电压比较器8、低电压比较器9、过零负载电流比较器10、D触发器、与门和或门组成。峰值电流比较器7的正端连接基准电流Ipeak,负端连接输出级的电感电流IL;高电压比较器8的正端接收基准电压Vhigh_ref,负端接收输出电压的分压反馈电压Vfb。低电压比较器9的正端接收收输出电压的分压反馈电压Vfb,负端接收基准电压Vlow_ref。过零负载电流比较器10的正端连接近似为零的基准电流信号I0A,负端连接输出级的电感电流IL。通过高电压比较器8和低电压比较器9的输入基准电压Vhigh_ref和Vlow_ref的设定,使片外输出电路的输出电压Vout,在PFM模式工作时,其值控制在Vhigh_ref和Vlow_ref之间。The PFM control module shown in Figure 4 consists of a peak
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