CN103248221B - Step-down controller - Google Patents

Abstract

A step-down converter, comprising a conversion circuit, a zero-crossing comparator, a current comparator, a voltage comparator and a PFM control circuit, the conversion circuit includes a switch tube Q1 connected to an input terminal and a power supply, an output terminal and the switch tube The switch tube Q2 connected to the output terminal of Q1 and grounded at the input terminal, an inductor L connected to the output terminal of the switch tube Q1 at one end, a capacitor C connected to the inductor L at one end and grounded at the other end, and a resistor connected in parallel to both ends of the capacitor C R1; the voltage comparator, zero-crossing comparator, and current comparator input the comparison results into the PFM control circuit for control; the PFM control circuit outputs control according to the comparison results of the voltage comparator, current comparator, and zero-crossing comparator A control signal for on-off of the switch tube Q1 and the switch tube Q2. The above step-down converter adopts an internally generated digital signal as a control signal, and a dynamic partial shutdown strategy is adopted in the PFM control circuit, so as to effectively reduce system loss.

Description

buck converter

【Technical field】

The invention relates to the field of electronic circuits, in particular to a step-down converter.

【Background technique】

With the development of integrated circuit technology, integrated circuit components are becoming more and more miniaturized, which makes the integration of integrated circuits higher and higher. Excessive voltage in integrated circuits will make metal oxide semiconductor field effect transistors (MOS transistors) ) breakdown, the circuit will not work if it is light, and the entire circuit will be damaged if it is serious. Therefore, it is necessary to reduce the higher DC voltage provided by the outside to a lower DC voltage for the integrated circuit to work. A proper power supply voltage can not only protect the integrated circuit, but also effectively reduce the power consumption of the whole system.

Systems used in biomedical engineering are generally powered by batteries or lithium batteries, and are required to be portable and able to work for a long time. This requires that DC-DC voltage converters used in biomedical engineering systems need to have the characteristics of low power consumption and high efficiency.

Power management DC-DCs that can be used for portable medical equipment include: 1. Low Dropout Linear Power Supply (Low Drop Output, LDO); 2. Switched Capacitor Converter (Switched Capacitor Converter); 3. Switching power supply type DC-DC.

LDO has ultra-low output voltage noise, which is its biggest advantage, but the disadvantage of LDO linear regulated power supply is that when the voltage difference between the input voltage and output voltage is large, the loss on the adjustment tube is large, resulting in low efficiency. Low.

Switched capacitor DC-DC converters have poor load capacity and are not suitable for relatively large loads. In addition, in modern microelectronics technology, the resistance integrated in the chip generally does not exceed 500KΩ, and the capacitance does not exceed 50pF. This is because if the integrated resistance or integrated capacitance exceeds these values, their nonlinearity will greatly damage the performance of the circuit. The loss outweighs the gain. In view of the unique characteristics of switched capacitors: large capacitance, this feature limits the application of switched capacitors.

Traditional switching power supply DC-DC converters include pulse-width modulation (Pulse-Width Modulation, PWM) control mode, or pulse-width modulation and pulse-frequency modulation (Pulse-Frequency Modulation, PFM) hybrid modulation (PWM/PFM) mode.

In the PWM control mode, because the switching power tube and the rectifier tube are always in the switching state, and the frequency is generally high, reaching several MHz, resulting in a large switching loss, resulting in a huge loss of system power consumption. In this case, the efficiency drops rapidly. Not conducive to the power management requirements of the biomedical engineering field. However, the structure required by the PFM control method is more complicated, and additional modules such as negative delay and one-shot signal generation are required. More modules are likely to cause system instability, oscillation, and additional power loss.

【Content of invention】

Based on this, it is necessary to provide a low-power and high-efficiency step-down converter to solve the problem of low efficiency and extra power loss in the traditional step-down conversion method.

A step-down converter, including a conversion circuit, a zero-crossing comparator, a current comparator, a voltage comparator and a PFM control circuit

The conversion circuit includes a switching tube Q1 whose input end is connected to the power supply, a switching tube Q2 whose output end is connected to the output end of the switching tube Q1 and whose input end is grounded, an inductor L whose one end is connected to the output end of the switching tube Q1, and an inductor L whose one end is connected to the output end of the switching tube Q1. The inductance L is connected to a capacitor C whose other end is grounded and a resistor R1 connected in parallel to both ends of the capacitor C;

The inverting input terminal of the voltage comparator is connected to the node between the inductor L and the capacitor C, the non-inverting input terminal inputs a reference voltage, and the comparison result is input into the PFM control circuit;

The non-inverting input terminal of the current comparator is connected to the input terminal of the switching tube Q1, the inverting input terminal inputs the current peak value of the inductor L, and the comparison result is input into the PFM control circuit;

The non-inverting input terminal of the zero-crossing comparator is connected to the output terminal of the switching tube Q1, the inverting input terminal is grounded, and the comparison result is input into the PFM control circuit;

The PFM control circuit outputs a control signal for controlling the switching of the switching tube Q1 and the switching tube Q2 according to the comparison results of the voltage comparator, the current comparator and the zero-crossing comparator.

Preferably, the current comparator includes a positive-phase current mirror module and a reverse-phase current mirror module, wherein,

The current I _in input by the positive-phase input terminal of the current comparator is mirrored by the positive-phase current mirror module and the current I _in input by the negative-phase input terminal of the current comparator is mirrored by the negative-phase current mirror module to the same node a;

If I _in + is greater than I _in -, the voltage of the node a is pulled up and the output terminal of the current comparator outputs a high level;

If I _in + is smaller than I _in −, the voltage of the node a is pulled down and the output terminal of the current comparator outputs a low level.

Preferably, the positive-phase current mirror module includes a first current mirror and a second current mirror, wherein,

The first current mirror includes N-channel MOS transistors NMOS1, MOS transistors NMOS2, MOS transistors NMOS3, MOS transistors NMOS4 and resistor R2, wherein,

The drain of the MOS transistor NMOS1 is connected to the current I _in + through the resistor R2, the gate is connected to the gate of the MOS transistor NMOS2, and then the current I _in + is connected, and the source is connected to the drain of the MOS transistor NMOS3, The gate of the MOS transistor NMOS3 is connected to the gate of the MOS transistor NMOS4 and then connected to the drain of the MOS transistor NMOS1, the source is grounded to the source of the MOS transistor NMOS4, and the drain of the MOS transistor NMOS4 is connected to the drain of the MOS transistor NMOS1. The source of the MOS transistor NMOS2 is connected, and the drain of the MOS transistor NMOS2 is connected to the second current mirror;

The second current mirror includes a P-channel MOS transistor PMOS1, a MOS transistor PMOS2, a MOS transistor PMOS3, a MOS transistor PMOS4, and a resistor R3, wherein,

The source of the MOS transistor PMOS1 is connected to the drain of the MOS transistor NMOS2 through the resistor R3, and the gate is connected to the gate of the MOS transistor PMOS2, and then connected to the drain of the MOS transistor NMOS2, and the drain is connected to the MOS transistor The source of PMOS3 is connected, the gate of the MOS transistor PMOS3 is connected to the gate of the MOS transistor PMOS4 and then connected to the source of the MOS transistor PMOS1, and the drain is connected to the drain of the MOS transistor PMOS4, and the gate of the MOS transistor PMOS4 The source is connected to the drain of the MOS transistor PMOS2, and the source of the MOS transistor PMOS2 outputs a positive-phase mirror current.

Preferably, the inverting current mirror module includes N-channel MOS transistors NMOS5, MOS transistors NMOS6, MOS transistors NMOS7, MOS transistors NMOS8 and resistor R4, wherein,

The drain of the MOS transistor NMOS5 is connected to the current I _in − through the resistor R4, the gate is connected to the gate of the MOS transistor NMOS6, and the current I _in − is connected to the drain, and the source is connected to the drain of the MOS transistor NMOS7, The gate of the MOS transistor NMOS7 is connected to the gate of the MOS transistor NMOS8 and then connected to the drain of the MOS transistor NMOS5, the source is grounded to the source of the MOS transistor NMOS8, and the drain of the MOS transistor NMOS8 is connected to the drain of the MOS transistor NMOS8. The source of the transistor NMOS6 is connected, and the drain of the MOS transistor NMOS6 outputs an inverse mirror current and the source of the MOS transistor PMOS2 is connected to output a positive mirror current.

Preferably, the current comparator further includes a first inverter and a second inverter, wherein,

The first inverter includes a P-channel MOS transistor PMOS5 and an N-channel MOS transistor NMOS9, the drain of the MOS transistor PMOS5 is connected to the drain of the MOS transistor PMOS4, and the source is connected to the drain of the MOS transistor NMOS9 , the gate is connected to the gate of the MOS transistor NMOS9 and then connected to the node a;

The second inverter includes a P-channel MOS transistor PMOS6 and an N-channel MOS transistor NMOS10, the drain of the MOS transistor PMOS6 is connected to the drain of the MOS transistor PMOS5, and the gate is connected to the gate of the MOS transistor NMOS10 The node b connected to the source of the MOS transistor PMOS5 and the drain of the MOS transistor NMOS10 is the output terminal of the current comparator.

Preferably, the PFM control module includes an AND gate, a first NOT gate, a second NOT gate, an OR gate, a NOR gate and an RS flip-flop, wherein,

The two input ends of the AND gate are respectively connected with the output end of the voltage comparator and the output end of the zero-crossing comparator, and the output end is connected with the R end of the RS flip-flop, and one input end of the OR gate is passed through the The first NOT gate is connected to the output terminal of the voltage comparator, the other input terminal is connected to the output terminal of the current comparator, the output terminal is connected to the S terminal of the RS flip-flop, and the input of the first NOT gate The terminal is connected with the output terminal of the voltage comparator, and the output terminal is connected with an input terminal of the OR gate;

The Q terminal of the RS flip-flop outputs an on-off control signal driven by the drive unit to control the on-off of the switching tube Q1;

The Q terminal of the RS flip-flop is connected to an input terminal of the NOR gate through the second NOT gate, and the other input terminal of the NOR gate is connected to the output terminal of the zero-crossing comparator, and the output terminal outputs The on-off control signal is driven by the driving unit to control the on-off of the switching tube Q2.

Preferably, a current detection circuit is further included, and the non-inverting input terminal of the current comparator is connected to the input terminal of the switch tube Q1 through the current detection circuit.

Preferably, the current detection circuit includes a P-channel MOS transistor PMOS7, a MOS transistor PMOS8 and an amplifier, wherein,

The switching tube Q1 is a P-channel power MOS tube, the switching tube Q2 is an N-channel rectifying MOS tube, the MOS tube PMOS7 is connected to the power MOS tube with common drain and common gate, and the source of the MOS tube PMOS7 is It is connected with one input end of the amplifier, the other input end of the amplifier is connected with the drain of the MOS transistor PMOS8 and the source of the power MOS transistor, the output end is connected with the gate of the MOS transistor PMOS8, and the MOS transistor PMOS8 source output sense current.

Preferably, a bandgap reference is further included, the voltage comparator is a hysteresis comparator, and the bandgap reference is connected to the non-inverting input end of the hysteresis comparator.

Preferably, it also includes a voltage dividing resistor R5 and a voltage dividing resistor R6, the hysteresis comparator non-inverting input terminal is connected to the node between the inductor L and the capacitor C through the voltage dividing resistor R5, and through the voltage dividing resistor R5 The piezoresistor R6 is grounded.

The above step-down converter detects whether the current of the inductor L reaches the peak value through the current comparator, thereby sending a signal to the PFM control circuit to control the closing of the switch tube Q1, and the zero-crossing comparator detects whether the drain voltage of the switch tube Q1 is negative, thereby detecting Whether the current of the inductor L is reversed, a signal is sent to the PFM control circuit to control the closing of the switch tube Q2, thereby preventing energy from flowing from the capacitor C to the ground, resulting in unnecessary power loss. The internally generated digital signal is used as the control signal, thereby eliminating the need for additional control modules such as negative delay and monostable trigger signal, improving the stability of the circuit, and reducing the complexity of the circuit structure and power consumption. At the same time, a dynamic partial shutdown strategy is adopted in the PFM control circuit, which effectively reduces system loss and improves efficiency.

【Description of drawings】

Figure 1 is a block diagram of a buck converter;

Fig. 2 is the schematic diagram of the step-down converter in the preferred embodiment;

Fig. 3 is the schematic diagram of the current comparator in the preferred embodiment;

Fig. 4 is the schematic diagram of the current detection circuit in the preferred embodiment;

Fig. 5 is the schematic diagram of the voltage comparator in the preferred embodiment;

Fig. 6 is the control signal of the inductor current I _L and the switching tube Q1 and the switching tube Q2 under the step-down converter continuous mode;

Fig. 7 is the simulation waveform of the output voltage V _out and the inductor current I _L when the input is V _in =5V;

Figure 8 is the simulation waveform of the output voltage V _out and the inductor current I _L when the input is V _in =3.5V;

Fig. 9 is the simulation waveform when the input is a step voltage V _in =6V to V _in =3.5V;

Fig. 10 is the output waveform when the load current is the step current _Iload =0mA to _Iload =24mA;

Figure 11 is the efficiency curve when the load current varies from 0 to 10mA.

【Detailed ways】

In order to make the purpose, technical solution and advantages of the present invention more clear, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

As shown in FIG. 1 , a buck converter includes a conversion circuit 100 , a current comparator 200 , a zero-crossing comparator 300 , a voltage comparator 400 and a PFM control circuit 500 .

The conversion circuit 100 includes a switching tube Q1 whose input end is connected to a power supply, a switching tube Q2 whose output end is connected to the output end of the switching tube Q1 and whose input end is grounded, an inductor L connected to the output end of the switching tube Q1 at one end, and an inductor L connected to the other end. A capacitor C with one end grounded and a resistor R1 connected in parallel to both ends of the capacitor C. In this embodiment, the switching transistor Q1 is a P-channel MOS transistor, and the switching transistor Q2 is an N-channel MOS transistor. In other embodiments, the switching tube Q1 and the switching tube Q2 may be replaced by controllable switching devices such as IGBT (Insulated Gate Bipolar Translator, insulated gate transistor). The conversion circuit 100 is a step-down chopper circuit (BuckChopper), which is a DC chopper that steps down the input and output voltages, that is, the output voltage is lower than the input voltage. Due to its superior voltage transformation function, it can directly Used where direct pressure reduction is required.

As shown in FIG. 2 , the non-inverting input terminal of the current comparator 200 is connected to the input terminal of the switch tube Q1 , the inverting input terminal inputs the current peak value I _peak of the inductor L, and the comparison result V _ie is input to the PFM control circuit 500 . The current comparator 200 detects whether the inductor current I _L reaches the peak value I _peak , so that the PFM control circuit 500 is used to control the switching off of the switch tube Q1 .

The non-inverting input terminal of the zero-crossing comparator 300 is connected to the output terminal of the switch tube Q1 , the inverting input terminal is grounded, and the comparison result V _inv is input to the PFM control circuit 500 . The zero-crossing comparator 300 detects whether the output voltage V _sw of the switch tube Q1 is negative, thereby detecting whether the current of the inductor L is reversed, and turns off the switch tube Q2, thereby preventing energy from flowing from the capacitor C to the ground, resulting in unnecessary power consumption loss.

The inverting input terminal of the voltage comparator 400 is connected to the node between the inductor L and the capacitor C, the reference voltage V _ref is input to the non-inverting input terminal, and the comparison result is input into the PFM control circuit 500 . In this embodiment, the voltage comparator 400 is preferably a hysteresis comparator, and the bandgap reference 700 is connected to the non-inverting input terminal of the hysteresis comparator to provide the reference voltage V _ref for the voltage comparator 400 .

The PFM control circuit 500 outputs a control signal for controlling the switching of the switching tube Q1 and the switching tube Q2 according to the comparison results of the current comparator 200 , the zero-crossing comparator 300 and the voltage comparator 400 .

The PFM control module 500 includes an AND gate, a first NOT gate, a second NOT gate, an OR gate, a NOR gate and an RS flip-flop M.

The two input terminals of the AND gate are respectively connected to the output terminal of the voltage comparator 400 and the output terminal of the zero-crossing comparator 300, and the output terminal is connected to the R terminal of the RS flip-flop M, and one input terminal of the OR gate is compared with the voltage through the first NOT gate The output terminal of the device 400 is connected to the other input terminal and the output terminal of the current comparator 200, the output terminal is connected to the S terminal of the RS flip-flop M, the input terminal of the first NOT gate is connected to the output terminal of the voltage comparator 400, and the output terminal Connect with an input of the OR gate.

The Q terminal of the RS flip-flop M outputs an on-off control signal PFM_P, which is driven by the driving unit 502 to control the on-off of the switch tube Q1. The Q terminal of the RS flip-flop M is connected to one input terminal of the NOR gate through the second NOT gate, and the other input terminal of the NOR gate is connected to the output terminal of the zero-crossing comparator 300, and the output terminal outputs the on-off control signal PFM_N through the drive unit 502 is driven to control the on-off of the switch tube Q2.

As shown in FIG. 3 , in this embodiment, the current comparator 200 includes a normal-phase current mirror module 210 , an inverse-phase current mirror module 220 , a first inverter 230 and a second inverter 240 .

The current I _in input by the positive phase input terminal of the current comparator 200 + the current I in input by the negative phase input terminal of the current comparator 200 mirrored by the positive phase current mirror module 210 _- (inductor peak current I _peak ) by the negative phase current mirror module 220 is mirrored to the same node a;

The positive phase current mirror module 210 includes a first current mirror 202 and a second current mirror 204 .

The first current mirror 202 includes N-channel MOS transistors NMOS1 , MOS transistors NMOS2 , MOS transistors NMOS3 , MOS transistors NMOS4 and a resistor R2 .

The drain of the MOS transistor NMOS1 is connected to the current I _in + through the resistor R2, the gate is connected to the gate of the MOS transistor NMOS2, and then the current I _in + is connected, the source is connected to the drain of the MOS transistor NMOS3, and the gate of the MOS transistor NMOS3 is connected to the MOS The gate of the tube NMOS4 is connected to the drain of the MOS tube NMOS1, the source is grounded to the source of the MOS tube NMOS4, the drain of the MOS tube NMOS4 is connected to the source of the MOS tube NMOS2, and the drain of the MOS tube NMOS2 is connected to the second current mirror;

The second current mirror includes a P-channel MOS transistor PMOS1, a MOS transistor PMOS2, a MOS transistor PMOS3, a MOS transistor PMOS4 and a resistor R3.

The source of the MOS tube PMOS1 is connected to the drain of the MOS tube NMOS2 through the resistor R3, the gate of the MOS tube PMOS1 is connected to the gate of the MOS tube PMOS2, and then connected to the drain of the MOS tube NMOS2, and the drain of the MOS tube PMOS1 is connected to the source of the MOS tube PMOS3. The gate of the tube PMOS3 is connected to the gate of the MOS tube PMOS4 and then connected to the source of the MOS tube PMOS1, the drain of the MOS tube PMOS3 is connected to the drain of the MOS tube PMOS4, the source of the MOS tube PMOS4 is connected to the drain of the MOS tube PMOS2, and the drain of the MOS tube PMOS2 The source outputs a positive-phase mirror current.

The inverting current mirror module 220 includes N-channel MOS transistors NMOS5 , MOS transistors NMOS6 , MOS transistors NMOS7 , MOS transistors NMOS8 and a resistor R4.

The drain of the MOS transistor NMOS5 is connected to the current I _in - through the resistor R4, the gate of the MOS transistor NMOS5 is connected to the gate of the MOS transistor NMOS6, and then the current I _in - is connected, the source of the MOS transistor NMOS5 is connected to the drain of the MOS transistor NMOS7, and the MOS transistor NMOS5 is connected to the drain of the MOS transistor NMOS7. The gate of NMOS7 is connected to the gate of MOS transistor NMOS8 and then connected to the drain of MOS transistor NMOS5, the source of MOS transistor NMOS7 is connected to the source of MOS transistor NMOS8, the drain of MOS transistor NMOS8 is connected to the source of MOS transistor NMOS6, and the drain of MOS transistor NMOS6 The output negative-phase mirror current is connected to the source of the MOS transistor PMOS2 and the output positive-phase mirror current meets at node a.

If I _in + is greater than I _in -, the voltage of node a is pulled up and outputs a high level at the output terminal of the current comparator 200, that is, V ₀ is high at this time; if I _in + is less than I _in -, the node a The voltage of a is pulled down and the output terminal of the current comparator 200 outputs a low level, that is, V ₀ is at a low level at this time.

The current comparator 200 also includes a first inverter 230 and a second inverter 240 .

The first inverter 230 includes a P-channel MOS transistor PMOS5, an N-channel MOS transistor NMOS9, the drain of the MOS transistor PMOS5 is connected to the drain of the MOS transistor PMOS4, the source of the MOS transistor PMOS5 is connected to the drain of the MOS transistor NMOS9, and the drain of the MOS transistor PMOS5 The gate is connected to the gate of the MOS transistor NMOS9 and connected to node a;

The second inverter 240 includes a P-channel MOS transistor PMOS6 and an N-channel MOS transistor NMOS10, the drain of the MOS transistor PMOS6 is connected to the drain of the MOS transistor PMOS5, the gate of the MOS transistor PMOS6 is connected to the gate of the MOS transistor NMOS10, and then connected to the MOS transistor The node b where the source of PMOS5 is connected, the source of MOS transistor PMOS6 is connected to the drain of MOS transistor NMOS10 is the output terminal of the current comparator 200 .

The first inverter 230 and the second inverter 240 . The node voltage V ₀ for driving node a conforms to the input request of the PFM control module 500 . The current comparator 200 in this embodiment only uses two mirror current circuits to compare the input current after mirroring. The structure is very simple, and because the driving current is very low, the power consumption is also very low, only tens of nanowatts.

As shown in FIG. 5 , it is a schematic diagram of a voltage comparator 400 . The voltage comparator 400 adopts the most classic voltage comparator, has a simple structure and low power consumption, and is very suitable for low power consumption requirements of portable medical equipment.

Referring to FIG. 2 , the non-inverting input terminal of the current comparator 200 is connected to the input terminal of the switch tube Q1 through the current detection circuit 600 .

As shown in FIG. 4, the current detection circuit 600 includes a P-channel MOS transistor PMOS7, a MOS transistor PMOS8 and an amplifier, wherein,

As mentioned above, the switching tube Q1 is a P-channel power MOS tube, the switching tube Q2 is an N-channel rectifying MOS tube, the MOS tube PMOS7 is connected to the switching tube Q1, that is, the power MOS tube, and the source of the MOS tube PMOS7 is connected to One input terminal of the input amplifier is connected, the other input terminal of the amplifier is connected with the drain of the MOS tube PMOS8 and the source of the power MOS tube (switching tube Q1), the output terminal is connected with the gate of the MOS tube PMOS8, and the source of the MOS tube PMOS8 outputs the detection current I _in +.

The current detection circuit 600 mirrors the current on the switching tube Q1 through the MOS transistor PMOS7, and then detects and outputs it through the current-carrying circuit.

according to:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}\mathrm{<span\; class="notranslate">\; \&mu;Cox</span>}\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; GS</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; the\; th</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

Wherein, I _d is the drain current flowing through the MOS transistor PMOS7, that is, the conduction current.

μ is the surface mobility (cm ² /V*s) of an N-channel or P-channel device.

Cox is the gate oxide capacitance per unit area (F/cm ² ).

W and L are the effective channel width and length of the MOS transistor PMOS7 respectively.

V _GS is the voltage between the gate and source of the MOS transistor PMOS7.

V _th is the threshold voltage of the MOS transistor PMOS7.

When V _GS (PMOS7)＝V _GS (Q1), we know

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; PMOS</span>}\mathrm{<span\; class="notranslate">\; 7</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; :</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; Q</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span>}_{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; PMOS</span>}\mathrm{<span\; class="notranslate">\; 7</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; :</span>{<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span>}_{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; Q</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; in</span>}}<span\; class="notranslate">\; +</span><span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; Q</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; *</span><span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; W</span>}}_{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; PMOS</span>}\mathrm{<span\; class="notranslate">\; 7</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; L</span>}}_{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; Q</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}}{{\mathrm{<span\; class="notranslate">\; W</span>}}_{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; Q</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; L</span>}}_{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; PMOS</span>}\mathrm{<span\; class="notranslate">\; 7</span>}<span\; class="notranslate">\; )</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

Wherein, _ID (PMOS7) and _ID (Q1) are conduction currents of the MOS transistor PMOS7 and the switch transistor Q1 respectively, and W and L are the width and length of the MOS transistor PMOS7 respectively.

It can be seen from formula (3) that the relationship between I _in + and the inductor current I _L is determined by the width-to-length ratio of the MOS transistor PMOS7 and the switch transistor Q1. Therefore, it can be detected accurately by controlling their width-to-length ratio. the inductor current I _L .

As shown in FIG. 2 , including a voltage dividing resistor R5 and a voltage dividing resistor R6, the hysteresis comparator, that is, the positive phase input terminal of the voltage comparator 400 is connected to the node between the inductor L and the capacitor C through the voltage dividing resistor R5, and the voltage dividing resistor R6 is grounded.

The basic topology of the conversion circuit 100 is shown in FIG. 2 . _Vin is the input voltage, usually powering an external power supply. The switching tube Q1 and the switching tube Q2 are power MOS tubes and rectification MOS tubes. In practical applications, the switch tube Q1 and the switch tube Q2 are usually implemented by MOS tubes with a large width-to-length ratio. In the normal working process, the switch tube Q1 and the switch tube Q2 are turned on at a certain time sequence, and the conduction time of the switch tube Q1 is ton. It means that the ratio of the turn-on time toff of the switch tube Q2 to the entire switching cycle is called the turn-off duty cycle, which is expressed by Doff.

Firstly, it is assumed that the switching tube Q1 and the switching tube Q2 are ideal switches, and their on-resistances are both 0, and it is assumed that the switching period is the switching period plus the non-conducting time. Since the on-time plus the off-time is equal to the switching period, the current in the inductor will not drop to zero, so it is also called the continuous current mode (Continuous Conduction Mode, CCM).

In a switching period T, the switch tube Q1 is turned on during 0-t _on time, and the current passes through the inductor L, the switch tube Q1 and the capacitor C to supply power to the load. At this time, the inductor L is used as an energy storage element. At this time, the node SW voltage V _sw is equal to the input voltage V _in , and the inductor current rises according to a fixed slope, and the slope can be expressed as:

S _on ＝(V _in -V _out )/L (4)

Among them, S _on is the rising slope of the inductor current _IL , V _in and V _out are the input voltage and output voltage respectively, and L is the value of the inductor.

Then, within the time t _on -T, the switch tube Q1 is turned off, the switch tube Q2 is turned on, and the energy stored in the inductor L is released to the load and the capacitor C, and the node SW voltage V _sw is equal to 0 at this time. The current I _L in the inductor L will drop according to a fixed slope, and its slope is:

S _off =V _out /L (5)

In one cycle, the average SW voltage is:

A _sw ＝D*V _in

Wherein, S _off is the falling slope of the inductor current _IL , and As _sw is the average value of the voltage V _sw of the node SW.

Since the voltage V _sw at node SW includes the action of all chopper circuits. The changed value of the inductor current and the output voltage can be expressed as:

${\mathrm{<span\; class="notranslate">\; \&Delta;I</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}}{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; T</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; t</span>}}_{\mathrm{<span\; class="notranslate">\; on</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; )</span>$

V _out = D*V _in (7)

Among them, △ _IL is the change value of the inductor current, T is the switching period, t _on is the time when the switch tube Q1 is turned on, and D is the duty cycle of the switch tube Q1.

The above analysis is based on: the turn-on time plus the turn-off time is the entire switching cycle, assuming that the inductance L in the circuit is relatively small, the output inductor current I _L is relatively small or the switching cycle T is relatively long, when the inductor current When it drops to zero, a new cycle still does not start, this situation is called the inductor current discontinuous mode (Discontinuous Conduction Mod, DCM). At this time, the control signals CLK_PMOS and CLK_NMOS of the switching transistor Q1 and the switching transistor Q2 and the inductor current I _L on the inductor L are shown in FIG. 6 . The change value of the inductor current I _L and the output voltage can be expressed as follows:

${\mathrm{<span\; class="notranslate">\; \&Delta;I</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}}{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; t</span>}}_{\mathrm{<span\; class="notranslate">\; off</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; D.</span>}}{\mathrm{<span\; class="notranslate">\; D.</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; D.</span>}}_{\mathrm{<span\; class="notranslate">\; off</span>}}}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; in</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 9</span>}<span\; class="notranslate">\; )</span>$

Among them, T _off is the off time of the switch.

The output voltage V _{out of} the DC-DC converter with this structure is lower than or equal to the input voltage V _in , so we call it a buck converter.

As shown in FIG. 7 and FIG. 8 , they are respectively: the simulation results of the output voltage V _out and the inductor current _IL when V _in =5V and V _in =3.5V. It can be seen that, in a large input range, the output voltage can maintain a constant output voltage V _out .

As shown in FIG. 9 , with a step input voltage, V _in =3.5V to V _in =6V, the output voltage is still V _out =2.5V, and the ripple is very small, only ten millivolts.

As shown in FIG. 10 , with a step load current, from I _load =0mA to I _load =24mA, the obtained output voltage is still VOUT=2.5V, which shows that the load capacity of the chip is sufficient for the application of medical chips.

As shown in Fig. 11, it is the conversion efficiency curve under different load currents obtained after the step-down converter simulation.

Please refer to FIG. 1 , the connection structure of the step-down converter is as follows: the voltage dividing resistor R5 and the voltage dividing resistor R6 are connected in series with the output DC voltage V _{out of} the conversion circuit 100 , and a part of the output voltage V _fb is fed back to the voltage comparator 100 The inverting input terminal of the bandgap reference BGR is compared with the reference voltage V _ref generated by the bandgap reference BGR, and the output level V _oe1 and the output V _inv signal of the zero-crossing comparator 300 are triggered by RS in an AND gate (AND gate) control circuit The R terminal (clearing terminal) of the device M sets the control signal PFM_P to "0", and after passing through the driving circuit 502, the signal CLK_PMOS is generated to control the switch tube Q1 to turn on. The input terminal of the current detection circuit 600 is connected to the source of the switch tube Q1, the output current I _in + is connected to the positive input terminal of the current comparator 200, and is compared with the reference current I _peak of the negative input terminal to generate a signal V _ie . The output level V _oe1 of the hysteresis comparator (voltage comparator 400) is reversed by the first NOT gate and the signal Vi _ie passes through the OR gate (OR gate), and the S terminal (setting terminal) of the RS flip-flop M in the control circuit ) sets the control signal PFM_P to "1". The positive input terminal of the zero-crossing comparator 300 is connected to the voltage V _sw of the positive terminal of the inductor L, the negative input terminal is grounded to GND, and outputs V _inv . _inv is connected to a NOR gate to generate a signal PFM_N, and the control signal CLK_NMOS of the switch transistor Q2 is generated through the driving circuit 502 . The control signals CLK_PMOS and CLK_NMOS are connected to the gates of the switching transistor Q1 and the switching transistor Q2 respectively. At the same time, when the switching tube Q1 is turned off, the current comparator 200 is not required to perform current comparison, and the current detection circuit 600 is not required to detect the current I _in +. Therefore, the present invention adopts a dynamic shutdown strategy, and the current comparator 200 And the current detection circuit 600 is turned off, thereby reducing unnecessary power loss and improving conversion efficiency. The invention solves the problems of large switching loss of a main switching device, large volume of an additional clock circuit, high cost and low efficiency existing in the existing DC-DC converter. It is very suitable for the application of medical chips.

In addition, the quiescent current of the buck converter is only tens of nanowatts during operation. In addition, the internally generated digital signal is used as the control signal, thereby eliminating the need for additional control modules such as negative delay and one-shot, improving the stability of the circuit, and reducing the complexity of the circuit structure and power consumption. At the same time, the PFM control circuit 500 adopts a dynamic partial shutdown strategy, which effectively reduces system loss and improves efficiency. Therefore, it is suitable for biomedical equipment with low power consumption requirements.

The above-mentioned embodiments only express several implementation modes of the present invention, and the description thereof is relatively specific and detailed, but should not be construed as limiting the patent scope of the present invention. It should be pointed out that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention should be based on the appended claims.

Claims (8)

1. A step-down converter, characterized in that, comprises a conversion circuit, a zero-crossing comparator, a current comparator, a voltage comparator and a PFM control circuit; The conversion circuit includes a switching tube Q1 whose input end is connected to the power supply, a switching tube Q2 whose output end is connected to the output end of the switching tube Q1 and whose input end is grounded, an inductor L connected to the output end of the switching tube Q1 at one end, and A capacitor C connected to the ground at the other end of the inductor L and a resistor R1 connected in parallel to both ends of the capacitor C; The inverting input terminal of the voltage comparator is connected to the node between the inductor L and the capacitor C, the non-inverting input terminal inputs a reference voltage, and the comparison result is input into the PFM control circuit; The non-inverting input terminal of the current comparator is connected to the input terminal of the switching tube Q1, the inverting input terminal inputs the current peak value of the inductor L, and the comparison result is input into the PFM control circuit; The non-inverting input terminal of the zero-crossing comparator is connected to the output terminal of the switching tube Q1, the inverting input terminal is grounded, and the comparison result is input into the PFM control circuit; The PFM control circuit outputs a control signal for controlling the on-off of the switching tube Q1 and the switching tube Q2 according to the comparison results of the voltage comparator, the current comparator, and the zero-crossing comparator; The current comparator includes a positive-phase current mirror module and a reverse-phase current mirror module, wherein, The current I _in input by the positive-phase input terminal of the current comparator is mirrored by the positive-phase current mirror module and the current I _in input by the negative-phase input terminal of the current comparator is mirrored by the negative-phase current mirror module to the same node a; If I _in + is greater than I _in -, the voltage of the node a is pulled up and the output terminal of the current comparator outputs a high level; If I _in + is less than I _in -, the voltage of the node a is pulled down and the output terminal of the current comparator outputs a low level; The positive-phase current mirror module includes a first current mirror and a second current mirror, wherein, The first current mirror includes N-channel MOS transistors NMOS1, MOS transistors NMOS2, MOS transistors NMOS3, MOS transistors NMOS4 and resistor R2, wherein, The drain of the MOS transistor NMOS1 is connected to the current I _in + through the resistor R2, the gate is connected to the gate of the MOS transistor NMOS2, and then the current I _in + is connected, and the source is connected to the drain of the MOS transistor NMOS3, The gate of the MOS transistor NMOS3 is connected to the gate of the MOS transistor NMOS4 and then connected to the drain of the MOS transistor NMOS1, the source is grounded to the source of the MOS transistor NMOS4, and the drain of the MOS transistor NMOS4 is connected to the drain of the MOS transistor NMOS1. The source of the MOS transistor NMOS2 is connected, and the drain of the MOS transistor NMOS2 is connected to the second current mirror; The second current mirror includes a P-channel MOS transistor PMOS1, a MOS transistor PMOS2, a MOS transistor PMOS3, a MOS transistor PMOS4, and a resistor R3, wherein, The source of the MOS transistor PMOS1 is connected to the drain of the MOS transistor NMOS2 through the resistor R3, and the gate is connected to the gate of the MOS transistor PMOS2, and then connected to the drain of the MOS transistor NMOS2, and the drain is connected to the MOS transistor The source of PMOS3 is connected, the gate of the MOS transistor PMOS3 is connected to the gate of the MOS transistor PMOS4 and then connected to the source of the MOS transistor PMOS1, and the drain is connected to the drain of the MOS transistor PMOS4, and the gate of the MOS transistor PMOS4 The source is connected to the drain of the MOS transistor PMOS2, and the source of the MOS transistor PMOS2 outputs a positive-phase mirror current. 2. The step-down converter according to claim 1, wherein the inverting current mirror module comprises N-channel MOS transistors NMOS5, MOS transistors NMOS6, MOS transistors NMOS7, MOS transistors NMOS8 and resistor R4, wherein, The drain of the MOS transistor NMOS5 is connected to the current I _in − through the resistor R4, the gate is connected to the gate of the MOS transistor NMOS6, and the current I _in − is connected to the drain, and the source is connected to the drain of the MOS transistor NMOS7, The gate of the MOS transistor NMOS7 is connected to the gate of the MOS transistor NMOS8 and then connected to the drain of the MOS transistor NMOS5, the source is grounded to the source of the MOS transistor NMOS8, and the drain of the MOS transistor NMOS8 is connected to the drain of the MOS transistor NMOS8. The source of the transistor NMOS6 is connected, and the drain of the MOS transistor NMOS6 outputs an inverse mirror current and the source of the MOS transistor PMOS2 is connected to output a positive mirror current. 3. The step-down converter according to claim 2, wherein the current comparator further comprises a first inverter and a second inverter, wherein, The first inverter includes a P-channel MOS transistor PMOS5 and an N-channel MOS transistor NMOS9, the drain of the MOS transistor PMOS5 is connected to the drain of the MOS transistor PMOS4, and the source is connected to the drain of the MOS transistor NMOS9 , the gate is connected to the gate of the MOS transistor NMOS9 and then connected to the node a; The second inverter includes a P-channel MOS transistor PMOS6 and an N-channel MOS transistor NMOS10, the drain of the MOS transistor PMOS6 is connected to the drain of the MOS transistor PMOS5, and the gate is connected to the gate of the MOS transistor NMOS10 The node b connected to the source of the MOS transistor PMOS5 and the drain of the MOS transistor NMOS10 is the output terminal of the current comparator. 4. The step-down converter according to claim 1, wherein the PFM control module comprises an AND gate, a first NOT gate, a second NOT gate, an OR gate, a NOR gate and an RS flip-flop, wherein, The two input ends of the AND gate are respectively connected with the output end of the voltage comparator and the output end of the zero-crossing comparator, and the output end is connected with the R end of the RS flip-flop, and one input end of the OR gate is passed through the The first NOT gate is connected to the output terminal of the voltage comparator, the other input terminal is connected to the output terminal of the current comparator, the output terminal is connected to the S terminal of the RS flip-flop, and the input of the first NOT gate The terminal is connected with the output terminal of the voltage comparator, and the output terminal is connected with an input terminal of the OR gate; The Q terminal of the RS flip-flop outputs an on-off control signal driven by the drive unit to control the on-off of the switching tube Q1; The Q terminal of the RS flip-flop is connected to an input terminal of the NOR gate through the second NOT gate, and the other input terminal of the NOR gate is connected to the output terminal of the zero-crossing comparator, and the output terminal outputs The on-off control signal is driven by the driving unit to control the on-off of the switching tube Q2. 5 . The step-down converter according to claim 1 , further comprising a current detection circuit, the positive phase input terminal of the current comparator is connected to the input terminal of the switch tube Q1 through the current detection circuit. 6. The step-down converter according to claim 5, wherein the current detection circuit comprises a P-channel MOS transistor PMOS7, a MOS transistor PMOS8 and an amplifier, wherein, The switching tube Q1 is a P-channel power MOS tube, the switching tube Q2 is an N-channel rectifying MOS tube, the MOS tube PMOS7 is connected to the power MOS tube with common drain and common gate, and the source of the MOS tube PMOS7 is It is connected with one input end of the amplifier, the other input end of the amplifier is connected with the drain of the MOS transistor PMOS8 and the source of the power MOS transistor, the output end is connected with the gate of the MOS transistor PMOS8, and the MOS transistor PMOS8 source output sense current. 7. The buck converter according to claim 1, further comprising a bandgap reference, the voltage comparator is a hysteresis comparator, and the bandgap reference is connected to the non-inverting input of the hysteresis comparator . 8. The step-down converter according to claim 7, further comprising a voltage dividing resistor R5 and a voltage dividing resistor R6, the positive phase input terminal of the hysteresis comparator is connected to the A node between the inductor L and the capacitor C is grounded through the voltage dividing resistor R6.