TWI710206B - Boost circuit and electronic device with the boost circuit - Google Patents

Abstract

A booster circuit is used to perform a boost conversion on an input voltage to generate an output voltage at an output end. The booster circuit includes an energy conversion unit and a control signal generating module for controlling the energy conversion unit. The characteristic is That is: when a diode mode signal of the control signal generating module is in an active state and a PWM signal is at a low potential, a voltage clamping module of the energy conversion unit is under the action of a negative feedback loop A clamping voltage is generated according to the input voltage and a fixed voltage difference, and the input voltage and the clamping voltage are coupled to both ends of an inductor of the energy conversion unit.

Description

Boost circuit and electronic device with the boost circuit

The present invention relates to the technical field of DC-DC converter circuits, in particular to a booster circuit that can operate with high efficiency even in the Asynchronous diode mode (Asynchronous diode mode), and an electronic device with the booster circuit .

It is known that switching power conversion circuits have various types, including: Buck, Boost, Inverter, and Buck-Boost. Figure 1 shows the topological structure diagram of a conventional boost type power conversion circuit. As shown in FIG. 1, the conventional step-up power conversion circuit 1'mainly includes: an inductor 11', a first MOS transistor 12', a second MOS transistor 13', an output capacitor 14', A first voltage dividing resistor 15', a second voltage dividing resistor 16', a feedback unit 17', a comparator 18', a control unit 19', a first switch 1A', and a second switch 1B' . It should be understood that the first voltage dividing resistor 15' and the second voltage dividing resistor 16' form a voltage detection unit for detecting an output voltage Vout of the step-up power conversion circuit 1'and corresponding Ground sends a feedback voltage V _FB to the feedback unit 17 ′, so that the control unit 19 ′ generates and transmits a first switch control signal S ₁ and a second switch correspondingly based on an output signal of the feedback unit 17 ′ the control signal S ₂ and a pulse width modulation signal PWM to the a first switch 1A 'and the second switch 1B'.

In more detail, when the step-up power conversion circuit 1'is operated in a boost mode, the first switch 1A' and the second switch 1B' are respectively switched to a short-circuit state and a In the open state, the first MOS transistor 12' and the second MOS transistor 13' are simultaneously controlled by the pulse width modulation signal PWM. In this case, the control unit 19' can adjust the output voltage Vout by changing the duty cycle of the pulse width modulation signal PWM. In more detail, as shown in FIG. 1, in the case of Vin>Vout-Vdif, the output signal cmp_out of the comparator 18' will be 0, prompting the step-up power conversion circuit 1'to operate in the diode mode (Asynchronous diode mode). At this time, the first switch 1A' and the second switch 1B' are respectively switched to an open state and a short-circuit state, so that the gate voltage of the first MOS transistor 12' is equal to Vin. In this case, when the pulse width modulation signal PWM is 0 and the second MOS transistor 13' is turned off, the clamping effect provided by the first MOS transistor 12' will cause the drain of the second MOS transistor 13' The common contact voltage V _SW =V _in +V _th +(I _lin /gm) between the electrode and the drain of the first MOS transistor 12', resulting in the voltage difference across the inductor 11' from the original (V _in- V _out ) is switched to (-V _th -(I _lin /gm)). It is supplemented that V _th and gm are the threshold voltage and equivalent transconductance value of the first MOS transistor 12 ′, respectively, and I _lin is the inductor current.

It can be seen from the above description that after entering the diode mode, the drain-source voltage difference V _{DS of the} first MOS transistor 12' will also change from the original I _lin *Rdson to V _in +V _th +(I _lin /gm)-V _out , where Rdson is the equivalent resistance between the drain and the source. In this case, the power consumption generated by the first MOS transistor 12' is Q=I _lin *V _DS = I _lin *(V _in +V _th +(I _lin /gm)-V _out ). It should be understood that when the output current of the step-up power conversion circuit _1'increases , the inductor current I _lin will also increase, resulting in an increase in the power consumption occurring in the first MOS transistor 12'; The first MOS transistor 12' will heat up and generate heat due to the increase in high consumption, which will adversely affect its working efficiency, and eventually cause the boost power conversion circuit 1'to fail to maintain the same high efficiency operation in the diode mode.

It can be seen from the above description that there is an urgent need for a novel booster circuit in this field.

The main purpose of the present invention is to provide a boost circuit which can maintain high efficiency even if it is operated in the Asynchronous diode mode.

To achieve the above objective, a boost circuit is proposed, which is used to perform a boost conversion on an input voltage to generate an output voltage at an output end, which includes an energy conversion unit and controls the energy conversion unit A control signal generation module, which is characterized in:

When a diode mode signal of the control signal generating module is in an active state and a PWM signal is at a low potential, a voltage clamping module of the energy conversion unit will act on the basis of a negative feedback loop. The input voltage and a fixed voltage difference generate a clamping voltage, and the input voltage and the clamping voltage are coupled to both ends of an inductor of the energy conversion unit.

In order to achieve the above objective, the present invention provides a booster circuit, which includes:

An inductor having a first terminal and a second terminal, and the first terminal is coupled to an input voltage;

A first MOS transistor having a gate terminal, a drain terminal and a source terminal, and the drain terminal is coupled to the second terminal of the inductor;

A second MOS transistor has a gate terminal, a drain terminal and a source terminal, wherein the drain terminal of the second MOS transistor is coupled to the second terminal of the inductor and the first MOS transistor A drain terminal, and the source terminal of the second MOS transistor is coupled to a ground terminal;

An output capacitor, coupled between the source terminal and the ground terminal of the first MOS transistor;

A voltage detecting unit, coupled between the source terminal of the first MOS transistor and the ground terminal, is used to detect an output voltage sent by the source terminal of the first MOS transistor, and provide an output voltage Feedback voltage

A control signal generation module has a first signal input terminal, a second signal input terminal, a third signal input terminal, and a plurality of signal output terminals, wherein the first signal input terminal is coupled to the input voltage, The second signal input terminal is coupled to the output voltage, and the third signal input terminal is coupled to the feedback voltage;

A first switch has an input terminal, an output terminal, and a controlled terminal. The input terminal is coupled to one of the signal output terminals of the control signal generating module to receive a first pulse width modulation signal. The controlled terminal is coupled to a signal output terminal of the control signal generating module to receive a first switch control signal, and the output terminal is coupled to the gate terminal of the first MOS transistor;

A second switch has an input terminal, an output terminal, and a controlled terminal. The controlled terminal is coupled to one of the signal output terminals of the control signal generating module to receive a second switch control signal, and the The output terminal is coupled to the gate terminal of the first MOS transistor; and

A voltage clamping module has a first signal receiving end, a second signal receiving end, a third signal receiving end, and a signal transmitting end; wherein the first signal receiving end is coupled to the first signal receiving end of the inductor Terminal, the second signal receiving terminal is coupled to the second terminal of the inductor, and the third signal receiving terminal is coupled to one of the signal output terminals of the control signal generating module to receive a second pulse width modulation signal, And the signal transmission terminal is coupled to the input terminal of the second switch;

Wherein, the gate terminal of the second MOS transistor is coupled to a signal output terminal of the control signal generating module to receive the first pulse width modulation signal;

Wherein, the voltage clamping module is used to generate a clamping voltage so that a common contact voltage between the drain terminal of the first MOS transistor and the drain terminal of the second MOS transistor is in a diode mode (Asynchronous diode mode) is equal to the sum of the clamping voltage and the input voltage.

In an embodiment, the control signal generation module includes:

A feedback unit having an input terminal and an output terminal, the input terminal serves as the third signal input terminal of the control signal generating module;

A comparator having a negative input terminal, a positive output terminal and an output terminal, the negative input terminal is used as the first signal input terminal of the control signal generating module, and the positive input terminal is used as the control signal generating module The second signal input terminal of; and

A control unit is coupled to the output terminal of the feedback unit and the output terminal of the comparator, and has the plurality of signal output terminals.

In an embodiment, the voltage detection unit includes:

A first voltage divider resistor, one end of which is coupled to the source terminal of the first MOS transistor; and

A second voltage dividing resistor, one end of which is coupled to the other end of the first voltage dividing resistor, and the other end of which is coupled to the ground;

Wherein, a common terminal between the first voltage dividing resistor and the second voltage dividing resistor is coupled to the third signal input terminal of the control signal generating module.

In one embodiment, the first MOS transistor is a P-type MOS transistor, and the second MOS transistor is an N-type MOS transistor.

In one embodiment, the first pulse width modulation signal is inverse to the second pulse width modulation signal.

In an embodiment, the voltage clamping module includes:

An error amplifier having a positive input terminal, a negative input terminal and an output terminal, and the positive input terminal serves as the first signal receiving terminal of the voltage clamping module and is coupled to the first terminal of the inductor;

A capacitor, one end of which is coupled to the negative input terminal of the error amplifier, and the other end of which is coupled to the ground terminal;

A third switch has an input terminal, an output terminal, and a controlled terminal. The output terminal is coupled to the capacitor and the negative input terminal of the error amplifier, and the controlled terminal serves as the voltage clamping module The third signal receiving end further receives the second pulse width modulation signal;

A clamping voltage generating resistor, one end of which is used as the second signal receiving end of the voltage clamping module to be coupled to the second end of the inductor, and the other end is coupled to the input end of the third switch;

A certain current source, coupled between the clamping voltage generating resistor and the ground terminal, wherein the constant current source and the clamping voltage generating resistor are used to generate the clamping voltage at the second terminal of the inductor; and

A buffer having an input terminal and an output terminal, wherein the input terminal of the buffer is coupled to the output terminal of the error amplifier, and the output terminal of the buffer serves as the signal transmission terminal of the voltage clamping module .

In one embodiment, when the input voltage is less than the difference between the output voltage and the clamp voltage, the first switch is switched to a short-circuit state by the first switch control signal, and the second switch is switched by the The second switch control signal is switched to an open state, so that the second MOS transistor and the first MOS transistor are simultaneously controlled by the first pulse width modulation signal.

In one embodiment, when the input voltage is greater than the difference between the output voltage and the clamp voltage, the first switch is switched to an open state by the first switch control signal, and the second switch is switched by the The second switch control signal is switched to a short-circuit state, so that the second MOS transistor is controlled by the first pulse width modulation signal, and the gate terminal of the first MOS transistor is coupled to the voltage clamp mode A gate bias signal provided by the signal transmission end of the group.

The present invention also provides an electronic device, which has the aforementioned booster circuit.

In possible embodiments, the electronic device may be a display device, a smart phone or a portable computer.

In order to enable your reviewer to further understand the structure, features, purpose, and advantages of the present invention, the drawings and detailed descriptions of preferred specific embodiments are attached as follows.

Please refer to FIG. 2, which shows a circuit structure diagram of a boost circuit of the present invention. As shown in Figure 2, the booster circuit 1 of the present invention includes: an inductor 11, a first MOS transistor 12, a second MOS transistor 13, an output capacitor 14, including a first voltage divider 15 and a A voltage detecting unit of the second voltage dividing resistor 16, a control signal generating module SG, a first switch 1A, a second switch 1B, and a voltage clamping module VM. The present invention mainly uses the voltage clamping module VM to generate a fixed voltage difference ΔV. In this way, under the condition that ΔV is less than the threshold voltage Vth of the first MOS transistor 12, even if the boost circuit 1 is operated on a diode In Asynchronous diode mode, the voltage difference V _DS between the drain terminal and the source terminal of the first MOS transistor 12 will not change significantly, so that the power consumption of the first MOS transistor 12 will not enter the diode mode due to the system. The substantial increase allows the boost circuit 1 to maintain high efficiency operation in the diode mode.

According to the design of the present invention, the inductor 11 has a first terminal and a second terminal, and the first terminal is coupled to an input voltage Vin. In addition, the first MOS transistor 12 has a gate terminal, a drain terminal and a source terminal, and the drain terminal is coupled to the second terminal of the inductor 11. On the other hand, the second MOS transistor 13 has a gate terminal, a drain terminal, and a source terminal. The drain terminal of the second MOS transistor 13 is coupled to the second terminal of the inductor 11 and the first terminal. The drain terminal of a MOS transistor 12 and the source terminal of the second MOS transistor 13 are coupled to a ground terminal. As further shown in FIG. 2, the output capacitor 14 is coupled between a source terminal of the first MOS transistor 12 and the ground terminal. Moreover, one end of the first voltage dividing resistor 15 is coupled to the source terminal of the first MOS transistor 12, and two ends of the second voltage dividing resistor 16 are respectively coupled to the other end of the first voltage dividing resistor 15 And the ground terminal, so that the voltage detection unit is coupled between the source terminal of the first MOS transistor 12 and the ground terminal for detecting the output from the source terminal of the first MOS transistor 12 An output voltage Vout of, and a feedback voltage V _{FB is provided} .

In more detail, the control signal generating module SG has a first signal input terminal SG1, a second signal input terminal SG2, a third signal input terminal SG3, and a plurality of signal output terminals; wherein, the first signal The input terminal SG1 is coupled to the input voltage Vin, the second signal input terminal SG2 is coupled to the output voltage Vout, and the third signal input terminal SG3 is coupled to the feedback voltage V _FB . On the other hand, the first switch 1A has an input terminal, an output terminal, and a controlled terminal. The input terminal is coupled to a signal output terminal of the control signal generating module SG to receive a first pulse width. Modulation signal PWM, the controlled terminal is coupled to a signal output terminal of the control signal generating module SG to receive a first switch control signal S ₁ , and the output terminal is coupled to the first MOS transistor 12 One gate extreme. And, it can be seen from FIG. 2 that the second switch 1B has an input terminal, an output terminal, and a controlled terminal, and the controlled terminal is coupled to a signal output terminal of the control signal generating module SG to receive a second The switch control signal S _{2 is} switched, and the output terminal is coupled to the gate terminal of the first MOS transistor 12.

As shown in FIG. 2, the voltage clamping module VM has a first signal receiving terminal VM1, a second signal receiving terminal VM2, a third signal receiving terminal VM3, and a signal transmitting terminal VM4; wherein, the first signal The receiving terminal VM1 is coupled to the first terminal of the inductor 11, the second signal receiving terminal VM2 is coupled to the second terminal of the inductor 11, and the third signal receiving terminal VM3 is coupled to one of the control signal generating module SG The signal output terminal receives a second pulse width modulation signal PWM_bar, and the signal transmission terminal VM4 is coupled to the input terminal of the second switch 1B. Furthermore, FIG. 2 also shows that the gate terminal of the second MOS transistor 13 is coupled to a signal output terminal of the control signal generating module SG to receive the first pulse width modulation signal PWM.

Continue to refer to FIG. 2 and also refer to FIG. 3, which shows the topological structure diagram of the boost circuit of the present invention. According to the design of the present invention, the control signal generating module SG includes: a (voltage) feedback unit 17, a comparator 18, and a control unit 19, wherein the feedback unit 17 has an input terminal and an output terminal, And the input terminal is used as the third signal input terminal SG3 of the control signal generating module SG. It is supplemented that a common terminal between the first voltage dividing resistor 15 and the second voltage dividing resistor 16 is coupled to the third signal input terminal SG3 of the control signal generating module SG for providing all The feedback voltage V _{FB is} sent to the third signal input terminal SG3. On the other hand, the comparator 18 has a negative input terminal, a positive output terminal, and an output terminal. The negative input terminal of the comparator 18 serves as the first signal input terminal SG1 of the control signal generating module SG, And the positive input terminal of the comparator 18 serves as the second signal input terminal SG2 of the control signal generating module SG. It is worth noting that FIG. 3 shows that the control unit 19 is coupled to the output terminal of the feedback unit 17 and the output terminal of the comparator 18, and the control unit 19 has a plurality of signal output terminals of the control signal generating module SG , For providing a first switch control signal S ₁ , a second switch control signal S ₂ , a first pulse width modulation signal PWM, and a second pulse width modulation signal PWM_bar.

As shown in FIGS. 2 and 3, the voltage clamping module VM includes: an error amplifier 1C, a capacitor 1D, a third switch 1E, a clamping voltage generating resistor 1F, a certain current source 1G, and a buffer 1H , Wherein the error amplifier 1C has a positive input terminal, a negative input terminal, and an output terminal, and the positive input terminal serves as the first signal receiving terminal VM1 of the voltage clamping module VM and is further coupled to the first signal receiving terminal VM1 of the inductor 11 One end. On the other hand, the two ends of the capacitor 1D are respectively coupled to the negative input terminal and the ground terminal of the error amplifier 1C; and the third switch 1E has an input terminal, an output terminal, and a controlled terminal. The output terminal is coupled to the capacitor 1D and the negative input terminal of the error amplifier 1C, and the controlled terminal serves as the third signal receiving terminal VM3 of the voltage clamping module VM to receive the second pulse width modulation signal PWM_bar .

Following the above description, one end of the clamping voltage generating resistor 1F serves as the second signal receiving end VM2 of the voltage clamping module VM and is further coupled to the second end of the inductor 11, and the other end thereof is coupled to the third This input of switch 1E. As shown in FIG. 3, the constant current source 1G is coupled between the clamp voltage generating resistor 1F and the ground terminal. In such a configuration, the constant current source 1G and the clamp voltage generating resistor 1F cooperate to generate the fixed voltage difference ΔV at the second end of the inductor 11, so that the drain terminal of the first MOS transistor 12 and the The common junction voltage V _SW between the drain terminals of the second MOS transistor 13 is equal to the sum of the fixed voltage difference ΔV and the input voltage Vin in an Asynchronous diode mode; that is, V _SW =Vin+ΔV. On the other hand, the buffer 1H has an input terminal and an output terminal, wherein the input terminal of the buffer 1H is coupled to the output terminal of the error amplifier 1C, and the output terminal of the buffer 1H serves as the voltage clamp The signal transmission terminal VM4 of the module VM.

Thus, the above description has introduced in detail each circuit unit and detailed topology of the boost circuit 1 of the present invention. Next, the working modes and operating efficiency of the booster circuit 1 of the present invention will be described below in conjunction with related drawings. Please refer to FIGS. 4A and 4B, where FIG. 4A is a topological structure diagram of the boost circuit of the present invention operating in normal mode, and FIG. 4B is a topology of the boost circuit operating of the present invention in diode mode Structure diagram. Also, please refer to FIG. 5, which shows a working timing diagram of the boost circuit of the present invention.

The present invention utilizes the voltage clamping module VM to sample the input voltage Vin, and at the same time, the clamping voltage generating resistor 1F and the constant current source 1G generate a fixed voltage difference ΔV at the second end of the inductor 11. As shown in FIG. 4A, the first MOS transistor 12 is a P-type MOS transistor, and the second MOS transistor 13 is an N-type MOS transistor. When the boost circuit 1 operates in a normal mode (Normal mode or Boost mode), the input voltage Vin will be smaller than the difference between the output voltage Vout and the fixed voltage difference ΔV, that is, Vin<Vout-ΔV. At this time, the first switch control signal 1A from the first switch S ₁ is switched to a short-circuit state (Short-circuit state), and the second switching signal S ₂ 1B switched to the open state of a switch controlled by the second ( Open-circuit state), so that the second MOS transistor 13 and the first MOS transistor 12 are simultaneously controlled by the first pulse width modulation signal PWM.

It is added that since the first pulse width modulation signal PWM is inverse to the second pulse width modulation signal PWM_bar, the control unit 19 can change the duty cycle of the first pulse width modulation signal PWM ( Duty cycle) to achieve regulation of the output voltage Vout. The label "Q1_gate" in FIG. 5 refers to the signal transmitted to the gate terminal of the first MOS transistor 12 through the first switch 1A. It can be found that in the normal mode, the signal Q1_gate is the same as the first pulse width modulation signal PWM, and the drain terminal voltage V _{SW of the} second MOS transistor 13 does not increase suddenly.

Please refer to FIG. 4B, which is a topological structure diagram of the boost circuit of the present invention operating in the diode mode. As shown in FIG. 4B, when the boost circuit 1 is operating in the Asynchronous diode mode, the input voltage Vin will be greater than the difference between the output voltage Vout and the fixed voltage difference ΔV, that is, Vin> Vout-ΔV. At this time, the first switch 1A ₁ switching to an open state (Open-circuit state) by the control signal S to the first switch and the second switch 1B switching signal S ₂ to a short-circuit state is controlled by the second switch ( Short-circuit state), so that the second MOS transistor 13 is controlled by the first pulse width modulation signal PWM, and the gate terminal of the first MOS transistor 12 is coupled to the voltage clamping module VM The signal transmission terminal VM4 provides a gate bias signal. As shown in FIG. 5 and FIG. 4B, after entering the diode mode, the drain terminal voltage V _{SW of the} second MOS transistor 13 can be observed to increase suddenly; at this time, due to the positive input terminal and the negative input terminal of the error amplifier 1C The virtual short between the two causes the common contact voltage V _SW between the drain terminal of the first MOS transistor 12 and the drain terminal of the second MOS transistor 13 (that is, the drain terminal Voltage) in the diode mode is equal to the sum of the fixed voltage difference ΔV and the input voltage Vin, V _SW =Vin+ΔV. It is easy to understand that as long as ΔV is adjusted to a very small value, V _SW can approach Vin. Preferably, the value of ΔV is smaller than the threshold voltage (Vth) of the first MOS transistor 12. Simply put, as long as ΔV<Vth is ensured, the efficiency of the boost circuit 1 of the present invention under various load conditions is better than the conventional boost power conversion circuit 1'(as shown in FIG. 1).

FIG. 6 is a comparison diagram of output current-efficiency curves of the boost circuit of the present invention and the conventional boost power conversion circuit. From the data in FIG. 6, it can be easily found that as the output current gradually increases, the efficiency of the conventional boost power conversion circuit 1'(as shown in FIG. 1) is continuously decreasing. It is worth noting that the voltage clamping module VM is added to the boost circuit 1 of the present invention. Therefore, even if the output current is gradually increased in response to various load conditions, the efficiency of the boost circuit 1 of the present invention remains At the normal level, there is no significant decline.

Based on the above description, the present invention further provides an electronic device. Please refer to FIG. 7, which shows a block diagram of an embodiment of the electronic device of the present invention. As shown in FIG. 7, an electronic device 100 includes a boost circuit 110 (implemented by the boost circuit 1 of FIG. 2) and an information processing circuit 120 powered by the boost circuit 110. The electronic device 100 may be a display Device, a smart phone or a portable computer.

In this way, the above has completely and clearly explained the technical solution of the boost circuit of the present invention; and from the above, it can be seen that the present invention has the following advantages:

(1) The boost circuit of the present invention can still maintain high efficiency operation in the diode mode.

(2) The electronic device of the present invention can have a longer operating time because its booster circuit still maintains a high-efficiency operation in the diode mode.

It must be emphasized that the foregoing disclosures in this case are preferred embodiments, and any partial changes or modifications that are derived from the technical ideas of this case and are easily inferred by those who are familiar with the art will not deviate from the patent of this case. Right category.

In summary, regardless of the purpose, means and effects of this case, it is shown that it is very different from the conventional technology, and its first invention is suitable for practicality, and it does meet the patent requirements of the invention. Please check it out and grant the patent as soon as possible. Society is for the best prayer.

<The present invention>

1: Boost circuit

11: Inductance

12: The first MOS transistor

13: The second MOS transistor

14: output capacitor

15: The first voltage divider resistor

16: second voltage divider resistor

17: Feedback unit

18: Comparator

19: Control unit

1A: First switch

1B: Second switch

1C: Error amplifier

1D: Capacitance

1E: third switch

1F: Clamping voltage generates resistance

1G: constant current source

1H: Buffer

SG: control signal generation module

VM: Voltage clamp module

SG1: The first signal input terminal

SG2: The second signal input terminal

SG3: The third signal input terminal

VM1: The first signal receiving end

VM2: The second signal receiving end

VM3: The third signal receiver

VM4: Signal transmission terminal

100: electronic device

110: Boost circuit

120: Information Processing Circuit

＜Actually knowledge＞

1’: Step-up power conversion circuit

11’: Inductance

12’: The first MOS transistor

13’: The second MOS transistor

14’: Output capacitor

15’: The first voltage divider resistor

16’: Second voltage divider resistor

17’: Feedback unit

18’: Comparator

19’: Comparator

1A’: First switch

1B’: Second switch

Figure 1 is a topological structure diagram of a conventional boost type power conversion circuit; 2 is a circuit structure diagram of the boost circuit of the present invention; Figure 3 is a topological structure diagram of the boost circuit of the present invention; 4A is a topological structure diagram of the boost circuit of the present invention operating in normal mode; 4B is a topological structure diagram of the boost circuit of the present invention operating in the diode mode; Figure 5 is a working timing diagram of the boost circuit of the present invention; Fig. 6 is a comparison diagram of output current-efficiency curves between the boost circuit of the present invention and the conventional boost power conversion circuit; and FIG. 7 is a block diagram of an embodiment of the electronic device of the present invention.

1: Boost circuit

11: Inductance

12: The first MOS transistor

13: The second MOS transistor

14: output capacitor

15: The first voltage divider resistor

16: second voltage divider resistor

1A: First switch

1B: Second switch

SG: control signal generation module

VM: Voltage clamp module

SG1: The first signal input terminal

SG2: The second signal input terminal

SG3: The third signal input terminal

VM1: The first signal receiving end

VM2: The second signal receiving end

VM3: The third signal receiver

VM4: Signal transmission terminal

Claims (9)

A boost circuit includes: an inductor having a first terminal and a second terminal, and the first terminal is coupled to an input voltage; a first MOS transistor having a gate terminal, a drain terminal, and a source Terminal, and the drain terminal is coupled to the second terminal of the inductor; a second MOS transistor has a gate terminal, a drain terminal and a source terminal, wherein the drain terminal of the second MOS transistor is coupled The second terminal of the inductor and the drain terminal of the first MOS transistor, and the source terminal of the second MOS transistor is coupled to a ground terminal; an output capacitor is coupled to the first MOS transistor Between a source terminal of the crystal and the ground terminal; a voltage detection unit, coupled between the source terminal of the first MOS transistor and the ground terminal, for detecting the output of the first MOS transistor An output voltage sent by the source terminal and a feedback voltage is provided; a control signal generation module has a first signal input terminal, a second signal input terminal, a third signal input terminal, and a plurality of signal outputs Terminal, wherein the first signal input terminal is coupled to the input voltage, the second signal input terminal is coupled to the output voltage, and the first signal input terminal is coupled to the feedback voltage; a first switch having an input Terminal, an output terminal, and a controlled terminal, the input terminal is coupled to one of the signal output terminals of the control signal generating module to receive a first pulse width modulation signal, and the controlled terminal is coupled to the control signal A said signal output terminal of the generating module is used to receive a first switch control signal, and the output terminal is coupled to the gate terminal of the first MOS transistor; a second switch has an input terminal, an output terminal, And a controlled terminal, the controlled terminal is coupled to a signal output terminal of the control signal generating module to receive a second switch control signal, and the output terminal is coupled to the gate terminal of the first MOS transistor And a voltage clamping module having a first signal receiving end, a second signal receiving end, a third signal receiving end, and a signal transmitting end; wherein the first signal receiving end is coupled to the inductor The first end, the second signal receiving end is coupled to the second end of the inductor, and the third signal receiving end is coupled to the control signal A said signal output terminal of the generating module receives a second pulse width modulation signal, and the signal transmission terminal is coupled to the input terminal of the second switch; wherein, the gate terminal of the second MOS transistor is coupled One of the signal output terminals of the control signal generating module is connected to receive the first pulse width modulation signal; wherein, the voltage clamping module is used to generate a fixed voltage difference, the fixed voltage difference being smaller than the first MOS The threshold voltage of the transistor is such that the common contact voltage between the drain terminal of the first MOS transistor and the drain terminal of the second MOS transistor is equal to the fixed voltage difference and the The sum of input voltages, where the diode mode refers to the operating mode of the control signal generating module when the input voltage is greater than the difference between the output voltage and the fixed voltage difference. In the diode mode, The first switch is switched to an open state by the first switch control signal, and the second switch is switched to a short-circuit state by the second switch control signal, so that the second MOS transistor is controlled by the first switch A pulse width modulated signal, and the gate terminal of the first MOS transistor is coupled to a gate bias signal provided by the signal transmission terminal of the voltage clamping module. For the boost circuit described in item 1 of the scope of patent application, the control signal generating module includes: a feedback unit having an input terminal and an output terminal, and the input terminal is used as the control signal generating module The third signal input terminal; a comparator having a negative input terminal, a positive output terminal and an output terminal, the negative input terminal is used as the first signal input terminal of the control signal generation module, and the positive input terminal The second signal input terminal as the control signal generating module; and a control unit, coupled to the output terminal of the feedback unit and the output terminal of the comparator, and has the plurality of signal output terminals. According to the boost circuit described in claim 1, wherein the voltage detection unit includes: a first voltage dividing resistor, one end of which is coupled to the source terminal of the first MOS transistor; and a second dividing resistor A voltage resistor, one end of which is coupled to the other end of the first voltage dividing resistor, and the other end of which is coupled to the ground; Wherein, a common terminal between the first voltage dividing resistor and the second voltage dividing resistor is coupled to the third signal input terminal of the control signal generating module. In the boost circuit described in claim 1, wherein the first MOS transistor is a P-type MOS transistor, and the second MOS transistor is an N-type MOS transistor. According to the booster circuit described in claim 1, wherein the first pulse width modulation signal is inverse to the second pulse width modulation signal. As described in the first item of the scope of patent application, the voltage clamping module includes: an error amplifier having a positive input terminal, a negative input terminal and an output terminal, and the positive input terminal is used as the voltage The first signal receiving end of the clamping module is further coupled to the first end of the inductor; a capacitor, one end of which is coupled to the negative input end of the error amplifier, and the other end of which is coupled to the ground end; a third The switch has an input terminal, an output terminal, and a controlled terminal. The output terminal is coupled to the capacitor and the negative input terminal of the error amplifier, and the controlled terminal serves as the third signal of the voltage clamping module The receiving end further receives the second pulse width modulation signal; a clamping voltage generating resistor, one end of which is used as the second signal receiving end of the voltage clamping module and then coupled to the second end of the inductor, and the other One end is coupled to the input terminal of the third switch; a certain current source is coupled between the clamp voltage generating resistor and the ground terminal, wherein the constant current source and the clamp voltage generating resistor are used to generate the A fixed voltage difference from the second terminal of the inductor; and a buffer having an input terminal and an output terminal, wherein the input terminal of the buffer is coupled to the output terminal of the error amplifier, and the buffer The output terminal serves as the signal transmission terminal of the voltage clamping module. The boost circuit described in item 1 of the scope of patent application, wherein, when the input voltage is less than the difference between the output voltage and the fixed voltage difference, the first switch is switched by the first switch control signal to a In a short-circuit state, and the second switch is switched to an open state by the second switch control signal, so that the second MOS transistor and the first MOS transistor are simultaneously controlled by the first pulse width modulation signal. A boost circuit for boosting an input voltage to an output terminal Generates an output voltage, which includes an energy conversion unit and a control signal generation module for controlling the energy conversion unit. The energy conversion unit has an inductor, a first MOS transistor, and a second MOS transistor. The second MOS transistor system is used to control the charging of the input voltage to the inductor, and the first MOS transistor system is used to control the discharge of the inductor to the output terminal, and is characterized in that: the control signal generating module has a normal Mode and a diode mode and are used to output a PWM signal or a PWM signal and a gate bias signal, wherein the normal mode means that the control signal generating module is when the input voltage is less than the output voltage and a The working mode in the case of a fixed voltage difference difference, and when the control signal generating module works in the normal mode, it outputs the PWM signal to control the first MOS transistor and the second MOS transistor; The diode mode refers to the operating mode of the control signal generating module when the input voltage is greater than the difference between the output voltage and the fixed voltage difference, and when the control signal generating module works on the diode In the mode, it outputs the gate bias signal to control the first MOS transistor and the PWM signal to control the second MOS transistor; and when the control signal generating module works in the diode mode, A voltage clamping module of the energy conversion unit generates a clamping voltage according to the input voltage and the fixed voltage difference under the action of a negative feedback loop, and the input voltage and the clamping voltage are coupled to the inductor Both ends, wherein the fixed voltage difference is less than the threshold voltage of the first MOS transistor. An electronic device having a booster circuit as described in any one of items 1 to 8 of the scope of patent application and an information processing circuit powered by the booster circuit, wherein the electronic device is a display device, a A smart phone or a portable computer.

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