CN111736686B - Protection circuit and server of SCC circuit are opened unusually - Google Patents

Protection circuit and server of SCC circuit are opened unusually Download PDF

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CN111736686B
CN111736686B CN202010538000.2A CN202010538000A CN111736686B CN 111736686 B CN111736686 B CN 111736686B CN 202010538000 A CN202010538000 A CN 202010538000A CN 111736686 B CN111736686 B CN 111736686B
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mos tube
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resistor
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CN111736686A (en
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杨舜量
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Suzhou Inspur Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention discloses a protection circuit and a server for abnormally starting an SCC circuit, wherein the protection circuit comprises the following components: the drain electrode of the first MOS tube is connected with the anode of the input voltage; a second MOS transistor; the two ends of the first capacitor are respectively connected with the source electrode of the first MOS tube and the source electrode of the second MOS tube; two ends of the second capacitor are respectively connected with the drain electrode of the second MOS tube and the negative electrode of the input voltage; the output end of the first pulse width modulation signal generator is connected with the grid electrode of the first MOS tube and the grid electrode of the second MOS tube; the input end of the diode is connected with the output end of the first pulse width modulation signal generator; and the input end of the comparator unit is connected with the output voltage, and the output end of the comparator unit is connected with the output end of the diode. The scheme provided by the invention obtains the safe voltage at the moment of starting the circuit through Laplace transformation, and detects the output voltage based on the safe voltage.

Description

Protection circuit and server of SCC circuit are opened unusually
Technical Field
The present invention relates to the field of circuits, and more particularly, to a protection circuit for an SCC circuit that is turned on abnormally and a server.
Background
With the greatly increased demands of enterprises and individuals on cloud services, power consumption is also greatly increased. At present, a general server power supply architecture is powered by a 12V power supply, and then, based on the 12V power supply, the Buck voltage reduction circuit is used to respectively provide power supplies for elements such as 5V, 3.3V and 1.8V. However, since AC (Alternating Current) supplies power to 12V and then to a CPU or other high-energy-consumption processor, the power conversion efficiency only reaches 89%. After the advent of new 48V server power architectures, the power conversion efficiency from AC to 48V to CPU can reach 92%. The conversion efficiency between these 3% will differ significantly as the power consumption increases.
Many voltage reduction modes are developed under the DCDC 48V power supply architecture, and the general Buck and LLC concept are also introduced. In a design environment with extremely high server density, another SCC is quite suitable for small-area applications. Its advantages are high boosting or reducing voltage by charging or discharging capacitor, and no need of magnetic element or inductor. However, in the prior art, various phenomena of the SCC under transient response and changes between current and voltage are not analyzed, and components in the SCC circuit cannot be protected.
Disclosure of Invention
In view of the above, an object of the embodiments of the present invention is to provide a protection circuit and a server for an SCC circuit that is turned on abnormally, wherein the change between current and voltage is obtained by analyzing the polarity of the SCC circuit operating mode in the time domain and the frequency domain through laplace transformation, so as to obtain a safe voltage at the instant of turning on the circuit, and the protection circuit detects the output voltage based on the safe voltage and protects the SCC circuit when the output voltage is abnormal.
In view of the above, an aspect of the embodiments of the present invention provides a protection circuit for abnormally opening an SCC circuit, which includes the following components: the drain electrode of the first MOS tube is connected with the positive electrode of the input voltage; a second MOS transistor; the two ends of the first capacitor are respectively connected with the source electrode of the first MOS tube and the source electrode of the second MOS tube; the two ends of the second capacitor are respectively connected with the drain electrode of the second MOS tube and the negative electrode of the input voltage; the output end of the first pulse width modulation signal generator is connected with the grid electrode of the first MOS tube and the grid electrode of the second MOS tube; the input end of the diode is connected with the output end of the first pulse width modulation signal generator; and the input end of the comparator unit is connected with the output voltage, and the output end of the comparator unit is connected with the output end of the diode.
In some embodiments, further comprising: and the drain electrode of the third MOS tube is connected with the source electrode of the first MOS tube, and the source electrode of the third MOS tube is connected with the drain electrode of the second MOS tube.
In some embodiments, further comprising: and the drain electrode of the fourth MOS tube is connected with the source electrode of the second MOS tube, and the source electrode of the fourth MOS tube is connected with the negative electrode of the input voltage.
In some embodiments, further comprising: and the output end of the second pulse width modulation signal generator is connected with the grid electrode of the third MOS tube and the grid electrode of the fourth MOS tube.
In some embodiments, the comparator unit comprises: one end of the first resistor is connected with the output voltage; one end of the second resistor is connected with the other end of the first resistor, and the other end of the second resistor is grounded; and a negative input end of the comparator is connected with the other end of the first resistor, a positive input end of the comparator is connected with a reference voltage, and an output end of the comparator is connected with an output end of the diode.
In another aspect of the embodiments of the present invention, there is also provided a server, including a protection circuit, where the protection circuit includes: the drain electrode of the first MOS tube is connected with the positive electrode of the input voltage; a second MOS transistor; the two ends of the first capacitor are respectively connected with the source electrode of the first MOS tube and the source electrode of the second MOS tube; the two ends of the second capacitor are respectively connected with the drain electrode of the second MOS tube and the negative electrode of the input voltage; the output end of the first pulse width modulation signal generator is connected with the grid electrode of the first MOS tube and the grid electrode of the second MOS tube; the input end of the diode is connected with the output end of the first pulse width modulation signal generator; and the input end of the comparator unit is connected with the output voltage, and the output end of the comparator unit is connected with the output end of the diode.
In some embodiments, further comprising: and the drain electrode of the third MOS tube is connected with the source electrode of the first MOS tube, and the source electrode of the third MOS tube is connected with the drain electrode of the second MOS tube.
In some embodiments, further comprising: and the drain electrode of the fourth MOS tube is connected with the source electrode of the second MOS tube, and the source electrode of the fourth MOS tube is connected with the negative electrode of the input voltage.
In some embodiments, further comprising: and the output end of the second pulse width modulation signal generator is connected with the grid electrode of the third MOS tube and the grid electrode of the fourth MOS tube.
In some embodiments, the comparator unit comprises: one end of the first resistor is connected with the output voltage; one end of the second resistor is connected with the other end of the first resistor, and the other end of the second resistor is grounded; and a negative input end of the comparator is connected with the other end of the first resistor, a positive input end of the comparator is connected with a reference voltage, and an output end of the comparator is connected with an output end of the diode.
The invention has the following beneficial technical effects: through Laplace conversion, the working mode of the SCC circuit is analyzed in time domain and frequency domain polarity respectively to obtain the change between current and voltage, so that the safe voltage at the moment of circuit starting is obtained, the output voltage is detected based on the change, and meanwhile, protection is carried out when the output voltage is abnormal.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a schematic diagram of a SCC circuit in the prior art;
FIG. 2 is a schematic diagram of a charging state of an SCC circuit;
FIG. 3 is a schematic diagram of a discharging state of an SCC circuit;
fig. 4 is a schematic diagram of an embodiment of a protection circuit for an abnormal turn-on SCC circuit according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In view of the above, a first aspect of the embodiments of the present invention provides an embodiment of a protection circuit for abnormally opening an SCC circuit. Fig. 1 is a schematic diagram of a SCC (capacitive Switching Converter) circuit in the prior art. As shown in fig. 1, the prior art includes 4 MOS transistors and two capacitors, two ends of the capacitor Cfly are respectively connected to the source of the MOS transistor Q1 and the source of the MOS transistor Q3, and two ends of the capacitor Co are respectively connected to the source of the MOS transistor Q2 and the source of the MOS transistor Q4.
The SCC circuit is divided into a Cfly charging stage and a Cfly discharging stage for analysis, the input current charges Cfly and Co in the period (Ton) from 0 to T1, at the moment, Q1 and Q3 are switched on, and Q2 and Q4 are switched off; during the time period (Toff) from T1 to T2, cfly charges Co, i.e., cfly discharges, while Q1 and Q3 are off and Q2 and Q4 are on.
Fig. 2 is a schematic diagram of the charging state of the SCC circuit. Converting the charged Time domain (Time domain) of FIG. 2 into S domain (frequency domain), deriving I (S) from the KCL current equation, and deriving the voltages of CFLY and Co from I (S).
R S1 ＝Q 1- R ds(on) +Q 3- R ds(on)
Figure BDA0002537739210000051
Figure BDA0002537739210000052
Figure BDA0002537739210000053
Figure BDA0002537739210000054
Obtaining by inverse Laplace transform:
Figure BDA0002537739210000055
Figure BDA0002537739210000056
/>
Figure BDA0002537739210000057
FIG. 3 is a schematic diagram of a discharging state of an SCC circuit. Converting the discharge Time domain of FIG. 3 into Sdomain, deriving I(s) from the KCL current equation, and deriving the voltages of CFLY and Co from I(s).
R S2 ＝Q 2- R ds(on) +Q 4- R ds(on)
Figure BDA0002537739210000058
Figure BDA0002537739210000061
Figure BDA0002537739210000062
Figure BDA0002537739210000063
Obtaining by inverse Laplace transform:
Figure BDA0002537739210000064
Figure BDA0002537739210000065
Figure BDA0002537739210000066
from the conclusion of the above equations, it can be concluded that the derived equations for charging and discharging are continuously related to time Ton/Toff, and that:
Figure BDA0002537739210000067
/>
Figure BDA0002537739210000068
in the above formula,. Mu. (t) Representing unit step function, V in Which is representative of the input voltage of the power supply,
Figure BDA0002537739210000069
represents the state of the voltage across the capacitor Cfly at the last Toff>
Figure BDA00025377392100000610
Representing the state of the voltage across the capacitor Co over the last Toff,
Figure BDA0002537739210000071
represents the state of the voltage across the capacitor Cfly at the last Ton>
Figure BDA0002537739210000072
Indicating the state of the voltage across the capacitor Co at the last Ton, R S1 Represents the value of RDS (ON) of Q1 and Q3 added together, R S2 Represents the value of RDS (ON) of Q2 and Q4, RDS (ON) represents the ON-resistance of the MOSFET, C T Representing the parallel value of Cfly and Co capacitance.
The charge-discharge formula is substituted by Cfly =50 μ F, co =500 μ F, vin =54v, fsw =100khz, duty =50%, and RDS (ON) =0.02 Ω, so that it can be obtained that when Q1 and Q3 are turned ON for the first time, the voltage at both ends of Cfly is charged to about 50V, and the output voltage Vo is only about 5V due to the divided voltage of Cfly and Co, so that Cfly needs an element with a rated voltage twice the input voltage, and Co needs an element with a rated voltage equal to the input voltage to ensure that the element is not burned at the moment of power supply turning ON. The faster the switching frequency Fsw, the faster the circuit will step down.
If the ratio of Cfly to Co is opposite, that is, cfly =500 μ F, co =50 μ F, vin =54v, fsw =100khz, duty =50%, and RDS (ON) =0.02 Ω are substituted into the above charging and discharging formula, it can be obtained that when Q1 and Q3 are turned ON for the first time, because Cfly and Co are not matched, the output voltage Vo will generate a surge close to the input voltage, which will destroy Co and any components at the rear end that cannot bear the input voltage, therefore, the present application designs a protection circuit based ON the protection of the components.
Fig. 4 is a schematic diagram illustrating an embodiment of a protection circuit for abnormally-turned on SCC circuitry according to the present invention. As shown in fig. 4, the protection circuit includes: the circuit comprises a first MOS tube Q1, a second MOS tube Q3, a first capacitor Cfly, a second capacitor Co, a first pulse width modulation signal generator PWM1, a Diode and a comparator unit.
The drain electrode of the first MOS tube Q1 is connected with the positive electrode of the input voltage, the source electrode of the first MOS tube Q1 is connected with the first end of the first capacitor Cfly, and the grid electrode of the first MOS tube Q1 is connected with the first pulse width modulation signal generator PWM 1. The grid electrode of the second MOS tube Q3 is connected with the first pulse width modulation signal generator PWM1, the source electrode of the second MOS tube Q3 is connected with the second end of the first capacitor Cfly, and the drain electrode of the second MOS tube Q3 is connected with the second capacitor Co. The input end of the Diode is connected with the output end of the first pulse width modulation signal generator PWM1, the output end of the Diode is connected with the output end of the comparator unit, and the input end of the comparator unit is connected with the output voltage.
With continued reference to fig. 4, when PWM1 turns on Q1 and Q3, the output voltage Vo goes high close to the input voltage Vin. At this time, the output voltage needs to be detected by the comparator unit, when the output voltage is greater than half of the Vin voltage (the input voltage is 54V, half is 27V), it is determined that the output voltage is abnormal, and the negative terminal of the comparator is higher than the positive terminal, and the comparator outputs a low level. Because the comparator outputs low level, the voltage output by the PWM1 is higher than the voltage output by the comparator, therefore, the PWM1 directly pulls down signals through the Diode, and then closes the Q1 and the Q3 to avoid the burning of the components at the output end, thereby playing the role of protecting circuit elements.
In some embodiments, further comprising: and the drain electrode of the third MOS tube Q2 is connected with the source electrode of the first MOS tube Q1, and the source electrode of the third MOS tube Q2 is connected with the drain electrode of the second MOS tube Q3.
In some embodiments, further comprising: and the drain electrode of the fourth MOS tube Q4 is connected with the source electrode of the second MOS tube Q3, and the source electrode of the fourth MOS tube Q4 is connected with the negative electrode of the input voltage.
In some embodiments, further comprising: and the output end of the second pulse width modulation signal generator PWM2 is connected with the grid electrode of the third MOS tube Q2 and the grid electrode of the fourth MOS tube Q4.
In some embodiments, the comparator unit comprises: one end of the first resistor R1 is connected with the output voltage; one end of the second resistor R2 is connected with the other end of the first resistor R1, and the other end of the second resistor R2 is grounded; and a negative input end of the comparator is connected with the other end of the first resistor R1, a positive input end of the comparator is connected with a reference voltage, and an output end of the comparator is connected with an output end of the diode.
The voltage across the second capacitor Co is equal to the output voltage, and the voltage across the first resistor R1 and the second resistor R2 is also equal to the output voltage, and assuming that the output voltage is equal to 28V, it is determined that the abnormality is abnormal, if the reference voltage is known to be 1.5V and R2=10k Ω, R1=176.66K Ω may be obtained according to the formula R1= R2 (Vo/VREF-1).
In view of the above object, according to a second aspect of the embodiments of the present invention, there is provided a server, including a protection circuit, the protection circuit including: the drain electrode of the first MOS tube is connected with the positive electrode of the input voltage; a second MOS transistor; the two ends of the first capacitor are respectively connected with the source electrode of the first MOS tube and the source electrode of the second MOS tube; the two ends of the second capacitor are respectively connected with the drain electrode of the second MOS tube and the negative electrode of the input voltage; the output end of the first pulse width modulation signal generator is connected with the grid electrode of the first MOS tube and the grid electrode of the second MOS tube; the input end of the diode is connected with the output end of the first pulse width modulation signal generator; and the input end of the comparator unit is connected with the output voltage, and the output end of the comparator unit is connected with the output end of the diode.
In some embodiments, further comprising: and the drain electrode of the third MOS tube is connected with the source electrode of the first MOS tube, and the source electrode of the third MOS tube is connected with the drain electrode of the second MOS tube.
In some embodiments, further comprising: and the drain electrode of the fourth MOS tube is connected with the source electrode of the second MOS tube, and the source electrode of the fourth MOS tube is connected with the negative electrode of the input voltage.
In some embodiments, further comprising: and the output end of the second pulse width modulation signal generator is connected with the grid electrode of the third MOS tube and the grid electrode of the fourth MOS tube.
In some embodiments, the comparator unit comprises: one end of the first resistor is connected with the output voltage; one end of the second resistor is connected with the other end of the first resistor, and the other end of the second resistor is grounded; and a negative input end of the comparator is connected with the other end of the first resistor, a positive input end of the comparator is connected with a reference voltage, and an output end of the comparator is connected with an output end of the diode.
It should be noted that the above description and extension of the protection circuit can be applied to the server, and for the sake of brevity of the technical solution of the present application, no further description is given here.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements and the like that may be made without departing from the spirit or scope of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims (4)

1. A protection circuit for an abnormal turn-on SCC circuit, comprising:
the drain electrode of the first MOS tube is connected with the anode of the input voltage;
a second MOS transistor;
the two ends of the first capacitor are respectively connected with the source electrode of the first MOS tube and the source electrode of the second MOS tube;
the two ends of the second capacitor are respectively connected with the drain electrode of the second MOS tube and the negative electrode of the input voltage;
the output end of the first pulse width modulation signal generator is connected with the grid electrode of the first MOS tube and the grid electrode of the second MOS tube;
the input end of the diode is connected with the output end of the first pulse width modulation signal generator;
the input end of the comparator unit is connected with the output voltage, and the output end of the comparator unit is connected with the output end of the diode;
the drain electrode of the third MOS tube is connected with the source electrode of the first MOS tube, and the source electrode of the third MOS tube is connected with the drain electrode of the second MOS tube;
a drain electrode of the fourth MOS tube is connected with a source electrode of the second MOS tube, and a source electrode of the fourth MOS tube is connected with a negative electrode of the input voltage;
and the output end of the second pulse width modulation signal generator is connected with the grid electrode of the third MOS tube and the grid electrode of the fourth MOS tube.
2. The protection circuit of claim 1, wherein the comparator unit comprises:
one end of the first resistor is connected with the output voltage;
one end of the second resistor is connected with the other end of the first resistor, and the other end of the second resistor is grounded; and
and the negative input end of the comparator is connected with the other end of the first resistor, the positive input end of the comparator is connected with a reference voltage, and the output end of the comparator is connected with the output end of the diode.
3. A server, comprising a protection circuit, the protection circuit comprising:
the drain electrode of the first MOS tube is connected with the positive electrode of the input voltage;
a second MOS transistor;
the two ends of the first capacitor are respectively connected with the source electrode of the first MOS tube and the source electrode of the second MOS tube;
the two ends of the second capacitor are respectively connected with the drain electrode of the second MOS tube and the negative electrode of the input voltage;
the output end of the first pulse width modulation signal generator is connected with the grid electrode of the first MOS tube and the grid electrode of the second MOS tube;
the input end of the diode is connected with the output end of the first pulse width modulation signal generator; and
the input end of the comparator unit is connected with the output voltage, and the output end of the comparator unit is connected with the output end of the diode;
the drain electrode of the third MOS tube is connected with the source electrode of the first MOS tube, and the source electrode of the third MOS tube is connected with the drain electrode of the second MOS tube;
a drain electrode of the fourth MOS tube is connected with a source electrode of the second MOS tube, and a source electrode of the fourth MOS tube is connected with a negative electrode of the input voltage;
and the output end of the second pulse width modulation signal generator is connected with the grid electrode of the third MOS tube and the grid electrode of the fourth MOS tube.
4. The server according to claim 3, wherein the comparator unit comprises:
one end of the first resistor is connected with the output voltage;
one end of the second resistor is connected with the other end of the first resistor, and the other end of the second resistor is grounded; and
and the negative input end of the comparator is connected with the other end of the first resistor, the positive input end of the comparator is connected with a reference voltage, and the output end of the comparator is connected with the output end of the diode.
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