JP3757219B2 - Charge pump circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a charge pump type DC-DC converter circuit, and relates to a technique for obtaining an output voltage of an arbitrary magnitude that is not limited to an integral multiple of a power supply voltage.
[0002]
[Prior art]
When the power supply voltage supplied from the outside is lower than the drive voltage required by the IC or the element, a booster circuit is provided in the preceding stage. As this step-up circuit, there is a charge pump circuit using a plurality of capacitors in addition to a step-up chopper type regulator using an inductance or a transformer. Among these, the charge pump circuit is also called a switched capacitor circuit or the like in some cases, and is widely used for a power supply circuit for a MOS-IC or the like.
FIG. 3 shows a basic configuration of the charge pump circuit.
[0003]
In FIG. 3, 1 is a power supply input terminal connected to an external power supply, 2 is a voltage output terminal connected to a load, and C1 is a boosting capacitor. A first switch S1 is connected between one end of the capacitor C1 and the power supply input terminal 1, and a second switch S2 is connected between the other end of the capacitor C1 and the ground. A third switch S3 is connected between one end of the capacitor C1 and the voltage output terminal 2, and a fourth switch S4 is connected between the other end of the capacitor C1 and the power input terminal 1. A smoothing capacitor C2 is connected between the voltage output terminal 2 and the ground. The first and second switches S1 and S2 are supplied with the first clock signal <CK1>, and the third and fourth switches S3 and S4 are supplied with the second clock signal <CK2>. An oscillation circuit 3 is provided.
[0004]
The charge pump converter having such a configuration generates an output voltage VOUT higher than the power supply voltage VDD by the following operation.
As shown in the timing chart of FIG. 4, when the first clock signal <CK1> output from the oscillation circuit 3 becomes high level at time t1, the switches S1 and S2 are turned on accordingly. Then, the capacitor C1 is charged by the power supply voltage V _DD supplied from the power input terminal 1. At this time, the potential Va of the circuit contact (a), which is one end of the capacitor C1, and the common connection point of the switches S1 and S3, rises with the charging of the capacitor C1, and the power supply voltage at the time ts when the charging of the capacitor C1 is completed. _Equal to V _DD .
[0005]
At time t2 after elapse of a predetermined time from time t1, the first clock signal <CK1> output from the oscillation circuit 3 is switched to a low level, and the second clock signal <CK2> is switched to a high level. In response to these clock signals, the switches S1 and S2 are turned off, and the switches S3 and S4 are turned on. At this time, the potential Va is a value obtained by adding the charging voltage V _C1 of the capacitor C1 to the power supply voltage V _DD of the power input terminal 1, that is, twice the power supply voltage V _DD , and the voltage Va and the voltage via the switch S3. It is supplied to the output terminal 2. As a result, the capacitor C2 is charged to a voltage higher than the power supply voltage V _DD , and the output voltage V _out appearing at the position of the voltage output terminal 2 is about twice as large as the power supply voltage V _DD .
[0006]
Note that, when a load is connected to the voltage output terminal 2, current flows out from the capacitor C1 toward the load and the capacitor C2, so that the voltage V _C1 between terminals of the capacitor _C1 and the potential Va decrease after time t2. Here, if the capacitances of the capacitors C1 and C2 are increased in each stage with respect to the current required by the load, the voltage drop of the terminal voltage V _C1 of the capacitor C1 can be suppressed, and the waveform of the potential Va is close to a square wave. Become. Incidentally, in the case of no load, the waveform of the potential Va is a square wave, and the output voltage _Vout is twice the power supply voltage V _DD .
At time t3 after a lapse of a predetermined time from time t2, the first clock signal <CK1> output from the oscillation circuit 3 is switched to the high level, and the second clock signal <CK2> is switched to the low level. The state of the circuit of FIG. 3 at time t3 is substantially the same as that of time t1, and thereafter, the circuit of FIG. 3 repeats the above operation.
[0007]
The circuit of FIG. 3 is a basic circuit of a charge pump for obtaining an output voltage that is approximately twice the power supply voltage. By combining a plurality of these, an output voltage that is an integral multiple of three times or more can be obtained. It becomes possible. (Strictly speaking, the output voltage is not an integer multiple of the power supply voltage, but is slightly lower than that.) However, depending on the external power supply and load used, the voltage required by the load is almost the same as the power supply voltage. It is not always an integer multiple. Therefore, in order to obtain an output voltage of an arbitrary magnitude that is not limited to an integral multiple of the power supply voltage using the charge pump circuit, a regulator circuit is provided in the front stage or the rear stage of the charge pump circuit (for example, FIG. 10 of Patent Document 1). In addition, a voltage dividing capacitor and a switch are further provided in the charge pump circuit to make the boosting step finer (for example, see the circuits in FIGS. 1 to 8 of Patent Document 1 and the description thereof). It was necessary to take measures such as
[0008]
[Patent Document 1]
Japanese Patent Laid-Open No. 2001-231249
[Problems to be solved by the invention]
However, when the regulator circuit is provided, there is a problem that a large power loss occurs there, and the power conversion efficiency of the entire circuit is lowered. On the other hand, a measure for providing a voltage dividing capacitor to make the boosting step finer can suppress a decrease in efficiency, but if the output voltage is precisely matched to an arbitrary voltage, the boosting step must be made finer. As a result, an extra voltage dividing capacitor and a switch are required, which complicates the circuit configuration.
Therefore, the present invention provides a charge pump circuit that can obtain an output voltage of any magnitude that is not limited to an integral multiple of the power supply voltage without lowering the power conversion efficiency of the circuit or complicating the circuit configuration. Objective.
[0010]
[Means for Solving the Problems]
The present invention for solving the above-described problems includes a power supply input terminal for receiving supply of a power supply voltage from the outside, a voltage output terminal for supplying an output voltage to a load, a first capacitor, and a first capacitor A first switch connected between one end of the first capacitor and the power input terminal, a second switch connected between the other end of the first capacitor and the ground, one end of the first capacitor and the voltage The third switch connected between the output terminal, the fourth switch connected between the other end of the first capacitor and the power supply input terminal, and the first to fourth switches at a predetermined timing. And a second capacitor connected between the voltage output terminal and the ground, and when the first and second switches are in the on state, the first circuit is provided. Supply the power supply voltage to the capacitor. And a charge pump circuit that supplies a voltage that is a combination of the power supply voltage and the charging voltage of the first capacitor to the second capacitor when the fourth switch is on, thereby generating an output voltage higher than the power supply voltage. A comparator for comparing a charging voltage of the first capacitor with a reference voltage, and when the charging voltage of the first capacitor reaches the reference voltage, the first and second switches are turned off to charge the first capacitor; This is characterized in that the system is stopped.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
The first to fourth switches are arranged at predetermined positions between the first capacitor for boosting and the power input terminal, between the first capacitor and the voltage output terminal, and between the first capacitor and the ground, A second capacitor for smoothing is connected between the voltage output terminal and the ground, and an oscillation circuit that outputs signals for turning on and off the first to fourth switches is installed to constitute a charge pump circuit. In this charge pump circuit, a reference voltage source and a comparator for comparing the charging voltage of the first capacitor with the reference voltage are installed, and charging of the first capacitor is performed when the charging voltage of the first capacitor reaches the reference voltage. Is configured to stop.
[0012]
Specifically, the first switch arranged between the first capacitor and the input terminal, the second switch arranged between the first capacitor and the ground, or both switches are connected to the output of the oscillation circuit. It is driven by a signal processing circuit that receives the signal and the output signal of the comparison circuit. Here, the signal processing circuit forcibly turns off one or both of the first switch and the second switch regardless of the state of the output signal of the oscillation circuit, depending on the state of the output signal of the comparison circuit. It should be possible.
The output voltage of the charge pump circuit is the sum of the power supply voltage and the charging voltage of the first capacitor. In the charge pump configured as described above, the charging voltage is determined by the reference voltage. Therefore, in the charge pump circuit having this configuration, the output voltage can be set to an arbitrary level by adjusting the reference voltage.
[0013]
【Example】
FIG. 1 shows an embodiment of a charge pump circuit according to the present invention that makes it possible to obtain an output voltage of an arbitrary magnitude that is not limited to an integral multiple of the power supply voltage.
The circuit shown in FIG. 1 includes a comparator 4, a reference voltage source 5, and a signal processing circuit 6. Here, the non-inverting input terminal (+) of the comparator 4 is supplied with the reference voltage Vr from the reference voltage source 5, and the inverting input terminal (−) of the comparator 4 is supplied from one end on the high potential side of the capacitor C1. The charging voltage V _C1 is supplied. The signal processing circuit 6 is supplied with the output signal of the comparator 4 and the first clock signal <CK1> of the oscillation circuit 3, respectively, and the signals <CK3 generated in the signal processing circuit 6 are supplied to the switches S1 and S2. > Is supplied. The structure of the power input terminal 1, the voltage output terminal 2, the capacitors C1 and C2, the switches S1 to S4, and the oscillation circuit 3 and the connection relationship among them are the same as those of the conventional circuit of FIG.
[0014]
In the charge pump circuit configured as described above, as shown in the timing chart of FIG. 2, the charging voltage V _C1 of the capacitor _C1 is lower than at least the reference voltage Vr output from the reference voltage source 5 immediately before the predetermined time t1. It is a value. When the first clock signal <CK1> output from the oscillation circuit 3 at the time t1 becomes a high level, the signal processing circuit 6 changes the third clock signal <CK1> according to the output state of the comparator 4 according to the first clock signal <CK1>. The clock signal <CK3> is set to the high level. Then, the switches S1 and S2 are turned on in response to this, and the capacitor C1 is charged by the power supply voltage V _DD .
[0015]
When the charging of the capacitor C1 proceeds and the charging voltage V _C1 reaches the reference voltage Vr at time tr, the output of the comparator 4 is inverted, and accordingly, the third clock signal output from the signal processing circuit 6 <CK3> is at a low level. Then, the switches S1 and S2 are turned off in response to the third clock signal <CK3>, and the charging voltage V _C1 of the capacitor C1 is held at a value substantially equal to the reference voltage Vr. Here, the potential Va of the circuit contact (a) rises with the charging of the capacitor C1 after the time t1 until the time tr, and is maintained at a value substantially equal to the reference voltage Vr after the time tr.
[0016]
At time t2 after elapse of a predetermined time from time t1, the first clock signal <CK1> output from the oscillation circuit 3 is switched to a low level, and the second clock signal <CK2> is switched to a high level. Here, since the signal processing circuit 6 generates the third clock signal <CK3> corresponding to the logical product of the first clock signal <CK1> and the output signal of the comparator 4, the third clock signal <CK3> is generated. CK3> maintains a low level. Therefore, the switches S1 and S2 are kept off, while the switches S3 and S4 are turned on according to the state of the second clock signal <CK2>.
[0017]
Then, the potential Va becomes a value obtained by adding the charging voltage V _C1 of the capacitor C1 to the power supply voltage V _DD of the power input terminal 1, and is supplied to the capacitor C2 and the voltage output terminal 2 via the switch S3. Here, since the charging voltage V _C1 is substantially equal to the reference voltage Vr, the capacitor C2 is charged to a voltage higher than the power supply voltage V _DD , and the output voltage V _out appearing at the position of the voltage output terminal 2 is approximately It becomes the magnitude of (power supply voltage V _DD + reference voltage Vr). After time t2, current flows out from the capacitor C1 toward the load and the capacitor C2, so that the voltage V _C1 between the terminals of the capacitor C1 decreases and the potential Va also decreases.
[0018]
At time t3 after elapse of a predetermined time from time t2, the first clock signal <CK1> output from the oscillation circuit 3 is switched to a high level, and the second clock signal <CK2> is switched to a low level. At this time, the terminal voltage V _C1 of the capacitor C1 has a value lower than the reference voltage Vr by a current flowing out during the time t2 to time t3. The state of the circuit of FIG. 1 at time t3 is substantially the same as that of time t1, and thereafter, the circuit of FIG. 1 repeats the above operation.
[0019]
As described above, the circuit of FIG. 1 stops the charging of the boosting capacitor C1 when the charging voltage V _C1 becomes substantially equal to the reference voltage Vr, and the output voltage V _OUT is reduced to the power supply voltage V _DD. It operates so as to have a magnitude of + reference voltage Vr). Here, the reference voltage Vr can be adjusted independently of the power supply voltage V _DD in the reference voltage source 5, and the output voltage V _OUT is set to an arbitrary magnitude depending on the set value of the reference voltage Vr. Can do. However, in the case of the circuit of FIG. 1, because of the circuit configuration, the maximum value of the charging voltage V _C1 is the power supply voltage V _DD , so the set value of the output voltage _VOUT is in the range of 1 to 2 times the power supply voltage V _DD It will be within. If an output voltage V _OUT more than twice the power supply voltage V _DD is required, the required number of circuits in FIG. 3 may be connected in series before or after the circuit in FIG.
[0020]
1 requires a comparator 4, a reference voltage source 5, and a signal processing circuit 6 as compared with the conventional circuit of FIG. 3. However, the “voltage dividing capacitor and switch” of Patent Document 1 introduced earlier. Compared with the technique for reducing the voltage boosting step by providing the circuit configuration, the circuit configuration is not complicated. Specifically, assuming a case where an output voltage V _{OUT that} is 1.75 times the power supply voltage V _DD is required, the technique of the present invention can use the circuit of FIG. 1 as it is. In the “technology to reduce the size”, it is necessary to combine a circuit for obtaining an output voltage V _OUT of 1.5 times and a circuit for obtaining an output voltage V _OUT of 1.25 times. If it is a multiple that is poorly cut, it will not be difficult to imagine that the circuit configuration of the charge pump circuit based on the “technology for reducing the step-up step” will be further complicated.
[0021]
The present invention is not limited to the circuit configuration shown in FIG. 1. For example, in the circuit of FIG. 1, the inverting input terminal (−) of the comparator 4 is connected to one end on the high potential side of the capacitor C1. You may connect to the end which becomes the high electric potential side of the capacitor | condenser C2. However, in this case, the circuit operation is different from the circuit of FIG. 1, and the ON operation of the switches S1 and S2 becomes intermittent compared to the ON operation of the switches S3 and S4, thereby stabilizing the output voltage _VOUT . It becomes an operation like this.
[0022]
【The invention's effect】
As described above, the charge pump circuit according to the present invention includes the first capacitor for boosting, the second capacitor for smoothing, the first to fourth switches, and the clock for turning on and off each switch. A conventional charge pump circuit composed of an oscillation circuit that outputs a signal, a reference voltage source, a comparator that compares the charge voltage of the first capacitor with the reference voltage, and another clock signal from each signal of the comparator and the oscillation circuit A signal processing circuit for generating the first capacitor is installed, and charging of the first capacitor is stopped when the charging voltage of the first capacitor reaches the reference voltage.
[0023]
According to the present invention, the output voltage V _OUT can be set to an arbitrary value that is not limited to an integral multiple of the power supply voltage V _DD depending on the set value of the reference voltage Vr.
When the output voltage is set to an arbitrary magnitude, there is no circuit portion that increases power loss unlike the regulator circuit, so that the power conversion efficiency of the entire circuit does not decrease. Even when the ratio between the output voltage V _OUT and the power supply voltage V _DD is a bad value, the circuit configuration is not complicated.
Therefore, according to the present invention, there is provided a charge pump circuit capable of obtaining an output voltage of an arbitrary magnitude that is not limited to an integral multiple of the power supply voltage without lowering the power conversion efficiency of the circuit or complicating the circuit configuration. It becomes possible to provide.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of an embodiment of a charge pump circuit according to the present invention.
FIG. 2 is a timing chart of signals and voltages appearing in the circuit of FIG.
FIG. 3 is a circuit diagram of a conventional basic charge pump circuit.
4 is a timing chart of signals and voltages appearing in the circuit of FIG. 2;
[Explanation of symbols]
1: Power input terminal 2: Voltage output terminal 3: Oscillator circuit 4: Comparator 5: Reference voltage source 6: Signal processing circuit C1: Boosting capacitor (first capacitor) C2: Smoothing capacitor (second capacitor) Capacitors) S1 to S4: Switches (first to fourth switches)

Claims (1)

  A power supply input terminal for receiving supply of power supply voltage from the outside, a voltage output terminal for supplying output voltage to the outside, a first capacitor, one end of the first capacitor, and the power supply input terminal A first switch connected to the first capacitor, a second switch connected between the other end of the first capacitor and the ground, and a connection between one end of the first capacitor and the voltage output terminal. The third switch, the fourth switch connected between the other end of the first capacitor and the power input terminal, and the first to fourth switches on and off at a predetermined timing. And a second capacitor connected between the voltage output terminal and the ground, and the first capacitor is connected to the first capacitor when the first and second switches are on. The power supply voltage is supplied, and the third and fourth switches are supplied. In a charge pump circuit for supplying a voltage that is a combination of the power supply voltage and the charging voltage of the first capacitor to the second capacitor when the switch is in an on state, thereby generating an output voltage higher than the power supply voltage. The comparator for comparing the charging voltage of the first capacitor with a reference voltage, and turning off the first and second switches when the charging voltage of the first capacitor reaches the reference voltage; A charge pump circuit that stops charging of the first capacitor.

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