CN201352323Y - High-efficient synchronous rectification depressurization-type voltage stabilizer - Google Patents

Abstract

The utility model discloses a high-efficiency synchronous rectification and step-down voltage stabilizer, which comprises: a main circuit, a pulse width modulation circuit, and a trigger mode circuit, wherein the main circuit provides a reduced voltage for a load and outputs a sampling voltage to pulse The width modulation circuit and the trigger mode circuit, the reference voltage 1 is input to the pulse width modulation circuit, the pulse width modulation circuit outputs the pulse signal to the main circuit, the enable signal EN and the reference voltage 2 are input to the trigger mode circuit, and the trigger mode circuit outputs the trigger enable The signal is sent to a pulse width modulation circuit, and the pulse width modulation circuit outputs an error enabling signal to a trigger mode circuit. The utility model solves the problems of low efficiency, slow transient response, and small output voltage precision of the existing step-down voltage stabilizer under light load conditions. At the same time, because the inductance current detection circuit is integrated, no additional I/O is needed, The utility model has the advantages of high efficiency, simple structure, low cost and the like.

Description

A high-efficiency synchronous rectification step-down regulator

technical field

The utility model relates to a voltage conversion device, in particular to a buck-type voltage stabilizer controlled by peak current.

Background technique

Due to the continuous development of VLSI, switching power supply chips have developed rapidly and are widely used in various devices, especially portable electronic products, such as mobile phones, MP3, PDA, PMP, DSC, etc.

The lower the working voltage of portable products, the better, which can greatly reduce the power consumption of the battery voltage and prolong the service time of the battery. 0.6V, or even greater, using it as an output rectifier, the dynamic power consumption under high current conditions is very large. In order to solve this problem, the concept of synchronous rectification is proposed. Synchronous rectification is a new technology that uses a power MOSFET (metallic oxide semiconductor field effect transistor) with a very low on-state resistance to replace the rectifier diode to reduce rectification loss. , which can greatly improve the conversion efficiency of the buck regulator.

At present, most of the topological structures of step-down regulators use an external inductor current detection circuit, which not only adds additional I/O, but also complicates the circuit implementation. At the same time, the conversion efficiency of the existing buck regulator is very low under light load conditions. In order to improve the conversion efficiency of the buck regulator, under light load conditions, when the inductor current crosses zero, the synchronous Rectifier MOSFETs. The existing method is to add a current zero-crossing detection circuit in the circuit, but the current transformer in the detection circuit is not only bulky but also expensive, and the sensing resistor also greatly reduces the efficiency of the step-down regulator.

Contents of the invention

The utility model aims at the disadvantages of the existing step-down voltage regulator, such as low conversion efficiency under light load conditions, additional I/O needs to be added, and complicated circuit implementation, and proposes a high-efficiency step-down synchronous rectification with peak current control Regulator with trigger mode circuit off at heavy load and on trigger mode circuit at light load. So that under various load conditions, the step-down voltage regulator has high efficiency, and at the same time adopts the internal integrated inductor current detection circuit, so that the step-down voltage regulator is small in size, light in weight and low in cost.

A high-efficiency synchronous rectification step-down regulator, including: a main circuit 101, a pulse width modulation circuit 102, and a trigger mode circuit 103, wherein the main circuit 101 provides a stepped-down voltage for a load and outputs a sampling voltage to a pulse width The modulation circuit 102 and the trigger mode circuit 103, the reference voltage 1Vref1 is input to the pulse width modulation circuit 102, the pulse width modulation circuit 102 outputs the pulse signal to the main circuit 101, the enable signal EN and the reference voltage 2Vref2 are input to the trigger mode circuit 103, The trigger mode circuit 103 outputs the trigger enable signal EN_Burst_Cmp to the pulse width modulation circuit 102 , and the pulse width modulation circuit 102 outputs the error enable signal EN_EA to the trigger mode circuit 103 .

Main circuit 101 described in the utility model constitutes as follows:

The positive pole of a DC power supply Vin is connected to the source of the main switch tube MP, the drain of the main switch tube MP is connected to the source of the rectifier switch tube MN and one end of the energy storage inductor L, the drain of the rectifier switch tube MN is grounded, and the energy storage inductor The other end of L is connected to the energy storage capacitor C, the other end of the energy storage capacitor C is grounded, one end of the load Rload is connected to the common end of the energy storage inductor L and the energy storage capacitor C, and the other end of the load Rload is grounded.

The composition of pulse width modulation circuit 102 described in the utility model is as follows:

One end of the resistor R1 is connected to the common end of the energy storage inductor L and the energy storage capacitor C in the main circuit 101, the other end is connected to one end of the resistor R2, the other end of the resistor R2 is grounded, and the common end of the resistor R1 and the resistor R2 is connected The negative input terminal of the error amplifier EA, the positive input terminal of the error amplifier EA is connected to the reference voltage 1Vref1, the error amplifier EA outputs the error signal Vea to the positive input terminal of the pulse width modulation comparator PWM COMP, and outputs the error enable signal EN-EA to The trigger comparator Burst Cmp, the negative input terminal of the pulse width modulation comparator PWM COMP is connected to the inductor current detection circuit and the slope compensation circuit, the output terminal of the pulse width modulation comparator PWM COMP is connected to the input terminal of the driving circuit, and the output terminal of the driving circuit is connected to Gates of the main switching transistor MP and the rectifying switching transistor MN in the main circuit 101 .

The composition of trigger mode circuit 103 described in the utility model is as follows:

The positive input terminal of the trigger comparator Burst Cmp is connected to the node between R1 and R2 in the pulse width modulation circuit 102, the negative input terminal is connected to the negative pole of Vref2, and the enable signal EN is input to the trigger comparator Burst Cmp, The trigger comparator Burst Cmp outputs a trigger enable signal EN_Burs_Cmp to the error amplifier EA in the pulse width modulation circuit 102.

The inductance current detection circuit and the slope compensation circuit described in the utility model are integrated in the chip.

The operating frequency of the error amplifier EA, the pulse modulation comparator PWM COMP, the trigger comparator Burs Cmp, the inductance current detection circuit and the slope compensation circuit described in the utility model is higher than the pulse signal frequency output by the pulse width modulation comparator.

The utility model solves the problems of low efficiency, slow transient response, and small output voltage precision of the existing step-down voltage stabilizer under light load conditions. At the same time, because the inductance current detection circuit is integrated, no additional I/O is needed. The utility model has the advantages of high efficiency, simple structure, low cost and the like.

Description of drawings

Fig. 1 is a functional block diagram of the utility model;

Fig. 2 is the schematic circuit diagram of the utility model.

Detailed ways

Below in conjunction with accompanying drawing, the utility model is further described. As shown in FIG. 1, a high-efficiency synchronous rectification step-down regulator includes: a main circuit 101, a pulse width modulation circuit 102, and a trigger mode circuit 103, wherein the main circuit 101 provides a stepped-down voltage for the load and Output the sampling voltage to the pulse width modulation circuit 102 and the trigger mode circuit 103, the reference voltage 1Vref1 is input to the pulse width modulation circuit 102, the pulse width modulation circuit 102 outputs the pulse signal to the main circuit 101, the enable signal EN and the reference voltage 2Vref2 are input To the trigger mode circuit 103 , the trigger mode circuit 103 outputs the trigger enable signal EN_Burst_Cmp to the pulse width modulation circuit 102 , and the pulse width modulation circuit 102 outputs the error enable signal EN_EA to the trigger mode circuit 103 .

The main circuit 101 is constituted as follows

The positive pole of a DC power supply Vin is connected to the source of the main switch tube MP, the drain of the main switch tube MP is connected to the source of the rectifier switch tube MN and one end of the energy storage inductor L, the drain of the rectifier switch tube MN is grounded, and the energy storage inductor The other end of L is connected to the energy storage capacitor C, the other end of the energy storage capacitor C is grounded, one end of the load Rload is connected to the common end of the energy storage inductor L and the energy storage capacitor C, and the other end of the load Rload is grounded.

The constitution of the pulse width modulation circuit 102 is as follows

One end of the resistor R1 is connected to the common end of the energy storage inductor L and the energy storage capacitor C in the main circuit 101, the other end is connected to one end of the resistor R2, the other end of the resistor R2 is grounded, and the common end of the resistor R1 and the resistor R2 is connected The negative input terminal of the error amplifier EA, the positive input terminal of the error amplifier EA is connected to the reference voltage 1Vref1, the error amplifier EA outputs the error signal Vea to the positive input terminal of the pulse width modulation comparator PWM COMP, and outputs the error enable signal EN-EA to The voltage amplifier Burst Cmp, the negative input terminal of the pulse width modulation comparator PWM COMP are connected to the inductor current detection circuit and the slope compensation circuit, and the inductor current detection circuit and the slope compensation circuit are integrated in the chip. The output terminal of the pulse width modulation comparator PWM COMP is connected to the input terminal of the driving circuit, and the output terminal of the driving circuit is respectively connected to the gates of the main switching tube MP and the rectifying switching tube MN in the main circuit 101.

The configuration of the trigger mode circuit 103 is as follows

The positive input terminal of the trigger comparator Burst Cmp is connected to the node between R1 and R2 in the pulse width modulation circuit 102, the negative input terminal is connected to the negative pole of Vref2, and the enable signal EN is input to the trigger comparator Burst Cmp, The trigger comparator Burst Cmp outputs a trigger enable signal EN_Burs_Cmp to the error amplifier EA in the pulse width modulation circuit 102.

The operating frequency of the error amplifier EA, the pulse modulation comparator PWM COMP, the trigger comparator Burs Cmp, the inductor current detection circuit and the slope compensation circuit is higher than the frequency of the pulse signal output by the pulse width modulation comparator.

The working principle of the utility model is as follows

The utility model adopts a double-loop feedback control mode. When the load changes, the inductance current detection circuit detects the peak value of the inductance current, and adjusts the duty ratio of the pulse signal accordingly to stabilize the voltage at both ends of the load Rload.

According to different application situations, the utility model can be divided into two working states of light load mode and heavy load mode.

When working under heavy load conditions, the trigger mode circuit 103 is turned off, the trigger comparator BurstCmp does not work at this time, the inductor current is continuous, the inductor current detection circuit detects the value of the inductor current, and accordingly controls the hollow ratio of the pulse signal to stabilize the load The voltage across Rload.

When working under light load conditions, the enable signal EN turns on the trigger mode circuit 103, triggers the comparator Burst Cmp to compare the voltage between the resistor network R1 and R2 with the reference voltage vref2, and generates the trigger enable signal EN_Burst_Cmp to control the error amplifier EA to enable The negative input terminal of the error amplifier is different from the DC level of the positive input terminal, the error amplifier EA amplifies the difference between the voltage between the resistor network R1 and R2 and the reference voltage vref1, and generates an error enable signal EN_EA to trigger the comparator Burst Cmp, so that The trigger enable signal EN_Burst_Cmp sent back by the trigger comparator Burst Cmp is reversed, and the pulse modulation comparator PWM COMP performs chopping according to the output of the error amplifier EA.

According to the rise and fall process of the voltage at both ends of the load Rload, the analysis is as follows

When the voltage across the load Rload drops to the normal lower limit voltage. At this time, the comparator Burst Cmp is triggered to flip, and the common-mode level of the two input terminals of the error amplifier EA is the same, and the error signal Vea output by the error amplifier turns into a high voltage at this time, and the pulse modulation comparator PWM COMP compares the error signal Vea with the inductance The detection circuit detects the voltage converted from the inductance L current, outputs a series of pulses, and the voltage at both ends of the load Rload starts to rise. When the feedback voltage of the output voltage rises to the reference voltage Vref1 of the positive input terminal of the error amplifier, the error amplifier EA The error enable signal EN_EA is generated to control the trigger enable signal EN_Burst_Cmp sent by the trigger comparator to flip, so that the common mode levels of the two input terminals of the error amplifier EA are different, the pulse width modulation comparator PWM COMP continues to output low level, and the main switch The voltage at both ends of the load Rload starts to drop when the tube MP cuts off, and when the voltage at both ends of the load Rload drops to the normal lower limit voltage, it returns to the cycle at the beginning of this section.

The output voltage under light load conditions can be achieved by repeating the above process.

The high-efficiency synchronous rectification step-down converter controlled by the peak current in the utility model can control the duty cycle of the pulse according to the sampled inductance current value, has fast transient response, and can set the trigger mode according to different load conditions, The step-down voltage regulator has the characteristics of high efficiency, simple structure, and low cost under both light load and heavy load conditions.

Of course, the above description is not a limitation of the present utility model, and the present utility model is not limited to the above-mentioned examples, and changes, modifications, additions or replacements made by those skilled in the art within the essential scope of the present utility model are also acceptable. It should belong to the protection scope of utility model.

Claims (6)

1. A high-efficiency synchronous rectification step-down regulator, characterized in that it comprises: A main circuit, a pulse width modulation circuit, and a trigger mode circuit, wherein the main circuit provides a stepped-down voltage for the load and outputs a sampling voltage to the pulse width modulation circuit and the trigger mode circuit, and the reference voltage 1 is input to the pulse width modulation circuit, so The pulse width modulation circuit outputs the pulse signal to the main circuit, the enable signal EN and the reference voltage 2 are input to the trigger mode circuit, the trigger mode circuit outputs the trigger enable signal to the pulse width modulation circuit, and the pulse width modulation circuit outputs the error enable signal to the trigger mode circuit. 2. A high-efficiency synchronous rectification step-down regulator according to claim 1, wherein the main circuit is composed as follows: The positive pole of a DC power supply is connected to the source of the main switch tube, the drain of the main switch tube is connected to the source of the rectifier switch tube and one end of the energy storage inductor L, the drain of the rectifier switch tube is grounded, and the other end of the energy storage inductor L is connected to The energy storage capacitor C, the other end of the energy storage capacitor C is grounded, one end of the load is connected to the common end of the energy storage inductor L and the energy storage capacitor C, and the other end of the load is grounded. 3. A high-efficiency synchronous rectification step-down voltage stabilizer according to claim 1, wherein the composition of the pulse width modulation circuit is as follows: One end of the resistor R1 is connected to the common end of the energy storage inductance L and the energy storage capacitor C in the main circuit, the other end is connected to one end of the resistor R2, and the other end of the resistor R2 is grounded, and the common termination error between the resistor R1 and the resistor R2 The negative input terminal of the amplifier, the positive input terminal of the error amplifier is connected to the reference voltage 1, the error amplifier outputs the error signal to the positive input terminal of the pulse width modulation comparator, and outputs the error enable signal to the trigger mode circuit, the pulse width modulation comparator The negative input terminal is connected to the inductor current detection circuit and the slope compensation circuit, the output terminal of the pulse width modulation comparator is connected to the input terminal of the driving circuit, and the output terminal of the driving circuit is respectively connected to the grid of the main switching tube and the rectifying switching tube in the main circuit. pole. 4. A high-efficiency synchronous rectification step-down voltage stabilizer according to claim 1, wherein the configuration of the trigger mode circuit is as follows: The positive input terminal of the trigger comparator is connected to the node between R1 and R2 in the pulse width modulation circuit, the negative input terminal is connected to the reference voltage 2, the enable signal EN is input to the trigger comparator, and the trigger comparator outputs a trigger enabling Can signal to the error amplifier in the pulse width modulation circuit. 5. A high-efficiency synchronous rectification step-down regulator according to claim 3, characterized in that: said inductor current detection circuit and slope compensation circuit are integrated inside the chip. 6. A high-efficiency synchronous rectification step-down regulator according to claim 3, characterized in that: the operating frequency of the error amplifier, pulse modulation comparator, inductor current detection circuit and slope compensation circuit is higher than that of the pulse The frequency of the pulse signal output by the width modulation comparator.

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