CN108964645B - Delay circuit - Google Patents

Delay circuit Download PDF

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Publication number
CN108964645B
CN108964645B CN201811161052.1A CN201811161052A CN108964645B CN 108964645 B CN108964645 B CN 108964645B CN 201811161052 A CN201811161052 A CN 201811161052A CN 108964645 B CN108964645 B CN 108964645B
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tube
electrode
delay circuit
control switch
drain electrode
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CN108964645A (en
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殷晓文
李冬超
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Shanghai Awinic Technology Co Ltd
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Shanghai Awinic Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/28—Modifications for introducing a time delay before switching
    • H03K17/284—Modifications for introducing a time delay before switching in field effect transistor switches
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/30—Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

Abstract

The application discloses delay circuit, owing to increased and set up a control switch, control switch connects in the circuit to break control according to the time sequence and switch on and turn off its place circuit, thereby change the continuous charge-discharge process of electric capacity in the delay circuit into discrete charge-discharge process, thereby prolong delay circuit's delay time, in order to reduce the size of electric capacity in the delay circuit, and then reduce the holistic area occupied of circuit.

Description

Delay circuit
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a delay circuit.
Background
Delay circuits are an important component in integrated circuits. The high-performance and high-precision delay circuit can greatly improve the ground performance of the integrated circuit.
The delay circuit is designed according to the time sequence requirement, so that the signal transmission is ensured to be in sequence. For example, in an application scenario of a Light-Emitting Diode (LED) driving chip, an MCU (micro control unit, microcontroller Unit) controls the LED chip, and if an interrupt signal is sent for processing parallel tasks, and the interrupt signal causes the enable signal to remain low for a long time, the chip may be turned off by mistake. A certain delay is designed between the external enabling and the chip internal enabling to prevent the chip from being turned off by mistake. If the interrupt time is relatively long and the chip delay is not long enough, the chip may be directly turned off by the interrupt signal.
The traditional delay circuit generally adopts a capacitor charge-discharge delay structure, and when the condition of larger delay time is realized, the problem of larger circuit occupation area exists.
Disclosure of Invention
In view of this, the present invention provides a delay circuit to solve the problem of large circuit occupation area when the delay circuit in the prior art is used to implement a larger delay time.
In order to achieve the above purpose, the present invention provides the following technical solutions:
a delay circuit comprising:
the power supply, the first PMOS tube, the inverter, the current source and the capacitor;
the source electrode of the first PMOS tube is connected with the power supply;
the drain electrode of the first PMOS tube is connected with one end of the inverter and one end of the capacitor;
the other end of the inverter is used as the output end of the delay circuit;
the other end of the capacitor is grounded;
the grid electrode of the first PMOS tube is used as the input end of the delay circuit and receives input voltage;
the delay circuit further comprises a control switch, wherein the control switch is connected between the drain electrode of the first PMOS tube and the first end of the current source, and is used for intermittently controlling connection of the drain electrode of the first PMOS tube and the first end of the current source to be turned on and off according to a time sequence;
the second end of the current source is grounded.
A delay circuit comprising:
the power supply, the first NMOS tube, the inverter, the current source and the capacitor;
the source electrode of the first NMOS tube is grounded;
the drain electrode of the first NMOS tube is connected with one end of the inverter and one end of the capacitor;
the other end of the inverter is used as the output end of the delay circuit;
the other end of the capacitor is grounded;
the grid electrode of the first NMOS tube is used as the input end of the delay circuit and receives input voltage;
the first end of the current source is connected with the power supply;
the delay circuit further comprises a control switch, wherein the control switch is connected between the drain electrode of the first NMOS tube and the second end of the current source, and is used for intermittently controlling connection of the drain electrode of the first NMOS tube and the second end of the current source IREF to be turned on and off according to a time sequence.
According to the technical scheme, the control switch is additionally arranged in the delay circuit, is connected in the circuit, and is used for intermittently controlling the circuit to be turned on and off according to the time sequence, so that the continuous charging and discharging process of the capacitor in the delay circuit is converted into the discrete charging and discharging process, the delay time of the delay circuit is prolonged, the size of the capacitor in the delay circuit is reduced, and the occupied area of the whole circuit is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a capacitor charge-discharge delay circuit in the prior art;
FIG. 2 is a schematic diagram of a delay circuit with a PMOS tube as an input tube according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a delay circuit with another PMOS tube as an input tube according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a delay circuit with another PMOS tube as an input tube according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a delay circuit with another PMOS tube as an input tube according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a delay circuit with another PMOS tube as an input tube according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a delay circuit with another PMOS tube as an input tube according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a delay circuit with another PMOS tube as an input tube according to an embodiment of the present invention;
fig. 9 is a schematic diagram of a delay circuit with an NMOS as an input tube according to an embodiment of the present invention;
fig. 10 is a schematic diagram of a delay circuit with another NMOS as an input tube according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of a delay circuit with another NMOS tube as an input tube according to an embodiment of the present invention;
fig. 12 is a schematic diagram of a delay circuit with another NMOS as an input tube according to an embodiment of the present invention.
Detailed Description
As described in the background art, when the capacitor charge-discharge delay circuit in the prior art has a larger delay time, the problem of larger circuit occupation area exists.
The inventor finds that the reason for the phenomenon is that, as shown in fig. 1, fig. 1 is a schematic diagram of a capacitor charge-discharge delay circuit in the prior art; assuming that the inverter has a flip voltage V, the delay time is:
as can be seen from the formula, to increase the delay time, the capacitance of the capacitor can be increased, VDD can be increased, or the inverting voltage V of the inverter can be reduced; however, the inversion voltage of the inverter is actually the threshold voltage V of the MOS transistor TH This V TH The numerical value is about 0.7V-1V, which is related to the temperature and the process, and the V is difficult to change in design TH A kind of electronic device. While theoretically increasing VDD may increase the delay time, the voltage domain is between 1.8V and 5.5V for digital logic circuits. If VDD is increased to 5.5V, the delay is only increased by a factor of 2.75, but the voltage domain of the VIN signal is not changed, the high level of VIN may not be high for MP, MP may be always on, and the circuit is disabled. It is also desirable to increase VDD and also increase the voltage domain of the input signal VIN. By increasing the capacitance of the capacitor, the capacitor occupies a larger area of the chip, and if vdd=2v, the flip voltage v=1v, and the discharge current I C To achieve a 2ms delay, a capacitance of 20pF is required at this time, which area overhead is not acceptable.
Based on this, the present invention provides a new delay circuit.
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 2, fig. 2 is a schematic diagram of a delay circuit with a PMOS transistor as an input transistor according to an embodiment of the present invention, where the delay circuit includes: power supply VDD, first PMOS transistor MP, inverter 11, and current source I REF And capacitor C d The method comprises the steps of carrying out a first treatment on the surface of the The source electrode of the first PMOS tube MP is connected with a power supply VDD; the drain electrode of the first PMOS tube MP and one end of the inverter 11, and the capacitor C d Is connected with one end of the connecting rod; the other end of the inverter 11 is used as an output end of the delay circuit; capacitor C d The other end of the first electrode is grounded; the grid electrode of the first PMOS tube MP is used as the input end of the delay circuit and receives the input voltage VIN; wherein the delay circuit further comprises a control switch K connected with the drain electrode of the first PMOS tube MP and the current source I REF Is used for intermittently controlling the on-off of the drain electrode of the first PMOS tube MP and the current source I according to the time sequence REF Is connected to the first end of the housing; current source I REF Is grounded.
In this embodiment, in the first PMOS transistor MP and the current source I REF The control switch K is additionally arranged between the two circuits and is connected in the circuit, and the circuit where the control switch K is arranged is intermittently controlled to be turned on and turned off according to the time sequence, so that the continuous charging and discharging process of the capacitor in the delay circuit is converted into the discrete charging and discharging process, the delay time of the delay circuit is prolonged, the size of the capacitor in the delay circuit is reduced, and the whole occupied area of the circuit is reduced.
The specific structure of the control switch K is not limited in this embodiment, as long as the on and off of the intermittent control circuit can be realized, which is not limited in this embodiment.
Optionally, as shown in fig. 3, fig. 3 shows a delay of another PMOS transistor as an input transistor according to an embodiment of the present inventionSchematic circuit structure. The control switch K in this embodiment includes a first switching tube MSW, where a gate of the first switching tube MSW receives a square wave signal OSC; the drain electrode of the first switching tube MSW is connected with the drain electrode of the first PMOS tube MP; source electrode of first switch tube MSW and current source I REF Is connected to the first end of the housing.
In this embodiment, the first switch tube MSW is a first NMOS tube MSW. In other embodiments of the present invention, the first switching tube MSW may be a PMOS tube, and in this embodiment, the first switching tube MSW is illustrated as a first NMOS tube MSW.
It should be noted that, in the embodiment of the present invention, the intermittent voltage of the control switch may be a square wave signal, a pulse signal, or other intermittent voltages, which is not limited in this embodiment.
In the present embodiment, the current source I REF The current source is not limited, and can be any type; referring to fig. 4, fig. 4 is a schematic diagram of a delay circuit with another PMOS transistor as an input transistor according to an embodiment of the present invention; wherein, the current source I REF Comprising the following steps: current bias module 12, bias current source I bias The second NMOS tube MN2 and the third NMOS tube MN3; wherein, the current bias module 12 and the bias current source I bias Is connected to the first end of the housing; bias current source I bias The second end of the second NMOS transistor MN2 is connected with the drain electrode, the grid electrode and the grid electrode of the third NMOS transistor MN3; the source electrode of the second NMOS tube MN2 is grounded; the drain electrode of the third NMOS tube MN3 is connected with the source electrode of the first NMOS tube MSW; the source of the third NMOS transistor MN3 is grounded.
It should be noted that the current bias module 12 is a bias current source I bias Providing a bias current; the current is I bias In this embodiment, when the delay circuit works normally, the current source I is biased bias Current and capacitance C provided d Is set to the discharge current I of C Mirror image.
In this embodiment, a switch tube MSW is added between the first PMOS tube MP and the third NMOS tube MN3, and the gate signal of the first NMOS tube MSW is a period T OSC Is a square wave signal of (a).
When VIN is changed from low level to high level, the first PMOS MP is turned off, and the voltage at node a starts to be changed from high to low.
When the square wave signal OSC is at high level, the first NMOS transistor MSW is turned on, the working state of the delay circuit is the same as that of the delay circuit in the prior art, the node a is at high level, and the third NMOS transistor MN3 is connected to the capacitor C d The high level pulse width of the square wave signal OSC is T in one period H Voltage V of node A A Drop Δv=i C ·T H /C d 。
When the square wave signal OSC is low level, the first NMOS transistor MSW is turned off, and the capacitor C d There is no bleed path for the charge in (a), and the node a potential is maintained. In each subsequent period of the square wave signal OSC, the delay circuit repeats the above process, the potential of the node a drops continuously, and VOUT turns from low to high when the voltage V of the inverter 11 drops, and the delay time is:
wherein T is OSC Is one cycle length of the switching signal; t (T) H Is of high level pulse width, T H /T OSC Duty ratio called square wave, if the duty ratio is set to 1%, the time is delayed by T delay Will become 100 times the original.
In other words, in this embodiment, after adding the control switch MSW controlled by the square wave signal OSC, the same delay T is realized, and the capacitor C only needs C d ·(T H /T OSC ) The requirements can be met, and the capacitance area is greatly reduced.
It should be noted that, the delay circuit provided in the embodiment of the invention greatly prolongs the delay time. In order to further improve the control accuracy of the delay circuit, the inventors further found that in the embodiment of the present invention, when the square wave signal OSC is low, the first NMOS transistor MSW is turned off, and the node B voltage V B When the square wave signal OSC is changed from low to high, the node B has a node capacitance C d Is set to the discharge current I of C Equal toThe sum of the mirror current of the third NMOS transistor MN3 and the discharge current of the node capacitance. Bias current source I bias Current and capacitance C of (2) d Is set to the discharge current I of C Cannot be maintained, so that there is a deviation in the delay.
In order to eliminate the delay deviation, another delay circuit is provided in the embodiment of the present invention, please refer to fig. 5, fig. 5 is a schematic diagram of a delay circuit structure in which another PMOS transistor provided in the embodiment of the present invention is used as an input transistor; the delay circuit is based on fig. 4, and further includes: the voltage follower circuit 13 in this embodiment is connected between the source of the first NMOS transistor MSW and the drain of the first PMOS transistor MP, and the voltage follower circuit is configured to make the source voltage of the first NMOS transistor MSW follow the voltage of the drain of the first PMOS transistor MP when the square wave signal OSC changes from low to high.
In this embodiment, a voltage follower circuit is added between node A and node B to make the voltage of node B follow the voltage V of node A when the square wave signal OSC is low to high A Thereby ensuring the discharge current I C Is a mirror image of the precision of (c).
It should be noted that, in the embodiment, the specific structure of the voltage follower circuit 13 is not limited, and optionally, as shown in fig. 6, fig. 6 is a schematic diagram of a delay circuit with another PMOS transistor as an input transistor according to the embodiment of the present invention; fourth NMOS tube MN13, second PMOS tube MP13 and first current source I B Impedance R F A first reverse control switch K1 and a second reverse control switch K2; the control signals of the first inverse control switch K1 and the second inverse control switch K2 are inverse to the level signal of the square wave signal OSC; the source electrode of the fourth NMOS tube MN13 is connected with the source electrode of the first NMOS tube MSW; the drain electrode of the fourth NMOS transistor MN13 and the resistor R F Is connected with one end of the connecting rod; impedance R F The other end of the power supply is connected with a power supply VDD; the grid electrode of the fourth NMOS tube MN13 is connected with one end of the first reverse control switch K1; the power supply VDD is connected with one end of a second reverse control switch K2, and the other end of the second reverse control switch K2 is connected with a first current source I B Is connected to the first end of the housing; first current source I B Is connected to the other end of the first reverse control switch K1 and is connected to the second PMOSA source of pipe MP 13; the drain electrode of the second PMOS tube MP13 is grounded; the grid electrode of the second PMOS tube MP13 is connected with the drain electrode of the first PMOS tube MP.
The specific principle of the voltage follower circuit 13 provided in the present embodiment is as follows:
wherein,the phase of the signal OSC is opposite to that of the signal OSC, and when the signal OSC is low, the first inverse control switch K1 and the second inverse control switch K2 are both closed and the follower circuit is turned on; when the square wave signal OSC is high, both the first and second inverse control switches K1 and K2 open the circuit to be inoperative.
When the square wave signal OSC changes from high to low, the voltage V of node B B Voltage V with node A A Is almost equal to each other and,to be high, the first reverse control switch K1 and the second reverse control switch K2 are closed to start working by the following circuit, and the voltage V of the node C is equal to C Equal to V A Adding drain-source voltage V of second PMOS tube MP13 GS1 Voltage V of node B B Voltage V equal to node C C Minus the drain-source voltage V of the fourth NMOS transistor MN13 GS2 By setting the second PMOS tube MP13, the width-to-length ratio of the fourth NMOS tube MN13 and I B And impedance R F The value of (2) is such that V GS1 ＝V GS2 Then V can be made to A ＝V B Thereby ensuring the accuracy of the discharge current. Furthermore, in order to save power consumption, there is +.>First current source I when low B Does not work.
V C ＝V A +V GS1
V B ＝V C -V GS2
In the present embodiment, the impedance R is not limited F Can be as shown in FIG. 6As the resistor, as shown in fig. 7, fig. 7 is a schematic diagram of a delay circuit with another PMOS transistor as an input transistor according to the embodiment of the present invention; wherein the impedance R F The transistor is biased in a saturation region, and the source electrode of the transistor is connected with a power supply VDD; the drain electrode of the transistor is connected with the drain electrode of the fourth NMOS transistor MN 13; the gate of the transistor receives a bias voltage V b- And (5) controlling.
In other embodiments of the present invention, the voltage follower circuit 13 may also be an operational amplifier structure, and the operational amplifier is an operational amplifier with a certain gain. The op-amp is connected in unity gain and the voltage at node B will follow the voltage at node a. Referring to fig. 8, fig. 8 is a schematic diagram of a delay circuit with another PMOS transistor as an input transistor according to an embodiment of the present invention; the voltage follower circuit 13 is an operational amplifier connected in a unit gain form, that is, a non-inverting input end of the operational amplifier is connected with a source electrode of the first NMOS tube MSW; the inverting input end of the operational amplifier is connected with the output end of the operational amplifier and is connected to the drain electrode of the first PMOS tube MP.
In all the embodiments, the input end is taken as a PMOS tube as an example, and in practical application, the input tube of the delay circuit may be an NMOS tube.
Referring to fig. 9, fig. 9 is a schematic diagram of a delay circuit with an NMOS as an input tube according to an embodiment of the present invention; the delay circuit includes: power supply VDD, first NMOS transistor MN, inverter 21, and current source I REF And capacitor C d The method comprises the steps of carrying out a first treatment on the surface of the The source electrode of the first NMOS tube MN is grounded; the drain of the first NMOS transistor MN and one end of the inverter 21, the capacitor C d Is connected with one end of the connecting rod; the other end of the inverter 21 is used as an output end of the delay circuit; capacitor C d The other end of the first electrode is grounded; the grid electrode of the first NMOS tube MN is used as the input end of the delay circuit and receives the input voltage VIN; current source I REF Is connected to a power supply VDD; wherein the delay circuit further comprises a control switch K connected to the drain of the first NMOS transistor MN and the current source I REF The drain electrode and the electricity of the first NMOS tube MN are intermittently controlled to be turned on and off according to the time sequenceStream source I REF Is connected to the second end of the first connector.
The detailed working principle can be seen from the delay control principle of the delay circuit using the PMOS tube as the input tube in the above embodiment, which is not limited in this embodiment.
Similarly, the specific structure of the control switch K is not limited in the present embodiment, as long as the on and off of the intermittent control circuit can be realized, and this is not limited in the present embodiment.
Optionally, as shown in fig. 10, fig. 10 is a schematic diagram of a delay circuit with another NMOS tube as an input tube according to an embodiment of the present invention; the control switch K in this embodiment includes a first switching tube MSW, where a gate of the first switching tube MSW receives a square wave signal OSC; source electrode of first switch tube MSW and current source I REF Is connected to the second end of the first member; the drain electrode of the first switch tube MSW is connected with the drain electrode of the first NMOS tube MN.
In this embodiment, the first switch tube MSW is a first PMOS tube MSW. In other embodiments of the present invention, the first switching tube MSW may be an NMOS tube, and in this embodiment, the first switching tube MSW is illustrated as a first PMOS tube MSW.
It should be noted that, in the embodiment of the present invention, the intermittent voltage of the control switch may be a square wave signal, a pulse signal, or other intermittent voltages, which is not limited in this embodiment.
In the present embodiment, the current source I REF The current source is not limited, and can be any type; referring to fig. 11, fig. 11 is a schematic diagram of a delay circuit with another NMOS as an input tube according to an embodiment of the present invention; wherein, the current source I REF Comprising the following steps: current bias module 22, bias current source I bias The second PMOS tube MP2 and the third PMOS tube MP3; wherein, the current bias module 22 and the bias current source I bias Is connected to the first end of the housing; bias current source I bias The second end of the second PMOS tube MP2 is connected with the drain electrode and the grid electrode of the third PMOS tube MP3; the source electrode of the second PMOS tube MP2 and the source electrode of the third PMOS tube MP3 are connected with the power supply VDD; the drain electrode of the third PMOS tube MP3 is connected with the source electrode of the first PMOS tube MSW.
It should be noted that the current bias module 22 is a bias current source I bias Providing a bias current; the current is I bias In this embodiment, when the delay circuit works normally, the current source I is biased bias Current and capacitance C provided d I of (2) C Mirror image.
The detailed working principle can be seen from the delay control principle of the delay circuit using the PMOS tube as the input tube in the above embodiment, which is not limited in this embodiment.
Similarly, in order to further improve the control accuracy of the delay circuit, the delay circuit in this embodiment may further include a voltage follower circuit, please refer to fig. 12, fig. 12 is a schematic diagram of a delay circuit with another NMOS transistor as an input tube according to an embodiment of the present invention. The delay circuit further comprises, on the basis of fig. 11: a voltage follower circuit 23; the voltage follower circuit 23 is connected between the source of the first PMOS MSW and the drain of the first NMOS MN, and is configured to make the source voltage of the first PMOS MSW follow the voltage of the drain of the first NMOS MN when the square wave signal OSC changes from low to high.
The voltage follower circuit 23 in the present embodiment may be the same as the structure of the voltage follower circuit 13 in fig. 6, see the voltage follower circuit 13 in fig. 6, that is, the voltage follower circuit 23 includes: a second NMOS transistor (hereinafter, MN13 in FIG. 6 is also used as its reference number), a fourth PMOS transistor (hereinafter, MP13 in FIG. 6 is also used as its reference number), a first current source I B Impedance R F A first reverse control switch K1 and a second reverse control switch K2; the control signals of the first inverse control switch K1 and the second inverse control switch K2 are inverse to the level signal of the square wave signal OSC; the source electrode of the second NMOS tube MN13 is connected with the source electrode of the first PMOS tube MSW; the drain electrode of the second NMOS transistor MN13 and the resistor R F Is connected with one end of the connecting rod; impedance R F The other end of the power supply is connected with a power supply VDD; the grid electrode of the second NMOS tube MN13 is connected with one end of the first reverse control switch K1; the power supply VDD is connected with one end of a second reverse control switch, and the other end of the second reverse control switch K2 is connected with a first current source I B Is connected to the first end of the housing; first current source I B The second end of the second PMOS transistor is connected with the other end of the first reverse control switch K1 and is connected to the source electrode of the fourth PMOS transistor MP 13; the drain electrode of the fourth PMOS tube MP13 is grounded; the grid electrode of the fourth PMOS tube MP13 is connected with the drain electrode of the first NMOS tube MN.
Likewise, the impedance R F Either as a resistor or as a transistor including a bias in the saturation region when the impedance R F When the transistor is included, the source electrode of the transistor is connected with the power supply VDD; the drain electrode of the transistor is connected with the drain electrode of the second NMOS tube; the gate of the transistor receives a bias voltage V b- And (5) controlling.
In other embodiments of the present invention, the voltage follower circuit 23 may also be an operational amplifier structure, and the operational amplifier is an operational amplifier with a certain gain. The op-amp is connected in unity gain and the voltage at node B will follow the voltage at node a. The non-inverting input end of the operational amplifier is connected with the source electrode of the first PMOS tube MSW; the inverting input terminal of the operational amplifier is connected to the output terminal of the operational amplifier and to the drain electrode of the first NMOS transistor MN.
The embodiment of the invention provides a delay circuit, which has the following advantages:
1. the mode of saving the capacitance area: a control switch K is added which controls the on and off of the circuit intermittently in time sequence, which in some embodiments may be a switching tube controlled by a square wave signal OSC.
2. The mode for improving the accuracy of the discharge current is as follows: a voltage follower circuit implementation is added between node a and node B.
The voltage follower circuit can be replaced by any voltage follower circuit, and the structure of the current source can be any current source circuit. The PMOS tube and the NMOS tube in the circuit can be replaced according to the requirement. The above matters are not limited in this embodiment.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in an article or apparatus that comprises such element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (12)

1. A delay circuit, comprising:
the power supply, the first PMOS tube, the inverter, the current source and the capacitor;
the source electrode of the first PMOS tube is connected with the power supply;
the drain electrode of the first PMOS tube is connected with one end of the inverter and one end of the capacitor;
the other end of the inverter is used as the output end of the delay circuit;
the other end of the capacitor is grounded;
the grid electrode of the first PMOS tube is used as the input end of the delay circuit and receives input voltage;
the delay circuit further comprises a control switch, wherein the control switch is connected between the drain electrode of the first PMOS tube and the first end of the current source, and is used for intermittently controlling connection of the drain electrode of the first PMOS tube and the first end of the current source to be turned on and off according to a time sequence, and in the process that the input voltage controls the first PMOS tube to be turned off, the charge-discharge process of the capacitor is converted into a discrete charge-discharge process by the connection and the disconnection of the control switch;
the second end of the current source is grounded;
the control switch comprises a first switch tube, and a grid electrode of the first switch tube receives square wave signals;
the drain electrode of the first switch tube is connected with the drain electrode of the first PMOS tube;
the source electrode of the first switching tube is connected with the first end of the current source;
the first switch tube is a first NMOS tube;
the delay circuit further comprises a voltage follower circuit; the voltage follower circuit is connected between the source electrode of the first NMOS tube and the drain electrode of the first PMOS tube.
2. The delay circuit of claim 1 wherein the current source comprises:
the current bias module, the bias current source, the second NMOS tube and the third NMOS tube;
the current bias module is connected with the first end of the bias current source;
the second end of the bias current source is connected with the drain electrode and the grid electrode of the second NMOS tube and the grid electrode of the third NMOS tube;
the source electrode of the second NMOS tube is grounded;
the drain electrode of the third NMOS tube is connected with the source electrode of the first NMOS tube;
and the source electrode of the third NMOS tube is grounded.
3. The delay circuit of claim 2 wherein the voltage follower circuit is configured to cause the source voltage of the first NMOS transistor to follow the voltage of the drain of the first PMOS transistor when the square wave signal changes from low to high.
4. A delay circuit as recited in claim 3, wherein said voltage follower circuit comprises:
the second NMOS tube, the second PMOS tube, the first current source, the impedance, the first reverse control switch and the second reverse control switch; the control signals of the first reverse control switch and the second reverse control switch are opposite to the level signal of the square wave signal;
the source electrode of the fourth NMOS tube is connected with the source electrode of the first NMOS tube;
the drain electrode of the fourth NMOS tube is connected with one end of the impedance;
the other end of the impedance is connected with the power supply;
the grid electrode of the fourth NMOS tube is connected with one end of the first reverse control switch;
the power supply is connected with one end of the second reverse control switch, and the other end of the second reverse control switch is connected with the first end of the first current source;
the second end of the first current source is connected with the other end of the first reverse control switch and is connected to the source electrode of the second PMOS tube;
the drain electrode of the second PMOS tube is grounded;
and the grid electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube.
5. The delay circuit of claim 4 wherein the impedance is a resistor;
alternatively, the impedance includes a transistor biased in a saturation region;
when the impedance comprises a transistor, the source of the transistor is connected to the power supply; the drain electrode of the transistor is connected with the drain electrode of the fourth NMOS tube; the gate of the transistor receives bias voltage control.
6. A delay circuit as recited in claim 3, wherein said voltage follower circuit comprises: an operational amplifier;
the non-inverting input end of the operational amplifier is connected with the source electrode of the first NMOS tube;
and the inverting input end of the operational amplifier is connected with the output end of the operational amplifier and is connected to the drain electrode of the first PMOS tube.
7. A delay circuit, comprising:
the power supply, the first NMOS tube, the inverter, the current source and the capacitor;
the source electrode of the first NMOS tube is grounded;
the drain electrode of the first NMOS tube is connected with one end of the inverter and one end of the capacitor;
the other end of the inverter is used as the output end of the delay circuit;
the other end of the capacitor is grounded;
the grid electrode of the first NMOS tube is used as the input end of the delay circuit and receives input voltage;
the first end of the current source is connected with the power supply;
the delay circuit further comprises a control switch, wherein the control switch is connected between the drain electrode of the first NMOS tube and the second end of the current source, and is used for intermittently controlling connection of the drain electrode of the first NMOS tube and the second end of the current source to be turned on and off according to a time sequence, and in the process that the input voltage controls the first NMOS tube to be turned off, the on and off of the control switch changes the charge-discharge process of the capacitor into a discrete charge-discharge process;
the control switch comprises a first switch tube, and a grid electrode of the first switch tube receives square wave signals;
the source electrode of the first switching tube is connected with the second end of the current source;
the drain electrode of the first switch tube is connected with the drain electrode of the first NMOS tube;
the first switch tube is a first PMOS tube;
the delay circuit further comprises a voltage follower circuit;
the voltage follower circuit is connected between the source electrode of the first PMOS tube and the drain electrode of the first NMOS tube.
8. The delay circuit of claim 7 wherein the current source comprises:
the current bias module, the bias current source, the second PMOS tube and the third PMOS tube;
the current bias module is connected with the first end of the bias current source;
the second end of the bias current source is connected with the drain electrode and the grid electrode of the second PMOS tube and the grid electrode of the third PMOS tube;
the source electrode of the second PMOS tube and the source electrode of the third PMOS tube are connected with the power supply;
and the drain electrode of the third PMOS tube is connected with the source electrode of the first PMOS tube.
9. The delay circuit of claim 8 wherein the voltage follower circuit is configured to cause the source voltage of the first PMOS transistor to follow the voltage of the drain of the first NMOS transistor when the square wave signal changes from low to high.
10. The delay circuit of claim 9 wherein the voltage follower circuit comprises:
the second NMOS tube, the fourth PMOS tube, the first current source, the impedance, the first reverse control switch and the second reverse control switch; the control signals of the first reverse control switch and the second reverse control switch are opposite to the level signal of the square wave signal;
the source electrode of the second NMOS tube is connected with the source electrode of the first PMOS tube;
the drain electrode of the second NMOS tube is connected with one end of the impedance;
the other end of the impedance is connected with the power supply;
the grid electrode of the second NMOS tube is connected with one end of the first reverse control switch;
the power supply is connected with one end of the second reverse control switch, and the other end of the second reverse control switch is connected with the first end of the first current source;
the second end of the first current source is connected with the other end of the first reverse control switch and is connected to the source electrode of the fourth PMOS tube;
the drain electrode of the fourth PMOS tube is grounded;
and the grid electrode of the fourth PMOS tube is connected with the drain electrode of the first NMOS tube.
11. The delay circuit of claim 10 wherein the impedance R F Is a resistor;
alternatively, the impedance includes a transistor biased in a saturation region;
when the impedance comprises a transistor, the source of the transistor is connected to the power supply; the drain electrode of the transistor is connected with the drain electrode of the second NMOS tube; the gate of the transistor receives bias voltage control.
12. The delay circuit of claim 9 wherein the voltage follower circuit comprises: an operational amplifier;
the non-inverting input end of the operational amplifier is connected with the source electrode of the first PMOS tube;
and the inverting input end of the operational amplifier is connected with the output end of the operational amplifier and is connected to the drain electrode of the first NMOS tube.
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WO2002003551A2 (en) * 2000-06-30 2002-01-10 Mosaid Technologies Incorporated Digital delay element
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