CN112595886A

CN112595886A - Low-power-consumption self-adaptive zero-crossing detection circuit

Info

Publication number: CN112595886A
Application number: CN202011484790.7A
Authority: CN
Inventors: 程心; 柳成林; 李睿文; 张章; 张永强
Original assignee: Hefei University of Technology
Current assignee: Hefei University of Technology
Priority date: 2020-12-16
Filing date: 2020-12-16
Publication date: 2021-04-02
Anticipated expiration: 2040-12-16
Also published as: CN112595886B

Abstract

The invention discloses a low-power-consumption self-adaptive zero-crossing detection circuit, which comprises a biasing module, a self-adaptive biasing module and a comparison module, wherein the biasing module is used for generating a zero-crossing signal; the bias module provides bias current for the zero-crossing detection circuit; the self-adaptive bias module provides self-adaptive bias current for the comparison module according to the external input voltage VX; the comparison module adjusts the response speed of the comparison module according to the condition of the external input voltage VX and the self-adaptive bias current; when the external input voltage VX rises from a negative value to 0V, the zero-crossing detection circuit outputs a low level to turn off the external NMOS power tube so as to prevent the generation of reverse current; the invention can reduce the power consumption of the zero-crossing detection circuit, improve the response speed of the zero-crossing detection circuit and reduce the energy loss caused by reverse current, thereby effectively improving the conversion efficiency of the switching power supply under the condition of light load.

Description

Low-power-consumption self-adaptive zero-crossing detection circuit

Technical Field

The invention relates to a power supply management module in the field of analog integrated circuit design, in particular to a low-power-consumption self-adaptive zero-crossing detection circuit applied to a switching power supply related to the Internet of things.

Background

With the rapid growth of the application of the internet of things, the demand for developing wireless sensor nodes is increasing day by day. Many applications, such as smart cities/buildings, healthcare, home automation, environmental monitoring, and even industrial applications, require long-term sensor operation. Because many internet of things portable devices and energy harvesting devices are not normally installed, their power supplies are not easily replaced, and require longer power supply life depending on load conditions. Therefore, the power management chip with low power consumption and high efficiency is very important for prolonging the service life of the power supply. A recent trend is to integrate a switching power supply with an internet of things device and a wearable device or a radio frequency transceiving system in one chip.

Different from mobile application, the wireless sensor used in the application of the internet of things has two working modes: active mode and standby mode. The wireless sensor is in a standby mode most of the time, when the load current is low; sometimes it is necessary to enter the active mode quickly for a short time to transmit data, when the load current is large. Calculations show that when the load current in standby mode is 1uA, the total energy consumption in standby mode is 10 times the total energy consumption in active mode, so the standby power controls the total power budget. Therefore, improving the conversion efficiency in the standby mode becomes more and more important to reduce the overall power consumption.

Under light load conditions, the switching power supply achieves efficiency maximization by blocking reverse current by operating in a discontinuous conduction mode. In order to work in the discontinuous conduction mode, the zero-crossing detection circuit is required to compare the voltage of the VX point with 0V voltage, and the NMOS power tube is turned off at the zero-crossing point so as to prevent reverse current. In discontinuous conduction mode, the comparator has a propagation delay, and the propagation delay has a very large effect on the switching power supply. If the NMOS power transistor cannot be turned off in time, even a delay of a few nanoseconds may cause a reverse current of approximately 100 milliamperes, resulting in a sharp drop in the conversion efficiency of the switching power supply. The switching power supply generally requires a high-speed comparator to cut off the reverse current as fast as possible, but the high-speed comparator usually occupies a large area, and meanwhile, the static current in the high-speed comparator is very large, and under the condition of light load, the current consumed by the zero-crossing detection circuit is dominant, so that the conversion efficiency is limited.

Disclosure of Invention

The invention provides a low-power-consumption self-adaptive zero-crossing detection circuit for overcoming the defects in the prior art, so that the power consumption of the zero-crossing detection circuit can be reduced, the response speed of the zero-crossing detection circuit is improved, the energy loss caused by reverse current is reduced, and the conversion efficiency of a switching power supply under the condition of light load is effectively improved.

The invention adopts the following technical scheme for solving the technical problems:

the invention discloses a low-power consumption self-adaptive zero-crossing detection circuit which is characterized by comprising the following components: the device comprises a biasing module, a self-adaptive biasing module and a comparison module;

the bias module converts an internal bias current IBIAS into a gate-source voltage difference and provides a gate voltage in the gate-source voltage difference to the self-adaptive bias module;

the self-adaptive bias module performs self-adaptive adjustment according to the external input voltage VX and the received gate voltage to obtain self-adaptive bias current and provides the self-adaptive bias current to the comparison module;

the comparison module carries out self-adaptive adjustment on the slew rate of the comparison module according to the external input voltage VX and the self-adaptive bias current, so that the slew rate is increased along with the increase of the difference value between the input voltage VX and 0 and the increase of the self-adaptive bias current;

when the external input voltage VX rises from a negative value to be more than 0V, the comparison module outputs a low level, so that the external NMOS power tube is turned off to prevent the generation of reverse current.

The low power consumption self-adaptive zero-crossing detection circuit is also characterized in that the bias module comprises: a reference current source and a second NMOS transistor MN 2;

the adaptive bias module comprises: a first NMOS transistor MN1 and a first PMOS transistor MP 1;

the comparison module comprises: a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a third NMOS transistor MN3, a fourth NMOS transistor MN4, and a fifth NMOS transistor MN 5;

the reference current source generates a bias current IBIAS and provides the bias current IBIAS to a channel between the source electrode and the drain electrode of the second NMOS tube MN 2;

the source of the second NMOS transistor MN2 receives an external input voltage GND, and the channel between the source and the drain of the second NMOS transistor MN2 receives the bias current IBIAS, so that a voltage difference, i.e., a first gate-source voltage, is generated between the gate and the source of the second NMOS transistor MN2, and a first gate voltage of the first gate-source voltage is provided to the gate of the first NMOS transistor MN 1;

the gate of the first NMOS transistor MN1 receives the first gate voltage, and generates an adaptive bias current in the channel between the drain and the source of the first NMOS transistor MN1 according to the external input voltage VX received by the source of the first NMOS transistor MN1 and provides the adaptive bias current to the channel between the drain and the source of the first PMOS transistor MP 1;

the source stage of the first PMOS transistor MP1 receives an external input voltage VDD, and the channel between the drain and the source of the first PMOS transistor MP1 receives the adaptive bias current, so that a voltage difference, i.e., a second gate-source voltage, is generated between the gate and the source of the first PMOS transistor MP1, and the second gate voltage of the second gate-source voltage is provided to the gate of the second PMOS transistor MP 2;

the gate of the second PMOS transistor MP2 receives the first gate voltage, the source of the second PMOS transistor MP2 receives the external input voltage VDD, so that a first current equal to the adaptive bias current is generated between the drain and the source of the second PMOS transistor MP2, and the first current generates a second current and a third current according to the external input voltage VX, which are respectively provided to the channel between the source and the drain of the fourth PMOS transistor MP4 and the channel between the source and the drain of the fifth PMOS transistor MP 5;

the channel between the source and the drain of the fourth PMOS transistor MP4 receives the second current and provides the second current to the channel between the source and the drain of the third NMOS transistor MN 3;

the source of the third NMOS transistor MN3 receives an external input voltage GND, and the channel between the source and the drain of the third NMOS transistor MN3 receives the second current, so that a voltage difference, i.e., a third gate-source voltage, is generated between the gate and the source of the third NMOS transistor MN3, and the third gate voltage of the third gate-source voltage is transmitted to the gate of the fourth NMOS transistor MN 4;

a channel between a source and a drain of the fifth PMOS transistor MP5 receives the third current and provides the third current to a gate of a fifth NMOS transistor MN5, and the gate of the fifth PMOS transistor MP5 receives an external input voltage GND;

the gate of the fourth NMOS transistor MN4 receives the second gate voltage, and the source of the fourth NMOS transistor MN4 receives the external input voltage VX, generates a fourth current, and supplies the fourth current to the gate of the fifth NMOS transistor;

the source of the fifth NMOS transistor MN5 receives an external input voltage GND, and the gate of the fifth NMOS transistor MN5 receives the third current and the fourth current, so that a voltage difference, i.e., a fourth gate-source voltage, is generated between the source and the drain of the fifth NMOS transistor MN5, and the fourth gate-source voltage in turn causes a channel between the source and the drain of the fifth NMOS transistor MN5 to generate a fifth current, and supply the fifth current to the output terminal;

the source of the third PMOS transistor MP3 receives an external input voltage VDD, and the gate of the third PMOS transistor MP3 receives the first gate voltage, so that the channel between the source and the drain of the third PMOS transistor MP3 generates a sixth current and provides the sixth current to the output terminal, and the output terminal receives the fifth current and the sixth current and generates an output voltage VOUT to an external circuit.

Compared with the prior art, the invention has the beneficial effects that:

1. the zero-cross detection circuit needs to have an extremely high speed in order to prevent generation of a reverse current. The traditional zero-crossing detection circuit can generate larger power consumption while obtaining higher speed, and is not in line with the design concept of a low-power-consumption switching power supply. While other zero-crossing detection circuits designed for low power consumption consume low power but are not fast enough, thus generating large reverse current. The invention adopts the self-adaptive technology of bias current and slew rate, and can obtain higher speed while consuming lower power consumption. The bias current self-adaptive technology can finish the self-adaptive adjustment of the slew rate of the comparison module according to the condition of the external input voltage VX, the aim of adjusting the bias current of the comparison module according to requirements is achieved, and the average power consumption of the whole circuit during operation is greatly reduced. The slew rate self-adaptive technology can complete the self-adaptive adjustment of the slew rate of the comparison module according to the condition of the external input voltage VX, the aim of adjusting the response speed of the comparison module according to requirements is fulfilled, and the detection speed of the whole circuit is greatly improved.

2. The traditional zero-crossing detection circuit takes an NMOS differential pair as an input stage of a comparison module, and only can detect non-negative voltage but cannot judge the negative voltage. The PMOS differential pair is used as the input stage of the comparison module, so that the non-negative voltage and the negative voltage can be detected simultaneously, the range of the input voltage is expanded, and the whole variation range of the external input voltage VX is covered.

3. According to the invention, the external input voltage VX is directly input from the grid electrode of the first NMOS tube MN1 and the source stage of the fourth NMOS tube MN4, no redundant MOS tube is introduced, the structure is simple, and the power consumption is lower. In addition, the introduction of the second input end increases the gain of the comparison module, improves the resolution of the comparison module, and enables the comparison module to distinguish extremely low external input voltage.

Drawings

Fig. 1 is a schematic diagram of a conventional switching power supply;

FIG. 2 is a schematic diagram of waveforms of voltage and inductor current at different NMOS turn-off times;

FIG. 3 is a schematic diagram of the zero crossing detection circuit of the present invention;

FIG. 4 is a small signal diagram with VX as input and VOUT1 as output;

FIG. 5 is a schematic diagram of a zero crossing detection circuit without the technique used in the present invention;

FIG. 6 is a waveform diagram of a simulation under large signal input conditions;

FIG. 7 is a waveform diagram of a simulation under a small signal input condition;

FIG. 8 is a waveform diagram of a zero crossing detection circuit gain simulation;

fig. 9 is a schematic diagram of a switching power supply structure to which the present invention is applied;

fig. 10 is a simulated waveform diagram of a switching power supply to which the present invention is applied;

Detailed Description

A conventional low power switching power supply structure is shown in fig. 1. When the voltage value of VOUT is smaller than the voltage value of VREF, the comparator outputs low level to enable the first PMOS tube MP1 to be conducted, the first NMOS tube MN1 is turned off, the input power VDD charges the inductor, the output capacitor is charged, and the output voltage VOUT rises; when the voltage value of VOUT is larger than the voltage value of VREF, the comparator outputs high level to turn off the first PMOS tube and turn on the second NMOS tube, demagnetizes the inductor to the ground, discharges the output capacitor and reduces the output voltage VOUT. The final VOUT voltage value stabilizes around the VREF voltage value.

The switching power supply operates in a discontinuous conduction mode under light load conditions to achieve higher conversion efficiency. Fig. 2 shows a schematic diagram and waveforms of the voltage and the inductor current at different turn-off times of the NMOS power transistor in the discontinuous conduction mode. If the NMOS power tube is turned off later, the output capacitor COUT can be discharged by reverse current, and due to the voltage drop of the conducting resistor of the NMOS power tube, the voltage VX of the switch node becomes positive, and the reverse current is generated, so that the energy loss is caused; if the NMOS power tube is just closed, the voltage VX of the switch node is zero, no reverse current exists, and therefore no energy loss exists. Therefore, in discontinuous conduction mode, accurate zero current detection is required.

The structure diagram of the zero-crossing detection circuit of the invention is shown in fig. 3. Next, the details of the circuit configuration will be described first.

A low power consumption adaptive zero crossing detection circuit comprising: the device comprises a biasing module, a self-adaptive biasing module and a comparison module;

wherein, the biasing module includes: a reference current source and a second NMOS transistor MN 2;

the adaptive bias module includes: a first NMOS transistor MN1 and a first PMOS transistor MP 1;

The functions and operating principles of the modules of the zero-cross detection circuit of the present invention will be described next.

The bias module of the low-power-consumption self-adaptive zero-crossing detection circuit converts an internal bias current IBIAS into a gate-source voltage difference and provides gate voltage in the gate-source voltage difference to the self-adaptive bias module;

the working principle of the self-adaptive bias module is as follows: by adopting the bias current self-adaptive technology, the self-adaptive adjustment of the bias current of the comparator can be completed according to the condition of the external input voltage VX.

Specifically, the width-to-length ratios of the first NMOS transistor MN1 and the second NMOS transistor MN2 are set to be equal, and the width-to-length ratios of the first PMOS transistor MP1 and the second PMOS transistor MP2 are set to be equal. When the value of the external input voltage VX is equal to 0V, the first NMOS transistor MN1 is clocked by 1: the ratio of 1 is to copy the current of the second NMOS transistor, which flows through the first PMOS transistor simultaneously, and then the current is converted from the second PMOS transistor MP2 into a 1: the ratio of 1 is copied to the comparison block, where the bias current value of the comparison block is equal to the current value set by the reference current source.

When the value of the external input voltage VX is greater than 0, the gate-source voltage of the first NMOS transistor MN1 is less than the gate-source voltage of the second NMOS transistor MN2, so the drain current of the first NMOS transistor MN1 is less than the current set by the reference current source, and similarly, the current flows through the first PMOS transistor MP1 at the same time, and then is divided by the second PMOS transistor MP2 by 1: the ratio of 1 is copied to the comparison module, so that the bias current value of the comparison module is smaller than the current value of the reference current source at this time.

When the value of the external input voltage VX is less than 0, the gate-source voltage of the first NMOS transistor is greater than the gate-source voltage of the second NMOS transistor MN2, so the drain current of the first NMOS transistor MN1 is greater than the current set by the reference current source, and similarly, the current flows through the first PMOS transistor MP1 at the same time, and then is divided by the second PMOS transistor MP2 by 1: the ratio of 1 is copied to the comparison module, so that the bias current value of the comparison module is larger than the current value of the reference current source at the moment.

For the realization of the zero-crossing detection function in the switching power supply, the zero-crossing detection circuit needs to detect the moment when the external input voltage VX jumps from below 0V to above 0V.

When VX is larger than zero, the zero-crossing detection circuit does not need to work, and the zero-crossing detection circuit can be closed to reduce power consumption. For the invention, when the value of the external input voltage VX is greater than 0, the bias current value of the comparator is smaller than the current value of the reference current source, and the zero-crossing detection circuit is in an approximately closed state, and the larger the value of the external input voltage VX is, the larger the closing degree is, and the lower the power consumption consumed by the zero-crossing detection circuit is.

When VX is less than zero, zero-crossing detection circuit work is required to detect the instant when external input voltage VX jumps from below 0V to above 0V. For the invention, when the value of the external input voltage VX is less than 0, the bias current value of the comparator is greater than the current value of the reference current source, and more current flows into the zero-crossing detection circuit at the moment, so that energy is consumed at a required place. At the moment, the transient response speed of the zero-crossing detection circuit is higher, and the accuracy is higher.

The working principle of the comparison module is as follows: and the self-adaptive adjustment of the slew rate of the comparator can be completed according to the condition of the external input voltage VX by adopting the slew rate self-adaptive technology.

And the slew rate of the comparison module is IOUT/CP. The IOUT is an output current of a differential pair composed of a second PMOS transistor MP2, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a third NMOS transistor MN3, and a fourth NMOS transistor MN4, and the CP is a parasitic capacitance of all gates of the fifth NMOS transistor MN 5.

Specifically, the width-to-length ratio of the third NMOS transistor MN3 to the fourth NMOS transistor MN4 is set to 1: 1. when the value of the external input voltage VX is equal to 0V, the fourth NMOS transistor MN4 is clocked by 1: the ratio of 1 replicates the current of the third NMOS transistor MN 3.

When the value of the external input voltage VX is greater than 0V, the gate-source voltage of the third NMOS tube MN3 is greater than the gate-source voltage of the fourth NMOS tube MN4, and the current of the fourth NMOS tube MN4 is less than the current of the third NMOS tube MN3, so that a larger current flows into the gate of the fifth NMOS tube MN5, namely the IOUT value is larger, and the slew rate is enhanced.

Similarly, when the value of the external input voltage VX is less than 0V, the gate-source voltage of the third NMOS transistor MN3 is less than the gate-source voltage of the fourth NMOS transistor MN4, and the current of the fourth NMOS transistor MN4 is greater than the current of the third NMOS transistor MN3, so that a greater current flows from the gate of the fifth NMOS transistor MN5, i.e., the IOUT value is greater, thereby increasing the slew rate.

Another benefit of introducing slew rate adaptation techniques is to make the comparison module gain larger, which is derived as follows. Fig. 4 shows a diagram of a small signal obtained by applying the superposition theorem to an input terminal of the external input voltage VX and an output terminal VOUT1 of the gate of the fifth NMOS transistor MN 5. The path gain is calculated as:

in the formula (1), gmn3 is transconductance of a third NMOS transistor MN3, gmn4 is transconductance of a fourth NMOS transistor MN4, gmp4 is transconductance of a fourth PMOS transistor MP4, ron3 is equivalent resistance of a channel length effect of the third NMOS transistor MN3, rop4 is equivalent resistance of a channel length effect of a fourth PMOS transistor MP4, ron4 is equivalent resistance of a channel length effect of the fourth NMOS transistor MN4, and rop5 is equivalent resistance of a channel length effect of a fifth PMOS transistor MP 5.

And the gains of VOUT1 to VOUT are:

in the formula (2), gmn5 is the transconductance of the fifth NMOS transistor MN5, rop3 is the equivalent resistance of the MP3 channel length effect of the third PMOS transistor, and ron5 is the equivalent resistance of the MN5 channel length effect of the fifth NMOS transistor.

Thus, the gain of the comparison module is:

compared with a circuit which does not apply the slew rate adaptive technology, the gain of the invention is increased:

the invention improves the gain, and simultaneously, the zero pole of the circuit is not changed. Therefore, the zero-crossing detection circuit has wider bandwidth and higher response speed to small signal input.

Next, the simulation result of the zero-cross detection circuit of the present invention will be described. In addition, the zero-cross detection circuit shown in fig. 5, to which the technique of the present invention is not applied, was also subjected to simulation under the same conditions for comparison, thereby embodying the advantages of the technique of the present invention. In simulation, the width-to-length ratio and the bias current of the MOS transistor corresponding to the zero-cross detection circuit shown in fig. 5 and the present invention are set to be the same.

The simulated waveform under large signal input conditions is shown in fig. 6. VX is the input voltage and VOUT is the output voltage. In the column of the output voltage VOUT, the solid line represents the waveform of the circuit of the present invention, and the dotted line represents the waveform without using the circuit of the present invention. The simulation sets the external input voltage VX to a square wave that jumps between negative 2V and positive 2V. Simulation results show that the delay of the rising edge of the circuit is reduced by 9.16% compared with the delay of the circuit without the technology, and the delay of the falling edge of the circuit is reduced by 66.54% compared with the delay of the circuit without the technology.

The simulated waveform under small signal input conditions is shown in fig. 7. VX is the input voltage and VOUT is the output voltage. In the column of the output voltage VOUT, the solid line represents the waveform of the circuit of the present invention, and the dotted line represents the waveform without using the circuit of the present invention. The simulation sets the external input voltage VX to a square wave that jumps between negative 20mV and positive 20 mV. Simulation results show that the delay of the rising edge of the circuit is reduced by 36.08 percent compared with the delay of the circuit without the technology, and the delay of the falling edge of the circuit is reduced by 6.95 percent compared with the delay of the circuit without the technology.

The zero-crossing detection circuit gain simulation waveform is shown in fig. 8. The solid line represents the waveform of the circuit of the present invention and the dotted line represents the waveform without using the circuit of the present invention. Simulation results show that compared with the circuit without the technology, the circuit gain of the invention is improved by 10.93%, and the unit gain bandwidth is increased by 42.33%.

A switching power supply structure to which the present invention is applied is shown in fig. 9. When the voltage value of VOUT is smaller than the voltage value of VREF, the comparator outputs low level to enable the first PMOS tube MP1 to be conducted, the first NMOS tube MN1 is turned off, the inductor is charged with magnetism, the capacitor is charged, and the output voltage rises; when the voltage value of VOUT is greater than the voltage value of VREF, the comparator outputs a high level, so that the first PMOS transistor MP1 is turned off, the first NMOS transistor MN1 is turned on, the inductor is demagnetized, the capacitor is discharged, the output voltage drops, meanwhile, the zero-crossing detection module detects the voltage value of VX constantly, the first NMOS transistor MN1 is turned off at the moment when the voltage value of VX crosses zero, then, the first PMOS transistor MN1 and the first NMOS transistor MN1 are both in a turned-off state, and the voltage value of VOUT slowly drops. The final VOUT voltage value stabilizes around the VREF voltage value. The switching power supply to which the present invention is applied is in discontinuous conduction mode. The zero-crossing detection circuit of the invention turns off the first NMOS tube MN1 at the moment when the VX voltage value crosses zero, so that the reverse current is extremely small, the loss is extremely small, and the conversion efficiency of the switching power supply is improved.

A simulated waveform of a switching power supply to which the present invention is applied is shown in fig. 10. Where IVDD represents the current flowing from the power supply and VOUT represents the output voltage. The current IVDD flowing from the power supply multiplied by the supply voltage is the power consumed by the power supply, while the supply voltage is constant. Therefore, the lower the average value of IVDD over a period of time, the lower the power consumption that is consumed. In addition, the zero-cross detection circuit needs to detect the instant when the external input voltage VX rises from a negative value to 0V or more, and output a low level in time. Therefore, the time of the zero-crossing detection circuit outputting the low level minus the time of the zero-crossing occurrence moment is the time delay of the zero-crossing detection circuit, and the smaller the difference value is, the smaller the time delay of the zero-crossing detection module is, the faster the speed is. Simulation results show that compared with a circuit which does not use a bias current self-adaptive technology and a slew rate self-adaptive technology, the average power consumption of the circuit is reduced by 20.29%, and the delay of the moment when the external input voltage VX is detected to jump from below 0V to above 0V is reduced by 18.83%.

The zero-crossing detection circuit provided by the invention can be used in a switching power supply related to the Internet of things, and can also be used in any switching power supply design needing to reduce the power consumption of a module and simultaneously block reverse current.

Claims

1. A low-power consumption adaptive zero-crossing detection circuit, comprising: the device comprises a biasing module, a self-adaptive biasing module and a comparison module;

2. The low power adaptive zero crossing detection circuit of claim 1, wherein the biasing module comprises: a reference current source and a second NMOS transistor MN 2;