CN111478563A - Zero-crossing detection circuit suitable for BUCK converter - Google Patents

Zero-crossing detection circuit suitable for BUCK converter Download PDF

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Publication number
CN111478563A
CN111478563A CN202010414691.5A CN202010414691A CN111478563A CN 111478563 A CN111478563 A CN 111478563A CN 202010414691 A CN202010414691 A CN 202010414691A CN 111478563 A CN111478563 A CN 111478563A
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China
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tube
electrode
nmos
transistor
buck converter
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CN202010414691.5A
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CN111478563B (en
Inventor
明鑫
张�杰
梁华
贾丽伟
程政
黄佳晖
王卓
张波
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/083—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the ignition at the zero crossing of the voltage or the current
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/175—Indicating the instants of passage of current or voltage through a given value, e.g. passage through zero
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0006—Arrangements for supplying an adequate voltage to the control circuit of converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Dc-Dc Converters (AREA)
  • Measurement Of Current Or Voltage (AREA)

Abstract

A zero-crossing detection circuit suitable for a BUCK converter is characterized in that when an upper power tube and a lower power tube of the BUCK converter are closed and opened by utilizing a sampling module, signals of a power ground and a switch node of the BUCK converter are sampled and connected to a first input end and a second input end of a comparator module; the comparator module is used for acquiring error information of a power ground and a switch node signal of the BUCK converter, converting the error information into a comparison result represented by high and low levels and outputting the comparison result to the output shaping module; the bias module is used for providing bias for the comparator module, and adjusting the turning point of the zero-crossing detection circuit by setting an error between the base voltage of the first NPN type triode and the base voltage of the second NPN type triode; the invention provides double power supply voltages, and the output shaping module is combined to realize shaping of the voltage information at the output end of the comparator module, and meanwhile, the voltage change range of the output end of the comparator module when the comparator is turned over can be effectively reduced, and the response speed of the zero-crossing detection circuit is improved.

Description

Zero-crossing detection circuit suitable for BUCK converter
Technical Field
The invention belongs to the technical field of power management, and particularly relates to a zero-crossing detection circuit which can be applied to a BUCK converter.
Background
Fig. 1 shows a power topology structure of a BUCK converter, and when an output load is small, when an upper power tube MH is turned off and a lower power tube M L is turned on, an inductive current I is generatedLIt will gradually decrease and then freewheel in reverse, i.e. from the switch node SW to the power ground PGND of the BUCK converter, causing energy losses. Therefore, a zero-cross detection circuit is required to detect the reverse current of the synchronous rectification transistor. When the zero-crossing detection circuit detects the current reversal of the synchronous rectifier tube, the zero-crossing detection circuit sends a signal to turn off the synchronous rectifier transistor so as to prevent the current reversal.
Under the influence of semiconductor manufacturing process deviation, environment temperature and working voltage, random input offset voltage and time delay exist in the zero-crossing detection circuit, so that the time from the detection of reverse current by the zero-crossing detection circuit to the sending of a signal for turning off the synchronous rectification transistor is inaccurate: when the turn-off time of the synchronous rectification transistor is too early, the inductive current continues current by depending on the body diode of the synchronous rectification transistor, and larger body diode loss is generated; when the turn-off time of the synchronous rectification transistor is too late, the current of the inductor is reversed, the system efficiency is reduced in the form of conduction loss, meanwhile, the SW has large ringing voltage, the voltage stress of the transistor and the inductor is increased, the loss of the power tube is aggravated, and the EMI problem is introduced; therefore, a relatively precise zero-crossing detection circuit is needed to timely turn off the synchronous rectification transistor to solve the above problems.
In current applications, switching power supplies are developed towards high voltage, high frequency and large current. In high-voltage application, the change rate of the inductive current is higher, and higher requirements are put forward on the reaction speed of the zero-crossing detection circuit; in high-frequency application, the switching period is shortened, the zero-crossing detection circuit needs extra blanking time, and higher requirements are also put forward on the reaction speed of the zero-crossing detection circuit; in large-current application, the body diode loss and the inductive current in the asynchronous state are reversed, so that the efficiency of the converter is reduced, and higher requirements are provided for the precision of a zero-crossing detection circuit.
Disclosure of Invention
Aiming at the problems that the time of a turn-off signal is inaccurate in the traditional zero-crossing detection circuit and the requirements on the response speed and the detection precision of the zero-crossing detection circuit, the invention provides the zero-crossing detection circuit suitable for the BUCK converter, and compared with the traditional zero-crossing detection comparator, the zero-crossing detection circuit provided by the invention can adjust the detuning amount according to the needs and change the turning point; meanwhile, two kinds of power supply voltages are adopted and the circuit of the output shaping module is designed, so that the transmission delay of the invention can be well optimized.
The technical scheme of the invention is as follows:
a zero-crossing detection circuit suitable for a BUCK converter comprises an upper power tube and a lower power tube, wherein a connection point of the upper power tube and the lower power tube is a switch node;
the zero-crossing detection circuit comprises a bias module, a sampling module, a comparator module and an output shaping module,
the sampling module is used for sampling the power ground of the BUCK converter and accessing the power ground to the first input end of the comparator module when an upper power tube of the BUCK converter is closed and a lower power tube of the BUCK converter is opened, and sampling a switch node signal of the BUCK converter and accessing the switch node signal to the second input end of the comparator module;
the input pair transistors of the comparator module are a first NPN triode and a second NPN triode, an emitting electrode of the first NPN triode is used as a first input end of the comparator module, an emitting electrode of the second NPN triode is used as a second input end of the comparator module, and the comparator module is used for acquiring error information of a power ground of the BUCK converter and a switch node signal of the BUCK converter, converting the error information into a comparison result represented by a high level and a low level and outputting the comparison result to the output shaping module;
the bias module is used for providing bias for the comparator module, a first output end of the bias module is connected with a base electrode of the first NPN type triode, a second output end of the bias module is connected with a base electrode of the second NPN type triode, and a turning point of the zero-crossing detection circuit is adjusted by setting an error between a base electrode voltage of the first NPN type triode and a base electrode voltage of the second NPN type triode;
the output shaping module comprises a first phase inverter, a second phase inverter, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a thirteenth NMOS tube and a fourteenth NMOS tube, power supplies of the first phase inverter and the second phase inverter are second power supply voltage, a power supply of the zero-crossing detection circuit is first power supply voltage, and the voltage value of the first power supply voltage is higher than that of the second power supply voltage;
the grid electrode of the seventh PMOS tube is connected with the first control signal, the source electrode of the seventh PMOS tube is connected with the second power supply voltage, and the drain electrode of the seventh PMOS tube is connected with the input end of the first phase inverter and is used as the comparison result of the input end of the output shaping module which is connected with the comparator module;
when an upper power tube and a lower power tube of the BUCK converter are closed, the first control signal is at a high level, and when the upper power tube and the lower power tube of the BUCK converter are opened, the first control signal is at a low level;
the input end of the second phase inverter is connected with the output end of the first phase inverter and the grid electrode of the fourteenth NMOS tube, and the output end of the second phase inverter is connected with the grid electrode of the thirteenth NMOS tube;
the grid electrode of the eighth PMOS tube is connected with the drain electrode of the ninth PMOS tube and the drain electrode of the fourteenth NMOS tube, the source electrode of the eighth PMOS tube is connected with the source electrode of the ninth PMOS tube and the first power supply voltage, and the drain electrode of the eighth PMOS tube is connected with the grid electrode of the ninth PMOS tube and the drain electrode of the thirteenth NMOS tube and serves as the output end of the zero-crossing detection circuit;
and the source electrodes of the thirteenth NMOS tube and the fourteenth NMOS tube are connected with the power ground of the zero-crossing detection circuit.
Specifically, the sampling module comprises a sixth NMOS tube, a seventh NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a third resistor, a fourth resistor, a sixth resistor, a seventh resistor, and a third current source, and the sixth NMOS tube, the seventh NMOS tube, the eleventh NMOS tube, and the twelfth NMOS tube are high-voltage resistant devices;
the grid electrode of the sixth NMOS tube is connected with the grid electrode of the seventh NMOS tube and the first control signal, the source electrode of the sixth NMOS tube is connected with the source electrode of the eleventh NMOS tube and the first input end of the comparator module, and the drain electrode of the sixth NMOS tube is connected with the power ground of the BUCK converter after passing through the third resistor;
the grid electrode of the eleventh NMOS tube is connected with the grid electrode of the twelfth NMOS tube and the second control signal, and the drain electrode of the eleventh NMOS tube is connected with the third current source and is connected with the power ground of the BUCK converter after passing through the sixth resistor;
the second control signal is in anti-phase with the first control signal;
the source electrode of the seventh NMOS tube is connected with the source electrode of the twelfth NMOS tube and the second input end of the comparator module, and the drain electrode of the seventh NMOS tube is connected with the switching node signal of the BUCK converter after passing through a fourth resistor;
and the drain electrode of the twelfth NMOS tube is connected with the power ground of the BUCK converter after passing through the seventh resistor.
Specifically, the comparator module further comprises a first diode, a second diode, a fourth NMOS transistor, a fifth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a fourth NPN type triode, a fifth NPN type triode, an eighth resistor, and a ninth resistor,
the grid electrode of the fourth NMOS tube is connected with the first power supply voltage, the source electrode of the fourth NMOS tube is connected with the collector electrode of the first NPN type triode, the cathode of the first diode and the anode of the second diode, and the drain electrode of the fourth NMOS tube is connected with the base electrode of the fourth NPN type triode and is connected with the second power supply voltage after passing through the eighth resistor;
the grid electrode of the fifth NMOS tube is connected with the first power supply voltage, the source electrode of the fifth NMOS tube is connected with the collector electrode of the second NPN type triode, the anode of the first diode and the cathode of the second diode, and the drain electrode of the fifth NMOS tube is connected with the base electrode of the fifth NPN type triode and is connected with the second power supply voltage after passing through a ninth resistor;
the grid-drain short circuit of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube and the collector electrode of the fourth NPN type triode, and the source electrode of the third PMOS tube is connected with the source electrodes of the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube and is connected with the first power supply voltage;
the grid electrode of the first PMOS tube is connected with the grid electrode and bias voltage of the second PMOS tube, the source electrode of the first PMOS tube is connected with the drain electrode of the fourth PMOS tube, and the drain electrode of the first PMOS tube is connected with the drain electrode of the ninth NMOS tube and outputs the comparison result of the comparator module;
the grid-drain short circuit of the tenth NMOS tube is connected with the grid electrode of the ninth NMOS tube and the drain electrode of the second PMOS tube, and the source electrode of the tenth NMOS tube is connected with the source electrode of the ninth NMOS tube and the power ground of the zero-crossing detection circuit;
the drain electrode of the fifth PMOS tube is connected with the source electrode of the second PMOS tube, and the grid electrode of the fifth PMOS tube is connected with the grid electrode and the drain electrode of the sixth PMOS tube and the collector electrode of the fifth NPN type triode;
and the emitting electrodes of the fourth NPN triode and the fifth NPN triode are connected with the third output end of the bias module.
Specifically, the first PMOS transistor, the second PMOS transistor, the ninth NMOS transistor, and the tenth NMOS transistor are high voltage tolerant devices.
Specifically, the bias module comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, an eighth NMOS transistor, a first resistor, a second resistor, a fifth resistor, a first current source, a second current source and a third NPN-type triode,
the grid electrode of the second NMOS tube is connected with the grid electrode and the drain electrode of the first NMOS tube, the grid electrode of the third NMOS tube and the first current source, the drain electrode of the second NMOS tube is used as a third output end of the bias module, and the source electrode of the second NMOS tube is connected with the source electrodes of the first NMOS tube and the third NMOS tube and is connected with the power ground of the zero-crossing detection circuit;
a base electrode and a collector electrode of the third NPN type triode are connected with a second current source, one end of the first resistor and one end of the second resistor, and an emitting electrode of the third NPN type triode is connected with a source electrode of the eighth NMOS tube;
the other end of the first resistor is used as a first output end of the bias module, and the other end of the second resistor is used as a second output end of the bias module and is connected with a drain electrode of a third NMOS tube;
and the grid electrode of the eighth NMOS tube is connected with the first power supply voltage, and the drain electrode of the eighth NMOS tube is connected with the power ground of the BUCK converter after passing through a fifth resistor.
Specifically, the bias module further includes a first capacitor, and the first capacitor is connected between the base of the third NPN transistor and the power ground of the BUCK converter.
Specifically, the eighth NMOS transistor is a high voltage tolerant device.
The invention has the beneficial effects that: according to the invention, the turning point of the zero-crossing detection circuit is adjusted by setting the error between the base voltage of the first NPN type triode and the base voltage of the second NPN type triode, so that the turning point can be adjusted as required; the double power supply and the output shaping module are designed, so that the voltage change range of the A point of the comparator during the turnover can be effectively reduced, the response speed of the zero-crossing detection circuit is improved, and the double power supply and the output shaping module have the characteristics of low direct-current detuning amount and low turnover delay.
Drawings
FIG. 1 is a power topology diagram of a BUCK converter.
Fig. 2 is a specific circuit diagram of a zero-crossing detection circuit suitable for a BUCK converter according to an embodiment of the present invention.
Detailed Description
The technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.
The zero-crossing detection circuit provided by the invention determines when a signal for turning off a lower power tube is generated by detecting and comparing the voltage information at the switching node SW of the BUCK converter with the power ground PGND of the BUCK converter. When the synchronous rectifier (i.e. the lower power tube) of the BUCK converter is turned on and the current flows in the forward direction, the voltage value of the switch node SW is IL*Rds,onIn which ILIs an inductive current, Rds,onThe on-resistance of the lower power transistor, therefore, when the switch node SW is close to 0 (i.e. PGND of the BUCK converter), the zero-crossing detection circuit is turned over to generate a signal for turning off the lower power transistor, and ideally, the lower power transistor is just turned off when the inductor current crosses zeroAnd (5) closing. The zero-crossing detection circuit provided by the invention comprises a bias module, a sampling module, a comparator module and an output shaping module, wherein the bias module is used for providing bias for the comparator module, and an implementation structure of the bias module is provided as shown in fig. 2 and comprises a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, an eighth NMOS tube N8, a first resistor R1, a second resistor R2, a fifth resistor R5, a first current source IBIAS1A second current source IBIAS2A third NPN type triode Q3, wherein the grid electrode of the second NMOS tube N2 is connected with the grid electrode and the drain electrode of the first NMOS tube N1, the grid electrode of the third NMOS tube N3 and the first current source IBIAS1The drain of the bias module is used as a third output end of the bias module, and the source of the bias module is connected with the sources of the first NMOS tube N1 and the third NMOS tube N3 and is connected with the power ground of the zero-crossing detection circuit; the base and the collector of the third NPN type triode Q3 are connected with a second current source IBIAS2One end of the first resistor R1 and one end of the second resistor R2, and the emitter of the first resistor R1 is connected with the source of the eighth NMOS transistor N8; the other end of the first resistor R1 is used as a first output end of the bias module, and the other end of the second resistor R2 is used as a second output end of the bias module and is connected with the drain electrode of the third NMOS transistor N3; the gate of the eighth NMOS transistor N8 is connected to the first power voltage, and the drain thereof is connected to the power ground PGND of the BUCK converter through the fifth resistor R5.
Ideally, it should be ensured that the first output terminal voltage of the bias module is the same as the second output terminal voltage (V2-V3), that is, the base voltages of the two BJT transistors, the first NPN transistor Q1 and the second NPN transistor Q2, are equal to make the switching point of the comparator module PGND-SW 0, however, the delay of the zero-crossing detection circuit itself and the delay from the output of the zero-crossing detection circuit to the complete turn-off of the BUCK converter lower power transistor cannot be ignored, so the present invention may cause a certain amount of error between V2 and V3 by flowing the bias current generated by the third NMOS transistor N3 through the second resistor R2, thereby causing the switching point to move forward to cancel the delay of the response, where the amount of forward movement may be represented as I3N3R2，IN3Is the current flowing through the third NMOS transistor N3, R2Is the resistance of the second resistor R2.
In some embodiments, the eighth NMOS transistor N8 may be set to high voltageAnd a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7 are arranged to reduce leakage current. In some embodiments, a filter capacitor, i.e., a first capacitor C1, may be further disposed in the bias module, and the first capacitor C1 is connected between the base of the third NPN transistor Q3 and the power ground PGND of the BUCK converter. The first capacitor C1 plays a role of filtering to stabilize the base voltage of the third NPN transistor Q3, i.e., V1, (I) V1 ═ V2 ═ V (I)BIAS2-IN3)*R5+VBE3>Vth1In which V isth1The BE junction of the first NPN transistor Q1 is conducted, so that the second current source IBIAS2The base bias voltages of the first transistor Q1 and the second transistor Q2 can be adjusted to make the circuit work normally, and meanwhile, a proper second current source I is arrangedBIAS2V2 can be made to be only slightly larger than Vth1And the current value of the third resistor R3 is reduced, namely, the power consumption of the circuit is reduced.
The sampling module is used for sampling a power ground PGND of the BUCK converter and connecting the PGND to a first input end of the comparator module when an upper power tube of the BUCK converter is closed and a lower power tube of the BUCK converter is opened, and sampling a switch node SW signal of the BUCK converter and connecting the switch node SW signal to a second input end of the comparator module. One implementation form of the sampling module is shown in fig. 2, and includes a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a third resistor R3, a fourth resistor R4, a sixth resistor R6, a seventh resistor R7, and a third current source IBIAS3The sixth NMOS transistor N6, the seventh NMOS transistor N7, the eleventh NMOS transistor N11 and the twelfth NMOS transistor N12 are logic-controlled high-voltage resistant devices; the gate of the sixth NMOS transistor N6 is connected to the gate of the seventh NMOS transistor N7 and the first control signal SLThe source of the comparator module is connected with the source of an eleventh NMOS transistor N11 and the first input end of the comparator module, and the drain of the comparator module is connected with the power ground PGND of the BUCK converter after passing through a third resistor R3; the gate of the eleventh NMOS transistor N11 is connected to the gate of the twelfth NMOS transistor N12 and the second control signal SL', its drain is connected to a third current source IBIAS3The power ground PGND of the BUCK converter is connected behind the sixth resistor R6; second control signal SL' with a first control signal SLInverting; the source electrode of the seventh NMOS transistor N7 is connected with the source electrode of the twelfth NMOS transistor N12 and the second input end of the comparator module, and the drain electrode of the seventh NMOS transistor N7 is connected with a switch node SW signal of the BUCK converter after passing through a fourth resistor R4; the drain of the twelfth NMOS transistor N12 is connected to the power ground PGND of the BUCK converter through a seventh resistor R7.
The sampling module is controlled by a first control signal SLAnd a second control signal SL' control whether SW and PGND are connected to the comparator or PGND, PGND and the third current source IBIAS3And accessing a comparator module. Two cases are included: (1) when the upper power tube is turned on and the lower power tube is turned off, the first control signal SL0, second control signal SL' -1; (2) when the upper power tube is closed and the lower power tube is opened, the first control signal SL1, the second control signal SL' -0. For case (1), the eleventh NMOS transistor N11 and the twelfth NMOS transistor N12 are turned on, the power ground PGND of the BUCK converter and the third current source IBIAS3The first input end of the comparator module is connected through an eleventh NMOS tube N11, the power ground PGND of the BUCK converter is connected through a twelfth NMOS tube N12 to the second input end of the comparator module, and the third current source I is connectedBIAS3The purpose of this is to make the emitter voltage of the first NPN transistor Q1 higher than the emitter voltage of the second NPN transistor Q2 during the duration of condition (1), so that the comparator block tends to pull high towards point a, i.e. the output of the comparator block, so that at the instant of switching to condition (2), the first control signal S is switched toLRising to 1, the seventh PMOS transistor P7 is turned off, and the tendency of the comparator module to pull up the point a prevents the point a from being pulled down to generate the zero crossing detection output signal ZVS _ out of the power transistor under the turn-off. For case (2), the sixth NMOS transistor N6 and the seventh NMOS transistor N7 are turned on, the power ground PGND of the BUCK converter is connected to the first input terminal of the comparator module through the sixth NMOS transistor N6, the switch node SW signal of the BUCK converter is connected to the second input terminal of the comparator module through the seventh NMOS transistor N7, the detection process starts, and the zero crossing detection output signal ZVS _ out is turned high when the switch node SW signal is gradually raised from a negative value to a turning point.
Comparator module obtaining BUCK conversionThe error information of the power ground of the device and the switch node signal of the BUCK converter is converted into a comparison result represented by high and low levels and is output to the output shaping module, as shown in fig. 2, an implementation circuit of the comparator module is provided, which includes a first diode D1, a second diode D2, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a ninth NMOS transistor N9, a tenth NMOS transistor N10, a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a first NPN transistor Q1, a second NPN transistor Q2, a fourth NPN transistor Q4, a fifth NPN transistor Q5, an eighth resistor R8, and a ninth resistor R9, a gate of the fourth NMOS transistor N4 is connected to a first power voltage VCC, a source thereof is connected to a collector of the first NPN transistor Q1, a cathode of the first diode D1 and an anode of the second diode D2, the drain of the third NPN type triode is connected with the base electrode of the fourth NPN type triode Q4 and is connected with a second power voltage VCC1 after passing through an eighth resistor R8; the gate of the fifth NMOS transistor N5 is connected to the first power voltage VCC, the source thereof is connected to the collector of the second NPN transistor Q2, the anode of the first diode D1 and the cathode of the second diode D2, and the drain thereof is connected to the base of the fifth NPN transistor Q5 and to the second power voltage VCC1 after passing through the ninth resistor R9; the gate-drain short circuit of the third PMOS transistor P3 is connected with the gate of the fourth PMOS transistor P4 and the collector of the fourth NPN triode Q4, and the source of the third PMOS transistor P3 is connected with the sources of the fourth PMOS transistor P4, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 and is connected with the first power supply voltage VCC; the grid electrode of the first PMOS tube P1 is connected with the grid electrode of the second PMOS tube P2 and the bias voltage VBIASThe source electrode of the comparator is connected with the drain electrode of the fourth PMOS tube P4, and the drain electrode of the comparator is connected with the drain electrode of the ninth NMOS tube N9 and outputs the comparison result of the comparator module; the grid-drain short circuit of the tenth NMOS transistor N10 is connected with the grid electrode of the ninth NMOS transistor N9 and the drain electrode of the second PMOS transistor P2, and the source electrode of the tenth NMOS transistor N10 is connected with the source electrode of the ninth NMOS transistor N9 and the power ground of the zero-crossing detection circuit; the drain electrode of the fifth PMOS transistor P5 is connected to the source electrode of the second PMOS transistor P2, and the gate electrode thereof is connected to the gate electrode and the drain electrode of the sixth PMOS transistor P6 and the collector electrode of the fifth NPN transistor Q5; and the emitters of the fourth NPN triode Q4 and the fifth NPN triode are connected with the third output end of the bias module.
When the detection process starts, the voltage error information of the power ground PGND and the switch node SW from the BUCK converter is converted into current error information through the first NPN transistor Q1 and the second NPN transistor Q2, and is converted into error voltage information through the load, i.e., the eighth resistor R8 and the ninth resistor R9, and the error voltage information is reflected on the bases of the fourth NPN transistor Q4 and the fifth NPN transistor Q5, and then the error information is converted into high and low levels at a point a through a full differential structure formed by the ninth NMOS transistor N9, the tenth NMOS transistor N10, the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, the fourth PMOS transistor P4, the fifth PMOS transistor P5, and the sixth PMOS transistor P6 and is output to the output shaping module.
The first PMOS transistor P1, the second PMOS transistor P2, the ninth NMOS transistor N9, and the tenth NMOS transistor N10 may be high voltage transistors to increase the impedance at point a and reduce the offset of the comparator, and the first PMOS transistor P1, the second PMOS transistor P2, the ninth NMOS transistor N9, and the tenth NMOS transistor N10 may also be replaced by low voltage transistors with longer channel length. The eighth resistor R8 and the ninth resistor R9 serve as load resistors for the first NPN transistor Q1 and the second NPN transistor Q2, and the reason why the resistors are used instead of the MOS transistors in this embodiment is that the former provides a faster response speed. The purpose of the first diode D1 and the second diode D2 is to make the voltage difference between V5 (the collector voltage of the first NPN transistor Q1) and V4 (the collector voltage of the second NPN transistor Q2) not exceed the turn-on voltage V of the diodesFThe response speed of the comparator can be improved.
The output shaping module provided by the invention can effectively reduce the voltage change range of the point A when the comparator is turned over and improve the response speed of the zero-crossing detection circuit besides shaping the voltage information of the point A. As shown in fig. 2, the output shaping module includes a first inverter INV1, a second inverter INV2, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a thirteenth NMOS transistor N13, and a fourteenth NMOS transistor N14, power supplies of the first inverter INV1 and the second inverter INV2 are a second power voltage VCC1, a power supply of the zero-crossing detection circuit is a first power voltage VCC, and a voltage value of the first power voltage VCC is higher than a voltage value of the second power voltage VCC 1; the grid of the seventh PMOS tube P7 is connected with the first control signal SLA source connected to a second power supply voltage VCC1, and a drain connected to a first inverting terminalThe input end of the INV1 is connected with the comparison result of the comparator module as the input end of the output shaping module; the input end of the second inverter INV2 is connected to the output end of the first inverter INV1 and the gate of the fourteenth NMOS transistor N14, and the output end thereof is connected to the gate of the thirteenth NMOS transistor N13; the grid electrode of the eighth PMOS tube P8 is connected with the drain electrode of the ninth PMOS tube P9 and the drain electrode of the fourteenth NMOS tube N14, the source electrode of the eighth PMOS tube P8 is connected with the source electrode of the ninth PMOS tube P9 and the first power supply voltage VCC, and the drain electrode of the eighth PMOS tube P9 and the drain electrode of the thirteenth NMOS tube N13 are connected as the output end of the zero-crossing detection circuit; the sources of the thirteenth NMOS transistor N13 and the fourteenth NMOS transistor N14 are connected to the power ground of the zero-cross detection circuit.
When in the stage of the upper power transistor being turned on and the lower power transistor being turned off, the seventh PMOS transistor P7 may pull up the point a to the second power voltage VCC1 instead of the first power voltage VCC, and the voltage value of the first power voltage VCC is higher than the second power voltage VCC1, because the power voltages of the first inverter INV1 and the second inverter INV2 are also the second power voltage VCC1 and much higher than the threshold voltages of the thirteenth NMOS transistor N13 and the fourteenth NMOS transistor N14, although the second power voltage VCC1 is lower than the first power voltage VCC, the point a may be recognized as a high level instead of a middle level or a low level. When the lower power tube is switched on and the upper power tube is switched off, the seventh PMOS tube P7 is closed, and the voltage of the point A is changed from VBIAS+VTHP1Determination of VTHP1Is the threshold voltage of the first PMOS transistor P1, and VBIAS+VTHP1Approximately equal to VCC1<VCC, so when reaching the upset point the voltage of A point is pulled down rather than VCC from VCC1, the voltage difference between before and after upset diminishes like this, and the required time of upset completion reduces, effectively improves detection speed. The inverter formed by the eighth PMOS transistor P8, the ninth PMOS transistor P9, the thirteenth NMOS transistor N13 and the fourteenth NMOS transistor N14 can raise the logic high level from VCC1 to VCC for outputting, so as to drive the subsequent logic circuit.
In summary, compared with the conventional zero-crossing detection comparator, the zero-crossing detection circuit applicable to the BUCK converter provided by the invention can adjust the detuning amount according to the requirement so as to change the turning point, and has a very small direct-current detuning amount; meanwhile, two power supply voltages and an output shaping module with a special circuit design are adopted, so that the transmission delay of the invention can be effectively reduced.
It will be appreciated by those of ordinary skill in the art that the foregoing examples are intended to assist the reader in understanding the principles of the invention, and are to be construed as being without limitation to such specifically recited examples and embodiments. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.

Claims (7)

1. A zero-crossing detection circuit suitable for a BUCK converter comprises an upper power tube and a lower power tube, wherein a connection point of the upper power tube and the lower power tube is a switch node;
the zero-crossing detection circuit comprises a bias module, a sampling module, a comparator module and an output shaping module,
the sampling module is used for sampling the power ground of the BUCK converter and accessing the power ground to the first input end of the comparator module when an upper power tube of the BUCK converter is closed and a lower power tube of the BUCK converter is opened, and sampling a switch node signal of the BUCK converter and accessing the switch node signal to the second input end of the comparator module;
the input pair transistors of the comparator module are a first NPN triode and a second NPN triode, an emitting electrode of the first NPN triode is used as a first input end of the comparator module, an emitting electrode of the second NPN triode is used as a second input end of the comparator module, and the comparator module is used for acquiring error information of a power ground of the BUCK converter and a switch node signal of the BUCK converter, converting the error information into a comparison result represented by a high level and a low level and outputting the comparison result to the output shaping module;
the bias module is used for providing bias for the comparator module, a first output end of the bias module is connected with a base electrode of a first NPN type triode, a second output end of the bias module is connected with a base electrode of a second NPN type triode, and a turning point of the zero-crossing detection circuit is adjusted by setting an error between a base electrode voltage of the first NPN type triode and a base electrode voltage of the second NPN type triode;
the output shaping module comprises a first phase inverter, a second phase inverter, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a thirteenth NMOS tube and a fourteenth NMOS tube, power supplies of the first phase inverter and the second phase inverter are second power supply voltage, a power supply of the zero-crossing detection circuit is first power supply voltage, and the voltage value of the first power supply voltage is higher than that of the second power supply voltage;
the grid electrode of the seventh PMOS tube is connected with the first control signal, the source electrode of the seventh PMOS tube is connected with the second power supply voltage, and the drain electrode of the seventh PMOS tube is connected with the input end of the first phase inverter and is used as the comparison result of the input end of the output shaping module which is connected with the comparator module;
when an upper power tube and a lower power tube of the BUCK converter are closed, the first control signal is at a high level, and when the upper power tube and the lower power tube of the BUCK converter are opened, the first control signal is at a low level;
the input end of the second phase inverter is connected with the output end of the first phase inverter and the grid electrode of the fourteenth NMOS tube, and the output end of the second phase inverter is connected with the grid electrode of the thirteenth NMOS tube;
the grid electrode of the eighth PMOS tube is connected with the drain electrode of the ninth PMOS tube and the drain electrode of the fourteenth NMOS tube, the source electrode of the eighth PMOS tube is connected with the source electrode of the ninth PMOS tube and the first power supply voltage, and the drain electrode of the eighth PMOS tube is connected with the grid electrode of the ninth PMOS tube and the drain electrode of the thirteenth NMOS tube and serves as the output end of the zero-crossing detection circuit;
and the source electrodes of the thirteenth NMOS tube and the fourteenth NMOS tube are connected with the power ground of the zero-crossing detection circuit.
2. The zero-crossing detection circuit suitable for the BUCK converter as claimed in claim 1, wherein the sampling module comprises a sixth NMOS transistor, a seventh NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a third resistor, a fourth resistor, a sixth resistor, a seventh resistor and a third current source, and the sixth NMOS transistor, the seventh NMOS transistor, the eleventh NMOS transistor and the twelfth NMOS transistor are high-voltage-resistant devices;
the grid electrode of the sixth NMOS tube is connected with the grid electrode of the seventh NMOS tube and the first control signal, the source electrode of the sixth NMOS tube is connected with the source electrode of the eleventh NMOS tube and the first input end of the comparator module, and the drain electrode of the sixth NMOS tube is connected with the power ground of the BUCK converter after passing through the third resistor;
the grid electrode of the eleventh NMOS tube is connected with the grid electrode of the twelfth NMOS tube and the second control signal, and the drain electrode of the eleventh NMOS tube is connected with the third current source and is connected with the power ground of the BUCK converter after passing through the sixth resistor;
the second control signal is in anti-phase with the first control signal;
the source electrode of the seventh NMOS tube is connected with the source electrode of the twelfth NMOS tube and the second input end of the comparator module, and the drain electrode of the seventh NMOS tube is connected with the switching node signal of the BUCK converter after passing through a fourth resistor;
and the drain electrode of the twelfth NMOS tube is connected with the power ground of the BUCK converter after passing through the seventh resistor.
3. The zero-crossing detection circuit for BUCK converter as claimed in claim 1 or 2, wherein the comparator module further comprises a first diode, a second diode, a fourth NMOS transistor, a fifth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a fourth NPN transistor, a fifth NPN transistor, an eighth resistor and a ninth resistor,
the grid electrode of the fourth NMOS tube is connected with the first power supply voltage, the source electrode of the fourth NMOS tube is connected with the collector electrode of the first NPN type triode, the cathode of the first diode and the anode of the second diode, and the drain electrode of the fourth NMOS tube is connected with the base electrode of the fourth NPN type triode and is connected with the second power supply voltage after passing through the eighth resistor;
the grid electrode of the fifth NMOS tube is connected with the first power supply voltage, the source electrode of the fifth NMOS tube is connected with the collector electrode of the second NPN type triode, the anode of the first diode and the cathode of the second diode, and the drain electrode of the fifth NMOS tube is connected with the base electrode of the fifth NPN type triode and is connected with the second power supply voltage after passing through a ninth resistor;
the grid-drain short circuit of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube and the collector electrode of the fourth NPN type triode, and the source electrode of the third PMOS tube is connected with the source electrodes of the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube and is connected with the first power supply voltage;
the grid electrode of the first PMOS tube is connected with the grid electrode and bias voltage of the second PMOS tube, the source electrode of the first PMOS tube is connected with the drain electrode of the fourth PMOS tube, and the drain electrode of the first PMOS tube is connected with the drain electrode of the ninth NMOS tube and outputs the comparison result of the comparator module;
the grid-drain short circuit of the tenth NMOS tube is connected with the grid electrode of the ninth NMOS tube and the drain electrode of the second PMOS tube, and the source electrode of the tenth NMOS tube is connected with the source electrode of the ninth NMOS tube and the power ground of the zero-crossing detection circuit;
the drain electrode of the fifth PMOS tube is connected with the source electrode of the second PMOS tube, and the grid electrode of the fifth PMOS tube is connected with the grid electrode and the drain electrode of the sixth PMOS tube and the collector electrode of the fifth NPN type triode;
and the emitting electrodes of the fourth NPN triode and the fifth NPN triode are connected with the third output end of the bias module.
4. The zero-crossing detection circuit suitable for the BUCK converter as claimed in claim 3, wherein the first PMOS transistor, the second PMOS transistor, the ninth NMOS transistor and the tenth NMOS transistor are high voltage tolerant devices.
5. The zero-crossing detection circuit for the BUCK converter as claimed in claim 3, wherein the bias module comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, an eighth NMOS transistor, a first resistor, a second resistor, a fifth resistor, a first current source, a second current source and a third NPN transistor,
the grid electrode of the second NMOS tube is connected with the grid electrode and the drain electrode of the first NMOS tube, the grid electrode of the third NMOS tube and the first current source, the drain electrode of the second NMOS tube is used as a third output end of the bias module, and the source electrode of the second NMOS tube is connected with the source electrodes of the first NMOS tube and the third NMOS tube and is connected with the power ground of the zero-crossing detection circuit;
a base electrode and a collector electrode of the third NPN type triode are connected with a second current source, one end of the first resistor and one end of the second resistor, and an emitting electrode of the third NPN type triode is connected with a source electrode of the eighth NMOS tube;
the other end of the first resistor is used as a first output end of the bias module, and the other end of the second resistor is used as a second output end of the bias module and is connected with a drain electrode of a third NMOS tube;
and the grid electrode of the eighth NMOS tube is connected with the first power supply voltage, and the drain electrode of the eighth NMOS tube is connected with the power ground of the BUCK converter after passing through a fifth resistor.
6. The zero-crossing detection circuit for the BUCK converter as recited in claim 5, wherein the bias module further comprises a first capacitor, and the first capacitor is connected between the base of the third NPN transistor and the power ground of the BUCK converter.
7. The zero-crossing detection circuit suitable for the BUCK converter as claimed in claim 5 or 6, wherein the eighth NMOS transistor is a high voltage resistant device.
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CN114337619A (en) * 2022-01-12 2022-04-12 电子科技大学 Reverse flow comparator for eliminating error turnover
CN114441842A (en) * 2022-01-17 2022-05-06 电子科技大学 Zero-crossing detection circuit for peak current mode control Buck converter
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CN107086793A (en) * 2017-06-19 2017-08-22 浙江大学 A kind of dynamic compesated control circuit for synchronous rectification power inverter
CN107132405A (en) * 2017-06-29 2017-09-05 英麦科（厦门）微电子科技有限公司 A kind of zero cross detection circuit for synchronous buck code converter
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CN112595886A (en) * 2020-12-16 2021-04-02 合肥工业大学 Low-power-consumption self-adaptive zero-crossing detection circuit
CN112595886B (en) * 2020-12-16 2022-06-07 合肥工业大学 Low-power-consumption self-adaptive zero-crossing detection circuit
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