CN111510118B - Low-power-consumption high-speed comparator - Google Patents
Low-power-consumption high-speed comparator Download PDFInfo
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- CN111510118B CN111510118B CN202010379102.4A CN202010379102A CN111510118B CN 111510118 B CN111510118 B CN 111510118B CN 202010379102 A CN202010379102 A CN 202010379102A CN 111510118 B CN111510118 B CN 111510118B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals
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Abstract
The invention discloses a low-power-consumption high-speed comparator which comprises four PMOS (P-channel metal oxide semiconductor) tubes, four NMOS (N-channel metal oxide semiconductor) tubes, two first buffers, two OR gates, a first analog signal input end, a second signal input end, a first comparison result output end, a second comparison result output end and a clock control end. When the clock control terminal qamp is at a high level, the comparator is in a reset state. When the clock control terminal qamp jumps from a high level to a low level, the comparator is in a comparison state. And after the comparator completes comparison, the comparator enters a latching state and keeps the output result unchanged. The comparator of the present invention can also obtain a smaller input mismatch voltage by increasing the size of the input tube. The high-speed comparator of the invention fully utilizes the characteristic of high characteristic frequency of the NMOS tube, and improves the conversion speed of the comparator. And the circuit has simple structure and is suitable for a high-speed conversion circuit.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to a low-power-consumption high-speed comparator.
Background
Clocked comparators are commonly used in analog-to-digital converters. Analog-to-digital converters operate at increasingly faster speeds, requiring comparator circuits with faster slew rates. Conventional comparator circuits typically have a pre-amplification circuit. Although the input mismatch voltage of the comparator can be reduced, the maximum operation speed of the comparator is reduced and the power consumption of the circuit is increased.
Disclosure of Invention
To overcome the problems in the prior art, it is an object of the present invention to provide a low power consumption high speed comparator circuit that can achieve a high speed slew rate with less power consumption.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a low-power-consumption high-speed comparator comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first OR gate, a second OR gate, a first analog signal input end, a second analog signal input end, a first comparison result output end, a second comparison result output end and a clock control end;
the first analog signal input end is connected with a grid electrode of a first PMOS (P-channel metal oxide semiconductor) tube, a high-voltage source is connected with a source electrode of a first PMOS tube PM0 and a source electrode of a second PMOS tube PM1, a drain electrode of the first PMOS tube is connected with a source electrode of a third PMOS tube, a grid electrode of the third PMOS tube is connected with an output end of a second OR gate, and a drain electrode of the third PMOS tube is connected with a grid electrode of a second NMOS tube, a drain electrode of the first NMOS tube, a drain electrode of the third NMOS tube, a first comparison result output end and a first input end of a first OR gate;
the source electrode of the second NMOS tube, the source electrode of the first NMOS tube and the source electrode of the third NMOS tube are all grounded;
the second analog signal input end is connected with the grid electrode of a second PMOS tube, the drain electrode of the second PMOS tube is connected with the source electrode of a fourth PMOS tube, the grid electrode of the fourth PMOS tube is connected with the output end of a first OR gate, and the drain electrode of the fourth PMOS tube is connected with the grid electrode of a first NMOS tube, the drain electrode of the second NMOS tube, the drain electrode of the fourth NMOS tube, the second comparison result output end and the first input end of the second OR gate;
the source electrode of the first NMOS tube, the source electrode of the second NMOS tube and the source electrode of the fourth NMOS tube are all grounded;
the clock control end is connected with the second input end of the first OR gate, the grid electrode of the third NMOS tube, and the grid electrode of the fourth NMOS tube and the second input end of the second OR gate.
The invention is further improved in that the drain electrode of the third PMOS tube, the gate electrode of the second NMOS tube, the drain electrode of the first NMOS tube, the drain electrode of the third NMOS tube, the input end of the first buffer and the first input end of the first OR gate are connected with the output end of the first comparison result through the first buffer.
The invention has the further improvement that the drain electrode of the fourth PMOS tube, the grid electrode of the first NMOS tube, the drain electrode of the second NMOS tube, the drain electrode of the fourth NMOS tube, the input end of the second buffer and the first input end of the second OR gate are connected with the output end of the second comparison result through the second buffer.
The invention has the further improvement that a third node is connected with the drain electrode of a third PMOS tube, the grid electrode of a second NMOS tube, the drain electrode of a first NMOS tube, the drain electrode of a third NMOS tube, the input end of a first buffer and the first input end of a first OR gate;
the fourth node is connected with the drain electrode of the fourth PMOS tube, the grid electrode of the first NMOS tube, the drain electrode of the second NMOS tube, the drain electrode of the fourth NMOS tube, the input end of the second buffer and the first input end of the second OR gate;
the fourth node is charged faster than the third node if the signal at the first analog signal input is higher than the signal at the second analog signal input.
A further improvement of the present invention is that the output of the first OR gate OR0 serves as the fifth node, and the output of the second OR gate OR1 serves as the sixth node;
when the clock control end signal is at a high level, the fifth node and the sixth node are driven to be pulled up to a power supply voltage through the first OR gate and the second OR gate; the third PMOS tube and the fourth PMOS tube are in a turn-off state; meanwhile, the third node and the fourth node are pulled down to the ground by the third NMOS tube and the fourth NMOS tube; the first comparison result output end and the second comparison result output end both output low levels.
The invention is further improved in that the charging capacity of the first PMOS tube and the second PMOS tube is changed by adjusting the direct current working level of the signal of the first analog signal input end and the signal of the second analog signal input end.
The invention has the further improvement that when the clock control end jumps from high level to low level, the power supply charges the third node and the fourth node through the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube; and pulling up the third node and the fourth node.
The invention is further improved in that when the clock control terminal jumps from a high level to a low level, the potentials of the fifth node and the sixth node are pulled down to the ground.
Compared with the prior art, the invention has the following beneficial effects: in the invention, the first NMOS tube NM0 and the second NMOS tube NM1 form a positive feedback loop, the positive feedback loop of the comparator only uses NMOS tubes with high characteristic frequency, and the PMOS tube provides large current for the positive feedback loop, thereby improving the conversion rate of the comparator. And the clock control terminal qamp is used for controlling the working state of the comparator. When the clock control terminal qamp is at a high level, the comparator is in a reset state. When the clock control terminal qamp jumps from a high level to a low level, the comparator is in a comparison state. And after the comparator completes comparison, the comparator enters a latching state and keeps the output result unchanged. The comparator of the present invention can also obtain a smaller input mismatch voltage by increasing the size of the input tube. The high-speed comparator of the invention fully utilizes the characteristic of high characteristic frequency of the NMOS tube, and improves the conversion speed of the comparator. And the circuit has simple structure and is suitable for a high-speed conversion circuit.
Drawings
FIG. 1 is a circuit structure of a low power consumption high speed comparator according to the present invention;
FIG. 2 is a timing diagram illustrating the operation of the circuit of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
The circuit structure of the invention is shown in fig. 1, and comprises four PMOS transistors, which are respectively a first PMOS transistor PM0, a second PMOS transistor PM1, a third PMOS transistor PM2, and a fourth PMOS transistor PM3, four NMOS transistors, which are respectively a first NMOS transistor NM0, a second NMOS transistor NM1, a third NMOS transistor NM2, and a fourth NMOS transistor NM3, two buffers, which are respectively a first buffer BUF0 and a second buffer BUF1, and two OR gates, which are respectively a first OR gate OR0 and a second OR gate OR 1. The first node n0, the third node n1, the fifth node n2, the second node p0, the fourth node p1, and the sixth node p2 are internal nodes. A first analog signal input terminal vip, and a second analog signal input terminal vin. A first comparison result output terminal von, a second comparison result output terminal vop, and a clock control terminal qamp.
The first analog signal input end vip is connected with the grid electrode of the first PMOS transistor PM0, and the high-voltage source is connected with the source electrode of the first PMOS transistor PM0 and the source electrode of the second PMOS transistor PM 1. The drain of the first PMOS transistor PM0 is connected to the source of the third PMOS transistor PM2, the gate of the third PMOS transistor PM2 is connected to the output of the second OR gate OR1, and the drain of the third PMOS transistor PM2 is connected to the gate of the second NMOS transistor NM1, the drain of the first NMOS transistor NM0, the drain of the third NMOS transistor NM2, the input of the first buffer BUF0, and the first input of the first OR gate OR 0.
The source of the second NMOS transistor NM1, the source of the first NMOS transistor NM0, and the source of the third NMOS transistor NM2 are all grounded.
The first comparison result output von is connected to an output of the first buffer BUF 0.
The second analog signal input end vin is connected with the gate of the second PMOS transistor PM1, the drain of the second PMOS transistor PM1 is connected with the source of the fourth PMOS transistor PM3, the gate of the fourth PMOS transistor PM3 is connected with the output end of the first OR gate OR0, and the drain of the fourth PMOS transistor PM3 is connected with the gate of the first NMOS transistor NM0, the drain of the second NMOS transistor NM1, the drain of the fourth NMOS transistor NM3, the input end of the second buffer BUF1 and the first input end of the second OR gate OR 1.
The source of the first NMOS transistor NM0, the source of the second NMOS transistor NM1, and the source of the fourth NMOS transistor NM3 are all grounded.
The second comparison result output vop is connected to an output of the second buffer BUF 1.
The clock control terminal qamp is connected to a second input terminal of the first OR gate OR0, a gate of the third NMOS transistor NM2, a gate of the fourth NMOS transistor NM3, and a second input terminal of the second OR gate OR 1.
The first node n0 is connected to the drain of the first PMOS transistor PM0 and the source of the third PMOS transistor PM 2.
The second node p0 is connected to the drain of the second PMOS transistor PM1 and the source of the fourth PMOS transistor PM 3.
The third node n1 is connected to the drain of the third PMOS transistor PM2, the gate of the second NMOS transistor NM1, the drain of the first NMOS transistor NM0, the drain of the third NMOS transistor NM2, the input terminal of the first buffer BUF0, and the first input terminal of the first OR gate OR 0.
The fourth node p1 is connected to the drain of the fourth PMOS transistor PM3, the gate of the first NMOS transistor NM0, the drain of the second NMOS transistor NM1, the drain of the fourth NMOS transistor NM3, the input of the second buffer BUF1, and the first input of the second OR gate OR 1.
The output terminal of the first OR gate OR0 serves as the fifth node n2, and the output terminal of the second OR gate OR1 serves as the sixth node p 2.
The first PMOS transistor PM0 and the second PMOS transistor PM1 are input transistors of the comparator. The lower the input common mode voltage of the tube, the faster the comparison speed of the comparator. The larger the sizes of the first PMOS transistor PM0 and the second PMOS transistor PM1 are, the lower the equivalent input mismatch voltage of the comparator is. When the clock control terminal qamp signal jumps from high level to low level, the high voltage source charges the third node n1 and the fourth node p1 through the first PMOS transistor PM0, the second PMOS transistor PM1, the third PMOS transistor PM2 and the fourth PMOS transistor PM3, and the voltage values of the first analog signal input end vip and the second analog signal input end vin respectively determine the charging speeds of the third node n1 and the fourth node p 1. If the signal of the first analog signal input vip is higher than the signal of the second analog signal input vin, the fourth node p1 is charged faster than the third node n 1.
The third PMOS pipe PM2 and the fourth PMOS pipe PM3 are used for isolating the first node n0 and the third node n1, and the second node p0 and the fourth node p 1. When the comparator is in a reset state, the first node n0 and the second node p0 are power voltages, and the third node n1 and the fourth node p1 are ground potentials. When the comparator is in the latched state, one of the nodes n1, p1 is at the supply voltage and the other is at ground. The first node n0 and the second node p0 are both power supply voltage potentials, so the third PMOS transistors PM2 and PM3 are required to isolate the first node n0 and the third node n1 from the second node p0 and the fourth node p 1.
The third NMOS transistor NM2 and the fourth NMOS transistor NM2NM3 are used in a reset comparator. When the clock terminal qamp signal is at a high level, the fifth node n2 and the sixth node p2 are driven to be pulled up to the power voltage by the first OR gate OR0 and the second OR gate OR 1. The third and fourth PMOS transistors PM2 and PM3 are in an off state. Meanwhile, the third node n1 and the fourth node p1 are pulled down to the ground by the third NMOS transistor NM2 and the fourth NMOS transistor NM 3. The first comparison result output terminal von and the second comparison result output terminal vop of the comparator both output a low level. The comparator is in a reset state.
The first buffer BUF0 is configured to isolate the third node n1 from the first comparison result output von, so as to avoid interference of a subsequent circuit on the positive feedback loop and influence on the comparison process of the comparator.
The second buffer BUF1 is configured to isolate the fourth node p1 from the second comparison result output vop, so as to avoid interference of a subsequent circuit on the positive feedback loop and influence on the comparison process of the comparator.
The first OR gate OR0 and the second OR gate OR1 are used for controlling the gate voltages of the third PMOS transistor PM2 and the fourth PMOS transistor PM 3. When the comparator is in the reset state, the outputs of the first OR gate OR0 and the second OR gate OR1 are all high. When the comparator is in the latch state, if the third node n1 is high, the output of the first OR gate OR0 is high, and the fourth PMOS transistor PM3 is in the off state. If the first node p1 is high, the output of the second OR gate OR1 is high, and the third PMOS transistor PM2 is in an off state.
The first OR gate OR0 and the second OR gate OR1 have higher logic flip thresholds.
FIG. 2 shows the operation timing of the circuit of the present invention, when the timing control qamp is high, the comparator is in a reset state. When the clock control terminal qamp is low, the comparator is in a latched state. When the signal of the clock control terminal jumps from a high level to a low level, the comparator is in a state of judging the signal input to the first analog signal input terminal vip and the signal input to the second analog signal input terminal vin.
The first and second PMOS transistors PM0 and PM1 in fig. 1 are input transistors of the comparator, and the charging capability of the first and second PMOS transistors PM0 and PM1 can be changed by adjusting the dc operating level of the signal at the first and second analog signal input terminals vip and vin. Greater charging capability may result in a smaller transition time. The first and second PMOS transistors PM0 and PM1 also determine the input mismatch voltage of the comparator. Larger transistor sizes may result in smaller mismatch voltages.
When the clock terminal qamp transits from a high level to a low level, the first PMOS transistor PM0 and the second PMOS transistor PM2 are connected in series and charge the third node n 1. The larger the size of the third PMOS transistor PM2, the faster the voltage ramp rate of the third node n 1. Similarly, the larger the size of the fourth PMOS transistor PM3, the faster the voltage at the first node p1 rises. However, if the sizes of the third PMOS transistor PM2 and the fourth PMOS transistor PM3 are too large, the layout parasitic capacitances of the third node n1 and the fourth node p1 are increased, and the switching speed of the comparator is reduced. Therefore, the first PMOS transistor PM0, the second PMOS transistor PM1, the third PMOS transistor PM2, and the fourth PMOS transistor PM3 may have the same size and use source/drain dose. On one hand, the layout area can be reduced, and on the other hand, the parasitics of the first node n0 and the second node p0 can be reduced.
The first NMOS transistor NM0 and the second NMOS transistor NM1 form a positive feedback loop. When the clock control terminal qamp transits from a high level to a low level, the first PMOS transistor PM0, the second PMOS transistor PM1, the third PMOS transistor PM2 and the fourth PMOS transistor PM3 charge the third node n1 and the fourth node p 1. The third node n1 and the fourth node p1 can be pulled up quickly. The voltage values of the first and second analog signal input terminals vip and vin determine the charging speeds of the third and fourth nodes n1 and p1 during the charging process. The first PMOS transistor PM0, the second PMOS transistor PM1, the third PMOS transistor PM2, and the fourth PMOS transistor PM3 provide strong currents for the first NMOS transistor NM0 and the second NMOS transistor NM1, so that the positive feedback loop is driven to make a judgment quickly. In addition, only the NMOS tube is used in the positive feedback loop, so that the characteristic of high characteristic frequency of the NMOS tube can be fully utilized, and the conversion speed of the comparator is improved. The NMOS transistor has a higher characteristic frequency than the PMOS transistor. A larger transconductance can be obtained with less power consumption, resulting in a shorter switching time of the comparator. Although the PMOS tube and the NMOS tube can be used for taking current, the transconductance of the positive feedback loop is improved, and the load capacitance of the positive feedback node is increased. It is not advantageous to increase the slew rate of the comparator.
In the comparator circuit of the invention, after the positive feedback node compares the result, the third PMOS transistor PM2 OR the fourth PMOS transistor PM3 is turned off by the first OR gate OR0 and the second OR gate OR1, so that a current channel is prevented from being formed between the power supply and the ground.
The logic flip thresholds of the first OR gate OR0 and the second OR gate OR1 in fig. 1 are high, so as to avoid that the third PMOS transistor PM2 and the fourth PMOS transistor 3 are turned off simultaneously in the case that the third node n1 and the fourth node p1 have not compared the result yet.
When the clock terminal qamp is at a high level, the comparator is in a reset state, the first node n0 and the fourth node p1 are pulled up to the power voltage, and the third node n1 and the fourth node p1 are pulled down to the ground. The fifth node n2 and the sixth node p2 are at high level. The third and fourth PMOS transistors PM2 and PM3 isolate the internal first node n0, third node n1, second node p0 and fourth node p 1. When the clock control terminal qamp jumps to a low level, the potentials of the fifth node n2 and the sixth node p2 are pulled down to the ground, the third PMOS transistor PM2 and the fourth PMOS transistor PM3 are turned on, and the third node n1 and the fourth node p1 are charged. The first PMOS transistor PM0, the second PMOS transistor PM1, the third PMOS transistor PM2 and the fourth PMOS transistor PM3 at this time can provide strong current drive for the third node n1 and the fourth node p1, so that the comparison speed of the comparator is improved.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (8)
1. A low-power-consumption high-speed comparator is characterized by comprising a first PMOS (P-channel metal oxide semiconductor) transistor (PM0), a second PMOS transistor (PM1), a third PMOS transistor (PM2), a fourth PMOS transistor (PM3), a first NMOS (N-channel metal oxide semiconductor) transistor (NM0), a second NMOS transistor (NM1), a third NMOS (N-channel metal oxide semiconductor) transistor (NM2), a fourth NMOS transistor (NM3), a first OR gate (OR0), a second OR gate (OR1), a first analog signal input end (vip), a second analog signal input end (vin), a first comparison result output end (von), a second comparison result output end (vop) and a clock control end (qamp);
a first analog signal input end (vip) is connected with a grid electrode of a first PMOS (PM0), a high-voltage source is connected with a source electrode of a first PMOS (PM0) and a source electrode of a second PMOS (PM1), a drain electrode of the first PMOS (PM0) is connected with a source electrode of a third PMOS (PM2), a grid electrode of the third PMOS (PM2) is connected with an output end of a second OR gate (OR1), and a drain electrode of the third PMOS (PM2) is connected with a grid electrode of a second NMOS (NM1), a drain electrode of a first NMOS (NM0), a drain electrode of a third NMOS (NM2), a first comparison result output end (von) and a first input end of the first OR gate (OR 0);
the source electrode of the second NMOS transistor (NM1), the source electrode of the first NMOS transistor (NM0) and the source electrode of the third NMOS transistor (NM2) are all grounded;
a second analog signal input end (vin) is connected with a grid electrode of a second PMOS (PM1), a drain electrode of the second PMOS (PM1) is connected with a source electrode of a fourth PMOS (PM3), a grid electrode of the fourth PMOS (PM3) is connected with an output end of a first OR gate (OR0), and a drain electrode of the fourth PMOS (PM3) is connected with a grid electrode of a first NMOS (NM0), a drain electrode of a second NMOS (NM1), a drain electrode of the fourth NMOS (NM3), a second comparison result output end (vop) and a first input end of a second OR gate (OR 1);
the source electrode of the first NMOS transistor (NM0), the source electrode of the second NMOS transistor (NM1) and the source electrode of the fourth NMOS transistor (NM3) are all grounded;
the clock control terminal (qamp) is connected with the second input terminal of the first OR gate (OR0), the gate of the third NMOS transistor (NM2), and the gate of the fourth NMOS transistor (NM3) is connected with the second input terminal of the second OR gate (OR 1).
2. A low-power consumption high-speed comparator as claimed in claim 1, characterized in that the drain of the third PMOS transistor (PM2), the gate of the second NMOS transistor (NM1), the drain of the first NMOS transistor (NM0), the drain of the third NMOS transistor (NM2), the input of the first buffer (BUF0) and the first input of the first OR-gate (OR0) are connected to the first comparison result output (von) via the first buffer (BUF 0).
3. A low-power consumption high-speed comparator as claimed in claim 2, characterized in that the drain of the fourth PMOS transistor (PM3), the gate of the first NMOS transistor (NM0), the drain of the second NMOS transistor (NM1), the drain of the fourth NMOS transistor (NM3), the input of the second buffer (BUF1) and the first input of the second OR-gate (OR1) are connected to the second comparison result output (vop) via the second buffer (BUF 1).
4. A low power consumption high speed comparator according to claim 3, characterized in that the third node (n1) is connected to the drain of the third PMOS transistor (PM2), the gate of the second NMOS transistor (NM1), the drain of the first NMOS transistor (NM0), the drain of the third NMOS transistor (NM2), the input of the first buffer (BUF0) and the first input of the first OR gate (OR 0);
the fourth node (p1) is connected with the drain electrode of the fourth PMOS tube (PM3), the grid electrode of the first NMOS tube (NM0), the drain electrode of the second NMOS tube (NM1), the drain electrode of the fourth NMOS tube (NM3), the input end of the second buffer (BUF1) and the first input end of the second OR gate (OR 1);
if the signal at the first analog signal input terminal (vip) is higher than the signal at the second analog signal input terminal (vin), the fourth node (p1) is charged faster than the third node (n 1).
5. A low power consumption high speed comparator as claimed in claim 4, characterized in that the output of the first OR gate (OR0) is provided as the fifth node (n2), and the output of the second OR gate (OR1) is provided as the sixth node (p 2);
when the clock control terminal (qamp) signal is at a high level, the fifth node (n2) and the sixth node (p2) are driven to be pulled up to the power supply voltage through the first OR gate (OR0) and the second OR gate (OR 1); the third PMOS tube (PM2) and the fourth PMOS tube (PM3) are in an off state; meanwhile, the third node (n1) and the fourth node (p1) are pulled down to the ground by the third NMOS transistor (NM2) and the fourth NMOS transistor (NM 3); the first comparison result output terminal (von) and the second comparison result output terminal (vop) both output a low level.
6. A low power consumption high speed comparator according to claim 3, characterized in that the charging capability of the first PMOS transistor (PM0) and the second PMOS transistor (PM1) is changed by adjusting the dc operating level of the signal at the first analog signal input (vip) and the signal at the second analog signal input (vin).
7. A low-power-consumption high-speed comparator according to claim 4, characterized in that when the clock control terminal (qamp) jumps from high level to low level, the power supply charges the third node (n1) and the fourth node (p1) through the first PMOS transistor (PM0), the second PMOS transistor (PM1), the third PMOS transistor (PM2) and the fourth PMOS transistor (PM 3); the third node (n1) and the fourth node (p1) are pulled up.
8. A low-power-consumption high-speed comparator as claimed in claim 5, characterized in that when the clocked terminal (qamp) transitions from high to low, the potentials of the fifth node (n2) and the sixth node (p2) are pulled down to ground.
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| CN111510118A (en) | 2020-08-07 |
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