CN111431517B - Ultra-high-speed bootstrap switch circuit with embedded input buffer - Google Patents
Ultra-high-speed bootstrap switch circuit with embedded input buffer Download PDFInfo
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- CN111431517B CN111431517B CN202010378270.1A CN202010378270A CN111431517B CN 111431517 B CN111431517 B CN 111431517B CN 202010378270 A CN202010378270 A CN 202010378270A CN 111431517 B CN111431517 B CN 111431517B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/04—Modifications for accelerating switching
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K2017/6878—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors using multi-gate field-effect transistors
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Abstract
The invention discloses an ultra-high-speed bootstrap switch circuit embedded with an input buffer, which comprises an input NMOS (N-channel metal oxide semiconductor) tube, an input PMOS (P-channel metal oxide semiconductor) tube, a breakover switch NMOS tube and a clock control NMOS tube, wherein the input NMOS tube is connected with the input PMOS tube through a power supply line; the input end is connected with the grid of the input PMOS tube and the grid of the input NMOS tube; the high-voltage source is connected with a source electrode of an input PMOS tube, a grid electrode of a conduction switch NMOS tube and a drain electrode of a clock control NMOS tube through a first constant current source, and the grid electrode of the clock control NMOS tube is connected with a clock signal input end; the drain electrode of the input NMOS tube is connected with a high voltage source, and the signal output end is connected with the drain electrode of the conduction switch NMOS tube. According to the invention, the voltage of the bootstrap switch is raised by using the direct current voltage difference of the NMOS source electrode follower and the PMOS source electrode follower, so that a capacitor for raising the voltage of the switch is omitted. The invention not only has simple circuit structure, but also has high working state switching speed.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to an ultra-high-speed bootstrap switch circuit with an embedded input buffer.
Background
The operating speed of the input bootstrap switch of the analog-to-digital converter directly determines the conversion rate of the analog-to-digital converter. The conventional bootstrap switch needs to drive not only the sampling capacitor but also the gate of the bootstrap switch. When the slew rate of the analog-to-digital converter rises, the gate potential of the bootstrap switch needs to be raised in a very short time. This requires an input drive circuit having a large drive capability. This greatly increases the power consumption of the circuit. Moreover, high-speed sampling cannot necessarily be achieved. Conventional bootstrap switches also require one or more capacitors for raising the gate voltage of the bootstrap switch. This also does not facilitate the application of the bootstrap switch to a small-scale process.
Disclosure of Invention
In order to overcome the problems in the prior art, the invention aims to provide an ultra-high-speed bootstrap switch circuit with an embedded input buffer, which can realize high-speed working state switching, can also be reduced in equal proportion and is applied to smaller processes.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
the ultra-high-speed bootstrap switch circuit with the embedded input buffer comprises an input NMOS (N-channel metal oxide semiconductor) tube, an input PMOS (P-channel metal oxide semiconductor) tube, a conduction switch NMOS tube, a clock control NMOS tube, a first constant current source, a second constant current source, an input end, an output end, a clock control tube and a clock signal input end;
the input end is connected with the grid of the input PMOS tube and the grid of the input NMOS tube; the high-voltage source is connected with a source electrode of an input PMOS (P-channel metal oxide semiconductor) tube, a grid electrode of a conduction switch NMOS tube and a drain electrode of a clock control NMOS tube through a first constant current source, the grid electrode of the clock control NMOS tube is connected with a clock signal input end, and the drain electrode of the input PMOS tube and the source electrode of the clock control NMOS tube are grounded;
the drain electrode of the input NMOS tube is connected with the high-voltage source, the negative electrode of the second constant-current source is grounded, and the signal output end is connected with the drain electrode of the conduction switch NMOS tube.
The invention has the further improvement that when the clock signal input end is switched from high level to low level, the NMOS tube is switched from off state to on state, and the first node charges and discharges the output end.
The invention is further improved in that the first node is connected with the source electrode of the input NMOS tube, the source electrode of the conduction switch NMOS tube and the anode of the second constant current source, and the first node is lower than the potential of the input end by a gate-source voltage difference Vgsn of the NMOS tube.
The invention is further improved in that when the NMOS transistor of the conduction switch is in a conduction state, the potential of the output end is equal to the potential of the first node.
The invention has the further improvement that the connection position of the drain electrode of the clock control NMOS tube and the grid electrode of the conduction switch NMOS tube is used as a second node; when the clock signal input terminal is switched from the low level to the high level, the potential of the second node is 0.
The invention has the further improvement that when the clock signal input end is at high level, the NMOS tube of the conduction switch is in a conduction state, and the current on the second constant current source controls the NMOS tube to flow to the ground through the clock; the potential of the second node is 0; the NMOS tube of the conduction switch is in a closed state; the output terminal is in a high impedance state.
The invention is further improved in that when the clock signal input end is at low level, the clock control NMOS tube is in a closed state, the second node is higher than the potential of the input end by a grid-source voltage difference Vgsp of the PMOS tube, and the grid-source voltage difference of the conduction switch NMOS tube is Vgsn + Vgsp, wherein Vgsn is the grid-source voltage difference of the NMOS tube.
Compared with the prior art, the invention has the following beneficial effects:
when the bootstrap circuit is switched from a high-impedance state to an input following state, the PMOS source follower can quickly drive the node B, and the NMOS tube NM1 is turned on in a very short time. When the bootstrap circuit switches from the input follower state to the high impedance state, the NMOS transistor NM2 can also pull down the potential of the second node B to the ground quickly, turning off the NMOS transistor NM1 in a very short time. The circuit has high working state switching speed. The circuit of the invention does not use a capacitor device, can reduce the layout area, and can use a smaller layout area to obtain better performance under more advanced process. In addition, a source follower in the circuit can isolate the input signal from the bootstrap switch, and the interference of the switch signal to the input signal is avoided.
Drawings
FIG. 1 is a block diagram of an ultra-high speed bootstrap switch circuit with embedded input buffer according to the present invention;
FIG. 2 is a timing diagram of the operation of the bootstrap switch circuit of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
The circuit structure of the invention is shown in fig. 1, and comprises an input NMOS tube NM0, an input PMOS tube PM0, a conducting switch NMOS tube NM1, a clock control NMOS tube NM2, a first constant current source I0, a second constant current source I1, an input end vi, an output end vo, a clock control tube NM2 and a clock signal input end ck, wherein a first node a and a second node B are internal nodes of the circuit.
The input end vi is connected with the grid of the input PMOS tube PM0 and the grid of the input NMOS tube NM 0; the high-voltage source is connected with the source electrode of the input PMOS tube PM0, the grid electrode of the conduction switch NMOS tube NM1 and the drain electrode of the clock control NMOS tube through a first constant current source I1, the grid electrode of the clock control NMOS tube NM2 is connected with the clock signal input end ck, and the drain electrode of the input PMOS tube PM0 and the source electrode of the clock control NMOS tube NM2 are grounded;
the drain of the input NMOS tube NM0 is connected with a high voltage source, the first node A is connected with the source of the input NMOS tube NM0, the source of the conduction switch NMOS tube NM1 and the anode of the second constant current source I0, the cathode of the second constant current source I0 is grounded, and the signal output end vo is connected with the drain of the conduction switch NMOS tube NM 1;
the connection position of the drain of the clock control NMOS transistor NM2 and the gate of the on-switch NMOS transistor NM1 serves as a second node B.
FIG. 2 shows the operation sequence of the circuit of the present invention, and the clock control tube ck is used to control the operation state of the circuit. When the clock signal of the clock signal input terminal ck is at a high level, the circuit is in a high impedance state. When the clock signal at the clock signal input terminal ck is at a low level, the circuit is in an input following state.
The NMOS transistor NM0 and the first constant current source I0 in fig. 1 form an NMOS source follower, which directly drives the first node a, i.e. drives the source of the conducting switch NMOS transistor NM 1. The first node a follows the signal at the input vi regardless of the state of the circuit. And the first node A is lower than the potential of the input end vi by the gate-source voltage difference Vgsn of the NMOS tube. When the turn-on switch NMOS 1 is in the on state, the potential of the output terminal vo is equal to the potential of the first node a.
The PMOS transistor PM0 and the first constant current source I1 in fig. 1 together form a PMOS source follower, which directly drives the second node B, i.e. drives the gate of the conducting switch NMOS transistor NM 1. When the clock signal at the clock signal input ck is low, the second node B follows the signal at the input vi. And the second node B is higher than the potential of the input end vi by the gate-source voltage difference Vgsp of the PMOS tube. The gate-source voltage difference of the turned-on switch NMOS 1 is Vgsn + Vgsp. The voltage difference is independent of the voltage value of the input signal.
As known from the expression of the gate-source voltage difference of NM1, the specific voltage value of the gate-source voltage difference of NM1 can be changed by adjusting the sizes of the first constant current source I0, the first constant current source I1, or the NMOS transistor NM0, the PMOS transistor PM 0. When the clock signal input terminal ck is at a high level, the NMOS transistor NM2 is in an on state, and the current of the second constant current source I1 flows to ground through the NMOS transistor NM 2. The second node B is pulled down to ground. The NMOS transistor NM1 is in an off state. The output vo is in a high impedance state.
When the clock signal input ck of the bootstrapped switch circuit switches from a low level to a high level, the second node B is pulled down to 0. The potential jump of the second node B is coupled to the first node a through the gate-source parasitic capacitance of the NMOS transistor NM 1. For a conventional bootstrapped switch circuit, the input signal can only be affected by clock glitches. In the invention, the low output impedance of the NMOS source follower can absorb the clock interference, isolate the input terminal vi from the internal node of the bootstrap switch, and avoid the clock interference from being coupled to the input terminal as much as possible.
When the clock signal input ck of the bootstrapped switch circuit switches from a high level to a low level, the second node B follows the input vi. The NMOS transistor NM1 switches from the off state to the on state, and the first node a charges and discharges the output terminal vo. At this time, the NMOS source follower may provide the charge and discharge current for the first node a, so as to avoid the interference to the input terminal vi.
When the bootstrap circuit is switched from a high-impedance state to an input following state, the PMOS source follower can quickly drive the node B, and the NMOS tube NM1 is turned on in a very short time. When the bootstrap circuit switches from the input follower state to the high impedance state, the NMOS transistor NM2 can also pull down the potential of the second node B to the ground quickly, turning off the NMOS transistor NM1 in a very short time. The circuit has high working state switching speed.
The NMOS transistor NM2 is used to control the working state of the bootstrap switch circuit. When the clock signal at the clock signal input terminal ck is at a low level, the NMOS transistor NM2 is in an off state, the second node B follows the input terminal vi, and the gate-source voltage of the NMOS transistor NM1 is maintained at Vgsn + Vgsp. When the clock signal at the clock signal input terminal ck is at a high level, the NMOS transistor NM2 is in a conducting state, the current of the second constant current source I1 flows to the ground through the NMOS transistor NM2, the potential of the second node B is 0, and the NMOS transistor NM1 is in a closing state.
The bootstrap switch circuit structure provided by the invention does not comprise a capacitor and has a simple structure. Besides high-speed working state switching, the device can also be scaled down in equal proportion and used in more advanced small-size processes.
When the clock signal ck is at a low level, the turn-on switch NMOS 1 is in a turn-on state, the gate of the turn-on switch NMOS 1 changes with the input, and the gate-source voltage difference of the turn-on switch NMOS 1 remains unchanged. When the clock signal ck is at a high level, the clock control NMOS transistor NM2 pulls down the gate voltage of the turn-on switch NMOS transistor NM1 to 0, and the turn-on switch NMOS transistor NM1 is in an off state. The voltage of the bootstrap switch is raised by using the direct current voltage difference of the NMOS source electrode follower and the PMOS source electrode follower, and compared with the traditional bootstrap switch circuit, the voltage raising circuit omits a capacitor for raising the voltage of the switch. In addition, the source follower has a high operating speed, and when the clock signal ck jumps from a high level to a low level, the potential of the node B can quickly follow the input voltage. When the clock signal ck transitions from low to high, the potential of the node B can also be pulled down to 0 quickly. The invention not only has simple circuit structure, but also has high working state switching speed.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (3)
1. The ultra-high-speed bootstrap switch circuit with the embedded input buffer is characterized by comprising an input NMOS (N-channel metal oxide semiconductor) tube (NM0), an input PMOS tube (PM0), a conducting switch NMOS tube (NM1), a clock control NMOS tube (NM2), a first constant current source (I0), a second constant current source (I1), an input end (vi), an output end (vo), a clock control tube (NM2) and a clock signal input end (ck);
the input end (vi) is connected with the grid electrode of the input PMOS tube (PM0) and the grid electrode of the input NMOS tube (NM 0); the high-voltage source is connected with a source electrode of an input PMOS (PM0), a grid electrode of a conducting switch NMOS (NM1) and a drain electrode of a clock control NMOS tube through a first constant current source (I1), the grid electrode of the clock control NMOS tube (NM2) is connected with a clock signal input end (ck), and the drain electrode of the input PMOS tube (PM0) and the source electrode of the clock control NMOS tube (NM2) are grounded;
the drain electrode of the input NMOS tube (NM0) is connected with a high voltage source, the negative electrode of the second constant current source (I0) is grounded, and the signal output end (vo) is connected with the drain electrode of the conduction switch NMOS tube (NM 1);
when the clock signal input end (ck) is switched from high level to low level, the NMOS tube (NM1) is switched from a cut-off state to a conducting state, and the first node (A) charges and discharges the output end (vo);
the first node (A) is connected with the source electrode of the input NMOS tube (NM0), the source electrode of the conduction switch NMOS tube (NM1) and the anode of the second constant current source (I0), and the potential of the first node (A) is lower than that of the input end (vi) by a grid-source voltage difference Vgsn of the NMOS tube;
when the NMOS tube (NM1) of the turn-on switch is in a turn-on state, the potential of the output end (vo) is equal to the potential of the first node (A);
the connection position of the drain electrode of the clock control NMOS tube (NM2) and the grid electrode of the breakover switch NMOS tube (NM1) is used as a second node (B); when the clock signal input terminal (ck) is switched from a low level to a high level, the potential of the second node (B) is 0.
2. The ultra-high speed bootstrap switch circuit of the embedded input buffer of claim 1, characterized in that, when the clock signal input terminal (ck) is high level, the turn-on switch NMOS tube (NM2) is in turn-on state, the current on the second constant current source (I1) flows to ground through the clock control NMOS tube (NM 2); the potential of the second node (B) is 0; the NMOS tube (NM1) of the turn-on switch is in a closed state; the output (vo) is in a high impedance state.
3. The bootstrap switch circuit with ultra high speed of embedded input buffer as claimed in claim 1, wherein when the clock signal input terminal (ck) is low, the clock control NMOS transistor (NM2) is in off state, the second node (B) is higher than the input terminal (vi) by a gate-source voltage difference Vgsp of PMOS transistor, and the gate-source voltage difference of the conducting switch NMOS transistor (NM1) is Vgsn + Vgsp, where Vgsn is the gate-source voltage difference of an NMOS transistor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010378270.1A CN111431517B (en) | 2020-05-07 | 2020-05-07 | Ultra-high-speed bootstrap switch circuit with embedded input buffer |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010378270.1A CN111431517B (en) | 2020-05-07 | 2020-05-07 | Ultra-high-speed bootstrap switch circuit with embedded input buffer |
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| CN111431517B true CN111431517B (en) | 2022-04-22 |
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