CN108155899B - Grid voltage bootstrap switch circuit - Google Patents

Grid voltage bootstrap switch circuit Download PDF

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CN108155899B
CN108155899B CN201711417126.9A CN201711417126A CN108155899B CN 108155899 B CN108155899 B CN 108155899B CN 201711417126 A CN201711417126 A CN 201711417126A CN 108155899 B CN108155899 B CN 108155899B
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pmos
nmos
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electrode
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CN108155899A (en
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李靖
魏祎
宁宁
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

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Abstract

A grid voltage bootstrap switch circuit belongs to the field of analog integrated circuits. The charge pump circuit is used for charging the fifth capacitor and the sixth capacitor to enable the stored charge quantity of the fifth capacitor and the sixth capacitor to be constant, the grid voltage boosting circuit and the grid voltage reducing circuit are used for changing grid end voltages of the NMOS switching tube and the PMOS switching tube to enable grid source voltages of the NMOS switching tube and the PMOS switching tube to be constant, and the switching circuit is used for controlling charging of the charge pump circuit and starting and closing of the grid voltage boosting circuit and the grid voltage reducing circuit. The NMOS switch tube and the PMOS switch tube are used for simultaneously connecting the input signal to the output, so that the on-resistance of the switch is reduced; by utilizing the mode that the NMOS switch tube and the PMOS switch tube are connected in parallel, the channel charge injection effect caused by clock change of the NMOS switch tube and the PMOS switch tube is mutually counteracted, and the clock feed-through effect is also mutually counteracted, thereby improving the linearity of the switch; the capacitor is charged by the diode, so that no overvoltage device exists in the circuit, and the reliability of the circuit is improved.

Description

Grid voltage bootstrap switch circuit
Technical Field
The invention belongs to the field of analog integrated circuit design, and particularly relates to a gate voltage bootstrap switch circuit.
Background
With the continuous development of modern communication technology and the continuous improvement of the requirement of people on communication speed, the frequency of an analog signal in a communication system is continuously improved, the requirement of converting the analog signal into a digital signal is continuously improved, and an analog-to-digital converter is required to have higher linearity when sampling the analog signal, so that a gate voltage bootstrap circuit is required.
The conventional gate voltage bootstrap switch circuit structure is shown in fig. 1, and is composed of a main switch tube MsAnd a gate voltage bootstrap circuit including a capacitor C7～C8And MOS transistor M1～M11. The working principle is as follows:
(1) off phase, when C L K is low and C L KB is high, M is low3Conduction, C7The lower plate being connected to ground, C8The upper plate voltage is 2 times of the power supply voltage VDD, so that M is2Is conducted to C7Therein store C7× VDD, M6Off, M5Will M4Is connected to a supply voltage VDD such that M4Off, C L KB is high, let M11Off, M10Is turned on to connect M9Source is connected to ground, so that M9Conducting the main switch tube MsIs connected to ground, then M7～M9And MsAnd (6) turning off.
(2) In the conducting phase, when C L K is converted to high level and C L KB is low level, M is in the conducting phase3Off, M1Is conducted to C8Store C8× VDD, C L KB is low, making M10Off, M11Is turned on to connect M9The source is connected to the supply voltage VDD, so that M9Turn off, C L K is switched to high level to make M5Off, M6Is turned on to connect M4The grid of (1) is pulled low, then M4Is conducted to further enable M8On, the input signal passes through M8To C7Lower plate due to capacitance C7The charge stored in the capacitor C is stored in the capacitor C without a discharge loop in the conversion process of the clock C L K7The charge on is kept constant, then the capacitance C7The voltage of the upper plate will rise synchronously until it equals Vin+ VDD, the main switch transistor M at this timesGate terminal voltage V ofD＝Vin+ VDD, the main switch tube MsGate source voltage V ofGSComprises the following steps:
VGS＝VD-Vin＝Vin+VDD-Vin＝VDD
the on-resistance of the main switch tube is as follows:
Figure BDA0001522264050000011
where μ is the carrier mobility, CoxThe unit area gate capacitance of the main switching tube,
Figure BDA0001522264050000012
is a main switch tube MsWidth to length ratio of VGSIs a main switch tube MsGate-source voltage of VthIs a main switch tube MsTurn-on threshold voltage of。
By using the grid voltage bootstrap circuit, the grid source voltage is equal to the power supply voltage VDD when the main switching tube is conducted, so that the conducting resistance is kept constant, and the output signal V can be realizedoutFor input signal VinAnd high-linearity tracking is realized.
However, in the conventional gate voltage bootstrap circuit, M2When the turn-off phase is in an overvoltage state, the reliability problem of the circuit can be caused, and the service life of the circuit is shortened; generally, in order to realize fast sampling of a high-speed signal, the on-resistance of the main switch tube is required to be very low, which results in a very large size, so that the channel charge injection effect and the clock feed-through effect of the main switch tube become serious, and the linearity of sampling of the main switch tube becomes low.
Disclosure of Invention
In view of the above insufficiency, the invention provides a gate voltage bootstrap switch circuit, the main switch tube of which is a CMOS switch tube, which can effectively improve the linearity, improve the reliability of the chip and reduce the on-resistance.
The technical scheme of the invention is as follows:
a gate voltage bootstrap switch circuit comprises an NMOS main switch tube MnAnd PMOS main switch tube MpAnd with NMOS main switch tube MnA first charge pump circuit, a gate voltage boost circuit, a first switch circuit, and a PMOS main switch tube MpA second charge pump circuit, a gate voltage reduction circuit and a second switch circuit connected,
NMOS main switch tube MnSource electrode of the PMOS main switch tube MpThe source electrode of the transistor is used as the input end of the grid voltage bootstrap switch circuit, and the drain electrode of the transistor is connected with a PMOS main switch tube MpAnd as the output terminal of the gate voltage bootstrapped switch circuit;
the first charge pump circuit comprises a first NMOS transistor MN1, a second NMOS transistor MN2, a first capacitor C1, a second capacitor C2 and a first diode D1,
the grid electrode of the first NMOS tube MN1 is connected with the source electrode of the second NMOS tube MN2 and the anode electrode of a first diode D1, and is connected with an inverted clock signal C L KB after passing through a second capacitor C2, the source electrode of the first NMOS tube MN1 is connected with the grid electrode of the second NMOS tube MN2, and is connected with a clock signal C L K after passing through a first capacitor C1, and the drain electrode of the first NMOS tube MN 56 2 is connected with the source voltage;
the second charge pump circuit comprises a first PMOS pipe MP1, a second PMOS pipe MP2, a third capacitor C3, a fourth capacitor C4 and a second diode D2,
the grid electrode of the first PMOS tube MP1 is connected with the source electrode of the second PMOS tube MP2, and is connected with an inverted clock signal C L KB after passing through a third capacitor C3, the source electrode of the first PMOS tube MP1 is connected with the grid electrode of the second PMOS tube MP2 and the cathode electrode of a second diode D2, and is connected with a clock signal C L K after passing through a fourth capacitor C4, and the drain electrode of the first PMOS tube MP2 is connected with the drain electrode of the second PMOS tube MP2 and is grounded;
the grid voltage boost circuit comprises a third NMOS transistor MN3, a fourth NMOSMN4, a fifth PMOS transistor MP5 and a sixth capacitor C6,
the grid electrode of a fourth NMOS tube MN4 is connected with the NMOS main switch tube MnA gate of the third NMOS transistor MN3, a drain of the fifth PMOS transistor MP5, a source of the fifth PMOS transistor MP5 connected to the input terminal of the gate voltage bootstrapped switch circuit, a drain of the fifth PMOS transistor MP5 connected to the source of the third NMOS transistor MN3 through a sixth capacitor C6, and an output terminal of the first charge pump circuit; the grid electrode of the fifth PMOS pipe MP5 is connected with the first switch circuit;
the grid voltage reduction circuit comprises a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth NMOS tube MN5 and a fifth capacitor C5,
the grid electrode of the fourth PMOS tube MP4 is connected with the PMOS main switch tube MpThe gate of the third PMOS transistor MP3, the drain of the fifth NMOS transistor MN5, the source of the fifth NMOS transistor MN5 is connected to the input terminal of the gate voltage bootstrapped switch circuit, the drain of the fifth NMOS transistor MP3 is connected to the source of the third PMOS transistor MP3 and the drain of the third NMOS transistor MN3 in the gate voltage boost circuit, and the fifth NMOS transistor MN5 and the output terminal of the second charge pump circuit are connected through a fifth capacitor C5; the grid electrode of a fifth NMOS pipe MN5 is connected with the second switch circuit; the drain electrode of the third PMOS tube MP3 is connected with the source electrode of a third NMOS tube MN3 in the grid voltage lifting circuit;
the first switch circuit generates a timing control signal to control the gate voltage boosting circuit according to a clock signal C L K and an inverted clock signal C L KB;
the second switch circuit generates a timing control signal to control the gate voltage reduction circuit according to a clock signal C L K and an inverted clock signal C L KB.
Specifically, the first switch circuit includes a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh PMOS transistor MP11, and a twelfth PMOS transistor MP12,
the gate of the sixth NMOS transistor MN6 is connected to the inverted clock signal C L KB, the source thereof is grounded, the drain thereof is connected to the sources of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8, and the drain of the fourth NMOS transistor MN4 in the gate voltage boost circuit;
the gate of the eleventh PMOS transistor MP11 is connected to the gate of the seventh NMOS transistor MN7 and the clock signal C L K, the source thereof is connected to the power supply voltage, and the drain thereof is connected to the drains of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 and the gate of the fifth PMOS transistor MP5 in the gate voltage boost circuit;
the grid electrode of the ninth NMOS tube MN9 is connected with a power supply voltage, the drain electrode of the ninth NMOS tube MN8 is connected with the grid electrode of the eighth NMOS tube MP5 in the grid voltage boosting circuit, and the source electrode of the ninth NMOS tube MN 3578 is connected with the drain electrodes of the tenth NMOS tube MN10 and the twelfth PMOS tube MP 12;
the source of the twelfth PMOS transistor MP12 is connected to the power supply voltage, the gate thereof is connected to the gate of the tenth NMOS transistor MN10 and to the inverted clock signal C L KB, and the source of the tenth NMOS transistor MN10 is grounded;
the second switch circuit comprises a sixth PMOS tube MP6, a seventh PMOS tube MP7, an eighth PMOS tube MP8, a ninth PMOS tube MP9, a tenth PMOS tube MP10, an eleventh NMOS tube MN11 and a twelfth NMOS tube MN12,
the gate of the sixth PMOS transistor MP6 is connected to the clock signal C L K, the source thereof is grounded, the drain thereof is connected to the sources of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8, and the drain of the fourth PMOS transistor MP4 in the gate voltage reduction circuit;
the gate of the eleventh NMOS transistor MN11 is connected to the gate of the seventh PMOS transistor MP7 and the inverted clock signal C L KB, the source thereof is grounded, and the drain thereof is connected to the drains of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 and the gate of the fifth NMOS transistor MN5 in the gate voltage reduction circuit;
the gate of the ninth PMOS transistor MP9 is grounded, the drain thereof is connected to the gate of the eighth PMOS transistor MP8 and the drain of the fifth NMOS transistor MN5 in the gate voltage reduction circuit, and the source thereof is connected to the drains of the tenth PMOS transistor MP10 and the twelfth NMOS transistor MN 12;
the source of the twelfth NMOS transistor MN12 is grounded, the gate thereof is connected to the gate of the tenth PMOS transistor MP10 and to the clock signal C L K, and the source of the tenth PMOS transistor MP10 is connected to the power voltage.
The invention has the beneficial effects that:
1. the invention realizes the grid voltage bootstrap, and makes the NMOS main switch tube MnAnd PMOS main switch tube MpThe gate-source voltage is fixed when the NMOS main switch tube M is conductednAnd PMOS main switch tube MpAt the same time, the input signal is connected to the output, reducing the on-resistance of the switch.
2. The invention utilizes NMOS main switch tube MnAnd PMOS main switch tube MpIn parallel connection, the NMOS main switch tube M is enablednAnd PMOS main switch tube MpThe channel charge injection effects caused by clock changes cancel each other out, and the clock feed-through effects also cancel each other out, thereby improving the linearity of the switch.
3. The invention charges the capacitor by adopting the diode, so that the circuit has no overvoltage device, and the reliability of the circuit is improved.
Drawings
Fig. 1 is a schematic diagram of a gate voltage bootstrapped switch circuit in the prior art.
Fig. 2 is an implementation form of a gate voltage bootstrapped switch circuit provided by the present invention.
Detailed Description
The technical scheme of the invention is described in detail below by combining the accompanying drawings and specific embodiments.
As shown in FIG. 2, the gate voltage bootstrapped switch circuit provided by the present invention includes an NMOS main switch tube MnAnd PMOS main switch tube MpAnd with NMOS main switch tube MnA first charge pump circuit, a gate voltage boost circuit, a first switch circuit, and a PMOS main switch tube MpA second charge pump circuit, a gate voltage reduction circuit, a second switch circuit, and an NMOS main switch tube MnSource electrode of the PMOS main switch tube MpAnd the source electrode is used as the input end of the grid voltage bootstrap switch circuit to be connected with an input signal VinThe drain electrode of the PMOS main switch tube M is connected withpAnd the drain electrode is used as the output end of the grid voltage bootstrap switch circuit to be connected with an output signal VoutInput signal VinIs connected to the NMOS main switch tube M through a grid voltage lifting circuit and a grid voltage reducing circuitnAnd PMOS main switch tube MpA gate electrode of (1); NMOS main switch tube MnThe grid of the PMOS transistor is a node A, and a PMOS main switch tube MpThe gate of (a) is node B.
Connecting NMOS main switch tube MnThe first charge pump circuit comprises a first NMOS tube MN1, a second NMOS tube MN2, a first capacitor C1, a second capacitor C2 and a first diode D1, wherein the gate of the first NMOS tube MN1 is connected with the source of the second NMOS tube MN2 and the anode of the first diode D1, and is connected with an inverted clock signal C L KB through the second capacitor C2, the source of the first NMOS tube MN1 is connected with the gate of the second NMOS tube MN2, and is connected with a clock signal C L K through the first capacitor C1, the drain of the first NMOS tube MN2 is connected with the drain of the second NMOS tube MN2 and is connected with a power voltage, and the cathode of the first diode D1 is used as the output end of the first charge pump circuit.
The grid voltage boosting circuit is connected with the output end of the first charge pump circuit and comprises a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth PMOS transistor MP5 and a sixth capacitor C6, wherein the grid electrode of the fourth NMOS transistor MN4 is connected with an NMOS main switching transistor M6nA gate of the third NMOS transistor MN3, a drain of the fifth PMOS transistor MP5, a source of the fifth PMOS transistor MP5 connected to the input terminal of the gate voltage bootstrapped switch circuit, a drain of the fifth PMOS transistor MP5 connected to the source of the third NMOS transistor MN3 through a sixth capacitor C6, and an output terminal of the first charge pump circuit; the grid electrode of the fifth PMOS pipe MP5 is connected with the first switch circuit.
The first charge pump circuit is conducted by raising the grid voltage of the MOS tube to a positive 2 times of the power supply voltage VDD and is used for raising the grid voltage in the circuitThe sixth capacitor C6 is charged so that the amount of charge stored by the sixth capacitor C6 is constant as the product of its capacitance value and 2 times the supply voltage VDD minus the diode drop; grid voltage lifting circuit for changing NMOS main switch tube MnBy raising the voltage of the NMOS main switch tube MnGate terminal voltage of the input signal V to realize the gate source voltage of the input signal VinIndependent constant value, thereby realizing the function of grid voltage boost and eliminating the input signal VinFor NMOS main switch tube MnThe first switch circuit is used for controlling charging of the first charge pump circuit and opening and closing of the grid voltage lifting circuit, the first switch circuit in the embodiment comprises a sixth NMOS tube MN6, a seventh NMOS tube MN7, an eighth NMOS tube MN8, a ninth NMOS tube MN9, a tenth NMOS tube MN10, an eleventh PMOS tube MP11 and a twelfth PMOS tube MP12, a grid electrode of the sixth NMOS tube MN6 is connected with an inverted clock signal C L KB, a source electrode of the sixth NMOS tube MN6 is grounded, a drain electrode of the sixth NMOS tube MN7 and a source electrode of the eighth NMOS tube MN8 are connected with a drain electrode of the fourth NMOS tube MN4 in the grid voltage lifting circuit, a grid electrode of the eleventh NMOS tube MP 56 is connected with a grid electrode of the seventh NMOS tube MN7 and a clock signal C L K, a source electrode voltage of the eleventh NMOS tube MP 56 is connected with a drain electrode of the seventh NMOS tube MN7 and a drain electrode of a clock signal C L K, a drain electrode of the eleventh NMOS tube MP tube is connected with a drain electrode 9, a drain electrode of the fifth NMOS tube MN9 is connected with a drain electrode 9, a drain electrode of the twelfth NMOS tube MN9 is connected with a drain electrode of the twelfth NMOS tube MN9 and a drain electrode 9, a drain electrode of the fifth PMOS tube 363672 is connected with a drain electrode 9, a drain electrode of the fifth NMOS tube MN 363672, a drain electrode 3636363672 is connected with a drain electrode of the NMOS tube 9.
The second charge pump circuit connected with the PMOS main switch tube comprises a first PMOS tube MP1, a second PMOS tube MP2, a third capacitor C3, a fourth capacitor C4 and a second diode D2, wherein the grid electrode of the first PMOS tube MP1 is connected with the source electrode of the second PMOS tube MP2, the grid electrode of the first PMOS tube MP1 is connected with an inverted clock signal C L KB after passing through the third capacitor C3, the source electrode of the first PMOS tube MP1 is connected with the grid electrode of the second PMOS tube MP2 and the cathode electrode of the second diode D2, the grid electrode of the first PMOS tube MP 3626K is connected with a clock signal C L K after passing through the fourth capacitor C4, the drain electrode of the first PMOS tube MP2 is connected with the ground, and the anode electrode of the second diode D2 is used.
The grid voltage reduction circuit is connected with the output end of the second charge pump circuit and comprises a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth NMOS tube MN5 and a fifth capacitor C5, wherein the grid electrode of the fourth PMOS tube MP4 is connected with the PMOS main switching tube M5pThe gate of the third PMOS transistor MP3, the drain of the fifth NMOS transistor MN5, the source of the fifth NMOS transistor MN5 is connected to the input terminal of the gate voltage bootstrapped switch circuit, the drain of the fifth NMOS transistor MP3 is connected to the source of the third PMOS transistor MP3 and the drain of the third NMOS transistor MN3 in the gate voltage boost circuit, and the fifth NMOS transistor MN5 and the output terminal of the second charge pump circuit are connected through a fifth capacitor C5; the grid electrode of a fifth NMOS pipe MN5 is connected with the second switch circuit; the drain of the third PMOS transistor MP3 is connected to the source of the third NMOS transistor MN3 in the gate voltage boost circuit.
The second charge pump circuit is conducted by reducing the grid voltage of the MOS tube to a negative power supply voltage VDD and is used for charging a fifth capacitor C5 in the grid voltage reduction circuit to fix the stored charge quantity to be the product of the capacitance value and 2 times of the power supply voltage VDD minus a diode drop, the grid voltage reduction circuit is used for changing the grid end voltage of the PMOS main switch tube and reducing the grid end voltage of the PMOS main switch tube M by reducing the voltagepThe gate terminal voltage of the transistor is equal to the input voltage VinIndependent constant value, thereby realizing the function of reducing the grid voltage and eliminating the input signal VinFor PMOS main switch tube MpThe second switch circuit in the embodiment comprises a sixth PMOS tube MP6, a seventh PMOS tube MP7, an eighth PMOS tube MP8, a ninth PMOS tube MP9, a tenth PMOS tube MP10, an eleventh NMOS tube MN11 and a twelfth NMOS tube MN12, the grid of the sixth PMOS tube MP6 is connected with a clock signal C L K, the sources of the sixth PMOS tube MP6 are grounded, the drains of the sixth PMOS tube MP6 and the eighth PMOS tube MP8 are connected with the sources of the seventh PMOS tube MP7 and the eighth PMOS tube MP8 and the drain of the fourth PMOS tube MP4 in the second gate voltage lifting circuit, the grid of the eleventh NMOS tube MN11 is connected with the grid of the seventh PMOS tube MP7 and an inverted clock signal C L, the sources of the eleventh NMOS tube MN11 are grounded, and the drain of the eleventh PMOS tube MP 353635 and the eighth PMOS tube MP8 is connected with the drain of the seventh PMOS tube MP7 and the drain of the eighth PMOS tube MP8 and the fifth gate voltage lifting circuitThe grid electrode of the MN5, the grid electrode of the ninth PMOS tube MP9 is grounded, the drain electrode of the ninth PMOS tube MP9 is connected with the grid electrode of the eighth PMOS tube MP8 and the drain electrode of the fifth NMOS tube MN5 in the second grid voltage lifting circuit, the source electrode of the ninth PMOS tube MP9 is connected with the drain electrodes of the tenth PMOS tube MP10 and the twelfth NMOS tube MN12, the source electrode of the twelfth NMOS tube MN12 is grounded, the grid electrode of the twelfth NMOS tube MP10 is connected with the grid electrode of the tenth PMOS tube MP10 and a clock signal C L K, and the source electrode of the tenth PMOS tube MP10 is connected with.
The working principle of the embodiment is as follows: in the gate voltage bootstrap switch circuit shown in FIG. 2, the NMOS main switch tube M is connectednThe first charge pump circuit charges a sixth capacitor C6 in the grid voltage boosting circuit, and the stored charge amount after charging is C × (2V)DD-VF) In which V isFFor the voltage drop when the diode is conducted, when the lower plate of the sixth capacitor C6 is connected with the input signal VinWhen the voltage of the upper plate is raised to VC6＝2VDD-VF+VinThe fifth PMOS transistor MP5 connects the NMOS main switch transistor MnIs connected with the upper plate of the sixth capacitor C6, so that the NMOS main switch tube MnGate source voltage V ofGSn＝VC6-Vin＝2VDD-VF+Vin-Vin＝2VDD-VFIs in accordance with the input signal VinIndependent and constant 2VDD-VFAt this time, the NMOS main switch tube MnConducting, outputting signal VoutFor input signal VinTracking is carried out, thereby realizing the grid voltage lifting function and eliminating the input signal to the NMOS main switch tube MnThe effect of the on-resistance.
Connecting PMOS main switch tube MpThe second charge pump circuit charges a fifth capacitor C5 in the gate voltage reduction circuit, and the charge amount stored after the charging is C × (2V)DD-VF) In which V isFWhen the upper plate of the fifth capacitor C5 is connected with input, the lower plate voltage is reduced to VC5＝Vin-(2VDD-VF) The fifth NMOS transistor MN5 is used for connecting the PMOS main switch transistor MpIs connected with the lower plate of the fifth capacitor C5, so that the PMOS main switch tube MpGate source voltage V ofGSp＝Vin-VC＝Vin-(2VDD-VF+Vin)＝-(2VDD-VF) Is in accordance with the input signal VinIndependent and constant- (2V)DD-VF) At this time, PMOS main switch tube MpConducting, outputting signal VoutFor input signal VinTracking is carried out, thereby realizing the grid voltage lifting function and eliminating the input signal to the PMOS main switch tube MpThe effect of the on-resistance.
Meanwhile, the invention can lead the NMOS main switch tube MnAnd PMOS main switch tube MpThe channel charge injection effect and the clock feed-through effect caused by the clock change are mutually counteracted, thereby improving the linearity of the switch.
In summary, the gate voltage bootstrapped switch circuit provided by the present invention enables the NMOS main switch transistor MnAnd PMOS main switch tube MpThe gate-source voltage is fixed when the NMOS main switch tube M is conductednAnd PMOS main switch tube MpSimultaneously input signal VinConnected to the output, reducing the on-resistance of the switch; by using NMOS main switch tube MnAnd PMOS main switch tube MpIn parallel connection, the NMOS main switch tube M is enablednAnd PMOS main switch tube MpChannel charge injection effects caused by clock change are mutually counteracted, and clock feed-through effects are mutually counteracted, so that the linearity of the switch is improved; the capacitor is charged by the diode, so that no overvoltage device exists in the circuit, and the reliability of the circuit is improved.
Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.

Claims (2)

1. A gate voltage bootstrap switch circuit is characterized in that the gate voltage bootstrap switch circuit comprises an NMOS main switch tube (M)n) And PMOS main switch tube (M)p) And with NMOS main switch tube (M)n) A first charge pump circuit, a gate voltage boost circuit and a first switch circuit connected with the PMOS main switch tube (M)p) A second charge pump circuit, a gate voltage reduction circuit and a second switch circuit connected,
NMOS main switch tube (M)n) Source electrode of the PMOS main switch tube (M)p) The source electrode of the gate voltage bootstrap switch circuit is used as the input end of the gate voltage bootstrap switch circuit, and the drain electrode of the gate voltage bootstrap switch circuit is connected with a PMOS main switch tube (M)p) And as the output terminal of the gate voltage bootstrapped switch circuit;
the first charge pump circuit comprises a first NMOS transistor (MN1), a second NMOS transistor (MN2), a first capacitor (C1), a second capacitor (C2) and a first diode (D1),
the grid electrode of the first NMOS tube (MN1) is connected with the source electrode of the second NMOS tube (MN2) and the anode of the first diode (D1) and is connected with an inverted clock signal (C L KB) through a second capacitor (C2), the source electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube (MN2) and is connected with a clock signal (C L K) through a first capacitor (C1), the drain electrode of the first NMOS tube (MN2) is connected with the source voltage, and the cathode electrode of the first diode (D1) is used as the output end of the first charge pump circuit;
the second charge pump circuit comprises a first PMOS tube (MP1), a second PMOS tube (MP2), a third capacitor (C3), a fourth capacitor (C4) and a second diode (D2),
the grid electrode of the first PMOS tube (MP1) is connected with the source electrode of the second PMOS tube (MP2) and is connected with an inverted clock signal (C L KB) after passing through a third capacitor (C3), the source electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube (MP2) and the cathode of the second diode (D2) and is connected with a clock signal (C L K) after passing through a fourth capacitor (C4), the drain electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube (MP2) and is grounded, and the anode electrode of the second diode (D2) is used as the output end of the second charge pump circuit;
the NMOS main switch tube (M)n) The gate-source voltage is 2V when the transistor is turned onDD-VFThe PMOS main switch tube (M)p) The gate-source voltage is- (2V) when conductingDD-VF) In which V isDDIs the voltage value of the supply voltage, VFThe voltage drop when the first diode (D1) is conducted and the voltage drop when the second diode (D2) is conducted;
the grid voltage boost circuit comprises a third NMOS transistor (MN3), a fourth NMOS transistor (MN4), a fifth PMOS transistor (MP5) and a sixth capacitor (C6),
the grid electrode of a fourth NMOS tube (MN4) is connected with the NMOS main switch tube (M)n) The grid of the first PMOS tube (MP5), the grid of the third NMOS tube (MN3) and the drain electrode of the fifth PMOS tube (MP5), the source electrode of the fifth PMOS tube (MP5) is connected with the input end of the grid voltage bootstrap switch circuit, the drain electrode of the fifth PMOS tube (MP5) is connected with the source electrode of the third NMOS tube (MN3) and the output end of the first charge pump circuit after passing through a sixth capacitor (C6); the grid electrode of a fifth PMOS tube (MP5) is connected with the first switch circuit;
the grid voltage reduction circuit comprises a third PMOS tube (MP3), a fourth PMOS tube (MP4), a fifth NMOS tube (MN5) and a fifth capacitor (C5),
the grid electrode of the fourth PMOS tube (MP4) is connected with the PMOS main switch tube (M)p) The gate of the third PMOS transistor (MP3), the drain of the fifth NMOS transistor (MN5), the source of the fifth NMOS transistor (MN5), the source of the fifth NMOS transistor (MN5), and the drain of the fifth NMOS transistor (MN5) are connected to the input terminal of the gate voltage bootstrapped switch circuit, and the drain of the third PMOS transistor (MP3), the drain of the fifth NMOS transistor (MN3) in the gate voltage boost circuit, and the fifth capacitor (C5) and the drain of the fifth NMOS transistor (MN5) are connected to the output terminal of the second charge pump circuit; the grid electrode of a fifth NMOS tube (MN5) is connected with the second switch circuit; the drain electrode of the third PMOS tube (MP3) is connected with the source electrode of a third NMOS tube (MN3) in the grid voltage lifting circuit;
the first switch circuit generates a timing control signal to control the gate voltage boosting circuit according to a clock signal (C L K) and an inverted clock signal (C L KB);
the second switch circuit generates a timing control signal to control the gate voltage reduction circuit according to a clock signal (C L K) and an inverted clock signal (C L KB).
2. The gate voltage bootstrapped switch circuit of claim 1, wherein the first switch circuit comprises a sixth NMOS transistor (MN6), a seventh NMOS transistor (MN7), an eighth NMOS transistor (MN8), a ninth NMOS transistor (MN9), a tenth NMOS transistor (MN10), an eleventh PMOS transistor (MP11), and a twelfth PMOS transistor (MP12),
the grid electrode of the sixth NMOS tube (MN6) is connected with the inverted clock signal (C L KB), the source electrode of the sixth NMOS tube is grounded, and the drain electrode of the sixth NMOS tube is connected with the source electrodes of the seventh NMOS tube (MN7) and the eighth NMOS tube (MN8) and the drain electrode of the fourth NMOS tube (MN4) in the grid voltage boosting circuit;
the gate of the eleventh PMOS tube (MP11) is connected with the gate of the seventh NMOS tube (MN7) and the clock signal (C L K), the source of the eleventh PMOS tube is connected with the power supply voltage, and the drain of the eleventh PMOS tube is connected with the drains of the seventh NMOS tube (MN7) and the eighth NMOS tube (MN8) and the gate of the fifth PMOS tube (MP5) in the gate voltage boost circuit;
the grid electrode of the ninth NMOS tube (MN9) is connected with a power supply voltage, the drain electrode of the ninth NMOS tube (MN8) is connected with the grid electrode of the eighth NMOS tube and the drain electrode of the fifth PMOS tube (MP5) in the grid voltage boosting circuit, and the source electrode of the ninth NMOS tube (MN10) is connected with the drain electrode of the tenth NMOS tube and the drain electrode of the twelfth PMOS tube (MP 12);
the source electrode of the twelfth PMOS tube (MP12) is connected with the power supply voltage, the grid electrode of the twelfth PMOS tube is connected with the grid electrode of the tenth NMOS tube (MN10) and is connected with the inverted clock signal (C L KB), and the source electrode of the tenth NMOS tube (MN10) is grounded;
the second switch circuit comprises a sixth PMOS tube (MP6), a seventh PMOS tube (MP7), an eighth PMOS tube (MP8), a ninth PMOS tube (MP9), a tenth PMOS tube (MP10), an eleventh NMOS tube (MN11) and a twelfth NMOS tube (MN12),
the grid electrode of the sixth PMOS tube (MP6) is connected with a clock signal (C L K), the source electrode of the sixth PMOS tube is grounded, and the drain electrode of the sixth PMOS tube is connected with the source electrodes of the seventh PMOS tube (MP7) and the eighth PMOS tube (MP8) and the drain electrode of the fourth PMOS tube (MP4) in the grid voltage reduction circuit;
the gate of the eleventh NMOS transistor (MN11) is connected with the gate of the seventh PMOS transistor (MP7) and the inverted clock signal (C L KB), the source of the eleventh NMOS transistor is grounded, and the drain of the eleventh NMOS transistor is connected with the drains of the seventh PMOS transistor (MP7) and the eighth PMOS transistor (MP8) and the gate of the fifth NMOS transistor (MN5) in the gate voltage reduction circuit;
the grid electrode of the ninth PMOS tube (MP9) is grounded, the drain electrode of the ninth PMOS tube is connected with the grid electrode of the eighth PMOS tube (MP8) and the drain electrode of the fifth NMOS tube (MN5) in the grid voltage reduction circuit, and the source electrode of the ninth PMOS tube is connected with the drain electrodes of the tenth PMOS tube (MP10) and the twelfth NMOS tube (MN 12);
the source of the twelfth NMOS transistor (MN12) is grounded, the grid of the twelfth NMOS transistor is connected with the grid of the tenth PMOS transistor (MP10) and is connected with the clock signal (C L K), and the source of the tenth PMOS transistor (MP10) is connected with the power voltage.
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CN111106819B (en) * 2019-12-31 2023-04-18 思瑞浦微电子科技（苏州）股份有限公司 Grid voltage bootstrap switch circuit
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