CN108471225B - voltage detection control circuit for bypass switch - Google Patents

voltage detection control circuit for bypass switch Download PDF

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Publication number
CN108471225B
CN108471225B CN201810382381.2A CN201810382381A CN108471225B CN 108471225 B CN108471225 B CN 108471225B CN 201810382381 A CN201810382381 A CN 201810382381A CN 108471225 B CN108471225 B CN 108471225B
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China
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tube
voltage
pmos tube
pmos
transistor
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CN108471225A (en
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李泽宏
张成发
孙河山
熊涵风
胡任任
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)

Abstract

A voltage detection control circuit for a bypass switch belongs to the technical field of electronic circuits. The bypass switch uses a VDMOS power tube as a main switch tube, the body diode conduction voltage of the VDMOS power tube is reduced to power supply voltage to supply power for the oscillator and the charge pump circuit, the oscillator generates a clock signal to control the charge pump circuit to pump up the power supply voltage to the voltage detection circuit to generate power supply voltage to supply power for the voltage detection circuit and the driving circuit, the output signal of the voltage detection circuit controls the charge pump circuit and the driving circuit, the driving circuit generates a driving signal with larger driving capacity to control the VDMOS power tube, the shutdown circuit stops charging the first capacitor when the output voltage reaches a preset upper limit, and the circuit is started to continue charging the first capacitor when the voltage of the first capacitor is reduced to a preset lower limit. The invention has the advantages of obviously reduced average conduction voltage drop, higher reverse voltage resistance and smaller leakage current; and the voltage detection circuit adopts a built-in comparator, so that the reliability of the preset voltage is guaranteed.

Description

Voltage detection control circuit for bypass switch
Technical Field
the invention belongs to the technical field of electronic circuits, and relates to a voltage detection control circuit for a bypass switch.
Background
the average conduction voltage drop of the bypass switch is an important factor directly determining the power consumption of the bypass switch module, and compared with the traditional diode bypass mode, the VDMOS adopted as the main switch tube of the bypass switch has the obvious advantages of extremely low conduction voltage drop and greatly reduced power consumption. The reverse withstand voltage of the bypass switch module determines the voltage range in which the rectification system is applied, for example, the number of solar cells connected in parallel in use of the photovoltaic system. Reverse withstand voltage and forward conduction voltage drop in the traditional Schottky diode design are mutually restricted indexes, the VDMOS is adopted as a bypass switch of a main switching tube, and the reverse withstand voltage value can be more flexibly designed. The leakage current of the bypass switch is also an important index, and for the solar cell unit of the photovoltaic system, when the solar cell unit generates electricity normally, the bypass switch module is in a closed state, and the leakage current also determines the static power consumption of the module. The conventional Schottky diode has large leakage, while a bypass switch adopting the VDMOS as a main switching tube adopts a high-voltage tube as a voltage-resistant tube, and the leakage current of the conventional Schottky diode can be designed to be below 10 uA. The traditional bypass switch module adopts collector voltage change to change preset voltage, generally can use a charge pump to convert input voltage into driving voltage to drive a VDMOS power tube, and the pump-up voltage of the charge pump is easy to vibrate when the voltage is higher because the fluctuation is larger, so that the problem of false triggering caused by the fact that the power supply ripple is larger in the preset voltage of the bypass switch is solved.
Disclosure of Invention
compared with the traditional Schottky bypass diode, the voltage detection control circuit for the bypass switch provided by the invention has the advantages that the VDMOS is adopted as the main switching tube of the bypass switch, the average conduction voltage drop is obviously reduced, the reverse withstand voltage is higher, the leakage current is smaller and the like; aiming at the problem of false triggering of the preset voltage of the bypass switch due to large power supply ripples, the voltage detection circuit adopts a built-in comparator, so that the reliability of the preset voltage is guaranteed; the charge stage and the discharge stage are realized through alternate operation, the charge pump converts an input voltage source into a driving voltage and drives the VDMOS power tube, so that the driving efficiency of the bypass switch is improved, and the average conduction voltage drop is obviously reduced.
The technical scheme of the invention is as follows:
a voltage detection control circuit for a bypass switch, wherein the bypass switch uses a VDMOS power tube as a main switching tube, the voltage detection control circuit comprises a first capacitor C1 and a control module, the control module comprises three control ends and an output end, the first control end of the control module is connected with a source electrode of the VDMOS power tube and a power voltage VDD, the second control end of the control module is connected with a drain electrode of the VDMOS power tube, the third control end of the control module is connected with a grid electrode of the VDMOS power tube, the output end of the control module is connected with one end of a first capacitor C1, and the other end of the first capacitor C1 is grounded; the conduction voltage drop of the VDMOS power tube body diode is used as the power supply voltage VDD;
the control module comprises an oscillator, a charge pump circuit, a voltage detection circuit, a drive circuit, a first resistor R1, a second resistor R2 and a high-voltage PMOS tube MP40,
the power supply ends of the oscillator and the charge pump circuit are connected with the first control end and are powered by the power supply voltage VDD;
the input end of the charge pump circuit is connected with the output end of the oscillator, the output voltage of the charge pump circuit is connected with the input end of the voltage detection circuit, the output voltage of the charge pump circuit is used for generating a supply voltage VDDH of the voltage detection circuit, and the supply voltage VDDH is connected with the power supply end of the driving circuit and the output end of the control module;
the output end of the voltage detection circuit is connected with the input end of the driving circuit and the clock control end of the oscillator, and is connected with the grid electrode of the high-voltage PMOS tube MP40 through a second resistor R2;
the output end of the driving circuit is connected with the third control end;
the first resistor R1 is connected between the first control end and the grid of the high-voltage PMOS tube MP 40;
The drain electrode of the high-voltage PMOS tube MP40 is connected with the second control end, and the source electrode of the high-voltage PMOS tube MP40 is grounded;
The voltage detection circuit comprises a detection module, a band-gap reference source module and a comparator module, wherein the band-gap reference source module is used for generating a band-gap reference voltage Vref and outputting the band-gap reference voltage Vref to a first input end of the comparator module,
the detection module comprises a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, a third resistor R3, a fourth resistor R4 and a fifth resistor R5,
the drain electrode of the seventh PMOS transistor MP7 is used as the input terminal of the voltage detection circuit, the source electrode thereof generates the supply voltage VDDH, and the gate electrode thereof is connected to the gate electrodes of the fourth NMOS transistor MN4, the fifth PMOS transistor MP5, the first NMOS transistor MN1 and the first PMOS transistor MP1, and the drain electrodes of the fourth PMOS transistor MP4 and the third NMOS transistor MN 3;
the sources of the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are connected to the supply voltage VDDH;
a fourth resistor R4 and a fifth resistor R5 are connected in series and in parallel between the supply voltage VDDH and the second input of the comparator block, and a third resistor R3 is connected between the second input of the comparator block and ground;
the grid electrode of the second PMOS tube MP2 is connected with the drain electrodes of the first PMOS tube MP1 and the first NMOS tube MN1, and the drain electrode of the second PMOS tube MP2 is connected with the series point of the fourth resistor R4 and the fifth resistor R5 after passing through the sixth resistor R6;
The grid electrode of the second NMOS tube MN2 is connected with the grid electrode of the third PMOS tube MP3 and the output end of the comparator module, the source electrode of the second NMOS tube MN2 is connected with the source electrodes of the first NMOS tube MN1, the third NMOS tube MN3, the fourth NMOS tube MN4 and the fifth NMOS tube MN5 and is grounded, and the drain electrode of the second NMOS tube MN2 is connected with the drain electrode of the third PMOS tube MP3, the third NMOS tube MN3 and the grid electrode of the fourth PMOS tube MP 4;
the grid electrode of the fifth NMOS transistor MN5 is connected to the grid electrode of the sixth PMOS transistor MP6, the fourth NMOS transistor MN4 and the drain electrode of the fifth PMOS transistor MP5, and the drain electrode thereof is connected to the drain electrode of the sixth PMOS transistor MP6 and serves as the output terminal of the voltage detection circuit.
specifically, the bandgap reference source module includes a seventh resistor R7, an eighth resistor R8, a first triode Q1, a second triode Q2, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, and an eleventh PMOS transistor MP11,
the gate-drain short circuit of the tenth PMOS transistor MP10 connects the gate of the eleventh PMOS transistor MP11 and the source of the eighth PMOS transistor MP8, and the source thereof connects the source of the eleventh PMOS transistor MP11 and the supply voltage VDDH;
the gate of the ninth PMOS transistor MP9 is connected to the gate and the drain of the eighth PMOS transistor MP8 and the collector of the second triode Q2, the source thereof is connected to the drain of the eleventh PMOS transistor MP11, the drain thereof is connected to the base and the collector of the first triode Q1 and the base of the second triode Q2, and the base and the drain are used as the output end of the bandgap reference source module;
The seventh resistor R7 and the eighth resistor R8 are connected in series and in parallel between the emitter of the second transistor Q2 and ground, and the series point is connected to the emitter of the first transistor Q1.
Specifically, the comparator module includes a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fifteenth PMOS transistor MP15, a sixteenth PMOS transistor MP16, and a seventeenth PMOS transistor MP17,
A gate of the sixteenth PMOS transistor MP16 is used as a first input terminal of the comparator module, a source thereof is connected to the drain of the fifteenth PMOS transistor MP15 and the source of the seventeenth PMOS transistor MP17, and a drain thereof is connected to the gate and the drain of the sixth NMOS transistor MN6 and the gate of the seventh NMOS transistor MN 7;
the grid electrode of the seventeenth PMOS tube MP17 is used as the second input end of the comparator module, and the drain electrode of the seventeenth PMOS tube MP17 is connected with the drain electrode of the seventh NMOS tube MN7 and the grid electrode of the eighth NMOS tube MN 8; the source electrodes of the sixth NMOS transistor MN6, the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 are grounded;
The drain of the thirteenth PMOS transistor MP13 is connected to the drain of the eighth NMOS transistor MN8 and serves as the output terminal of the comparator module, the gate thereof is connected to the gate of the fifteenth PMOS transistor MP15 and the gate of the eighth PMOS transistor MP8 in the bandgap reference source module, and the source thereof is connected to the drain of the fourteenth PMOS transistor MP 14;
the gate of the twelfth PMOS transistor MP12 is connected to the gate of the fourteenth PMOS transistor MP14 and the source of the eighth PMOS transistor MP8 in the bandgap reference source module, the drain thereof is connected to the source of the fifteenth PMOS transistor MP15, and the source thereof is connected to the source of the fourteenth PMOS transistor MP14 and is connected to the supply voltage VDDH.
The invention has the beneficial effects that: the voltage detection control circuit provided by the invention is used for a VDMOS power tube as a bypass switch of a main switch tube, improves the driving efficiency of the bypass switch, and has the advantages of obviously reduced average conduction voltage drop, higher reverse withstand voltage and smaller leakage current compared with the traditional bypass switch using a Schottky diode; the voltage detection circuit adopts a built-in comparator, so that the reliability of the preset voltage is guaranteed.
drawings
Fig. 1 is a structural diagram of a voltage detection control circuit for a bypass switch according to the present invention.
fig. 2 is a schematic structural diagram of a control module in a voltage detection control circuit for a bypass switch according to the present invention.
fig. 3 is a waveform diagram of an output of a voltage detection control circuit for a bypass switch according to the present invention.
fig. 4 is a schematic structural diagram of a voltage detection control circuit for a bypass switch according to an embodiment of the present invention.
Fig. 5 is a schematic output diagram of a voltage detection circuit of a voltage detection control circuit for a bypass switch according to the present invention.
Detailed Description
The technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.
the voltage detection control circuit provided by the invention is suitable for a bypass switch taking a VDMOS power tube as a main switching tube, as shown in figure 1, the voltage detection control circuit comprises a first capacitor C1 and a control module, the control module comprises three control ends and an output end, the first control end is connected with the source electrode of the VDMOS power tube and is connected with a power voltage VDD, the second control end is connected with the drain electrode of the VDMOS power tube, the third control end is connected with the grid electrode of the VDMOS power tube, the output end is connected with one end of a first capacitor C1, and the other end of the first capacitor C1 is grounded; the conduction voltage drop of the diode of the VDMOS power tube body is used as the power supply voltage VDD.
The control module comprises an oscillator, a charge pump circuit, a voltage detection circuit, a drive circuit, a first resistor R1, a second resistor R2 and a high-voltage PMOS (P-channel metal oxide semiconductor) transistor MP40, wherein power supply ends of the oscillator and the charge pump circuit are connected with a first control end and are powered by a power supply voltage VDD; the input end of the charge pump circuit is connected with the output end of the oscillator, the output voltage of the charge pump circuit is connected with the input end of the voltage detection circuit, the output voltage of the charge pump circuit is used for generating a power supply voltage VDDH of the voltage detection circuit, and the power supply voltage VDDH is connected with the power supply end of the driving circuit and the output end of the control module; the output end of the voltage detection circuit is connected with the input end of the driving circuit and the clock control end of the oscillator, and is connected with the grid electrode of the high-voltage PMOS tube MP40 after passing through a second resistor R2; the output end of the driving circuit is connected with the third control end; the first resistor R1 is connected between the first control end and the grid of the high-voltage PMOS tube MP 40; the drain of the high voltage PMOS transistor MP40 is connected to the second control terminal, and the source thereof is grounded.
The voltage detection circuit comprises a detection module, a band gap reference source module and a comparator module, wherein the band gap reference source module is used for generating band gap reference voltage Vref and outputting the band gap reference voltage Vref to a first input end of the comparator module, the detection module comprises a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a seventh PMOS tube MP7, a third resistor R3, a fourth resistor R4 and a fifth resistor R5, the first NMOS tube MN1, the first PMOS tube MP1, the second NMOS tube MN2, the third PMOS tube MP3, the third NMOS tube MN3, the fourth tube MP4, the fourth PMOS tube MN4, the fifth PMOS tube MN4, a sixth PMOS tube MP 72 and a fifth PMOS tube 4, and a fifth PMOS 363672 are used as power supply voltage, and a fifth PMOS 36363672 is generated by the PMOS power supply circuit, and a fifth PMOS 36363672, the grid electrodes of the NMOS transistors are connected with the grid electrodes of the fourth NMOS transistor MN4, the fifth PMOS transistor MP5, the first NMOS transistor MN1 and the first PMOS transistor MP1, and the drain electrodes of the fourth PMOS transistor MP4 and the third NMOS transistor MN 3; the sources of the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are connected to a supply voltage VDDH; the fourth resistor R4 and the fifth resistor R5 are connected in series and in parallel between the supply voltage VDDH and the second input terminal of the comparator module, and the third resistor R3 is connected between the second input terminal of the comparator module and ground; the grid electrode of the second PMOS tube MP2 is connected with the drain electrodes of the first PMOS tube MP1 and the first NMOS tube MN1, and the drain electrode of the second PMOS tube MP2 is connected with the series point of the fourth resistor R4 and the fifth resistor R5 after passing through the sixth resistor R6; the grid electrode of the second NMOS tube MN2 is connected with the grid electrode of the third PMOS tube MP3 and the output end of the comparator module, the source electrode of the second NMOS tube MN2 is connected with the source electrodes of the first NMOS tube MN1, the third NMOS tube MN3, the fourth NMOS tube MN4 and the fifth NMOS tube MN5 and is grounded, and the drain electrode of the second NMOS tube MN2 is connected with the drain electrode of the third PMOS tube MP3, the grid electrode of the third NMOS tube MN3 and the grid electrode of the fourth PMOS tube MP 4; the grid electrode of the fifth NMOS transistor MN5 is connected to the grid electrode of the sixth PMOS transistor MP6, the fourth NMOS transistor MN4 and the drain electrode of the fifth PMOS transistor MP5, and the drain electrode thereof is connected to the drain electrode of the sixth PMOS transistor MP6 and serves as the output terminal of the voltage detection circuit.
the bandgap reference source module is configured to generate a bandgap reference voltage Vref as an input signal of the comparator module, and as shown in fig. 4, is an implementation circuit structure of the bandgap reference source module, and includes a seventh resistor R7, an eighth resistor R8, a first triode Q1, a second triode Q2, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, and an eleventh PMOS transistor MP11, where the eighth PMOS transistor MP8, the ninth PMOS transistor MP9, the tenth PMOS transistor MP10, and the eleventh PMOS transistor MP11 form a cascode current mirror, a gate drain of the tenth PMOS transistor 10 is shorted and connected to a gate of the eleventh PMOS transistor MP11 and a source of the eighth PMOS transistor MP8, and a source of the tenth PMOS transistor MP 353526 is connected to a source of the eleventh PMOS transistor MP11 and a power supply voltage VDDH; the gate of the ninth PMOS transistor MP9 is connected to the gate and the drain of the eighth PMOS transistor MP8 and the collector of the second triode Q2, the source thereof is connected to the drain of the eleventh PMOS transistor MP11, the drain thereof is connected to the base and the collector of the first triode Q1 and the base of the second triode Q2, and the base and the drain are used as the output end of the bandgap reference source module; the seventh resistor R7 and the eighth resistor R8 are connected in series and in parallel between the emitter of the second transistor Q2 and ground, and the series point is connected to the emitter of the first transistor Q1.
The comparator module may use a multi-stage comparator, which is used to ensure that the gain of the comparator is large enough to prevent the output voltage of the comparator from being stuck in the middle state, and as shown in fig. 4, the comparator module is a circuit structure for implementing the comparator module, and includes a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fifteenth PMOS transistor MP15, a sixteenth PMOS transistor MP16, and a seventeenth PMOS transistor MP17, wherein the twelfth PMOS transistor MP12, the thirteenth PMOS transistor MP13, the fourteenth PMOS transistor MP14, and the fifteenth PMOS transistor MP15 form a cascode current mirror, the gate of the sixteenth PMOS transistor MP16 is used as the first input terminal of the comparator module, the source thereof is connected to the drain of the fifteenth PMOS transistor MP15 and the source of the seventeenth PMOS transistor MP17, and the drain thereof is connected to the drain of the sixth NMOS transistor MN6 and the NMOS 7; the gate of the seventeenth PMOS transistor MP17 is used as the second input terminal of the comparator module, and the drain thereof is connected to the drain of the seventh NMOS transistor MN7 and the gate of the eighth NMOS transistor MN 8; the source electrodes of the sixth NMOS transistor MN6, the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 are grounded; the drain of the thirteenth PMOS transistor MP13 is connected to the drain of the eighth NMOS transistor MN8 and serves as the output terminal of the comparator module, the gate thereof is connected to the gate of the fifteenth PMOS transistor MP15 and the gate of the eighth PMOS transistor MP8 in the bandgap reference source module, and the source thereof is connected to the drain of the fourteenth PMOS transistor MP 14; the gate of the twelfth PMOS transistor MP12 is connected to the gate of the fourteenth PMOS transistor MP14 and the source of the eighth PMOS transistor MP8 in the bandgap reference source module, the drain thereof is connected to the source of the fifteenth PMOS transistor MP15, and the source thereof is connected to the source of the fourteenth PMOS transistor MP14 and is connected to the supply voltage VDDH.
The working principle of the invention is as follows: when the current flows from the first control end D + to the second control end D-through the VDMOS power tube, the body diode of the VDMOS power tube is conducted, and the voltage is set as VF1The voltage is power supply voltage VDD for supplying power to the control module, and the oscillator in the control module and the power supply end of the charge pump circuit are connected with the power supply voltage VDD; the oscillator is controlled by a clock signal EN output by the voltage detection circuit, the oscillator is started when the clock signal EN is low, and the oscillator is turned off when the clock signal EN is high; when the oscillator is started, clock signals CLK and CLK _ N are generated to drive the charge pump circuit, the charge pump circuit pumps up a power supply voltage VDD supplied for the charge pump circuit, and high voltage CP is output; the voltage detection circuit is used for detecting the high voltage CP output by the charge pump circuit, the high voltage CP output by the charge pump circuit generates a supply voltage VDDH through a seventh PMOS tube MP7 in the voltage detection circuit to charge a first capacitor C1, when the output voltage reaches a preset upper limit (namely a preset value of starting a VDMOS power tube), an output signal EN is at a high level, an oscillator is turned off, the output signal of the driving circuit is also at the high level VDDH at the moment, a third control end G outputs the high level VDDH, the VDMOS power tube is turned on, and the voltage drop of two ends of the VDMOS power tube is reduced to VF2the control module turns off and no longer charges the first capacitor C1. With the charge consumption of the first capacitor C1, when the voltage on the first capacitor C1 drops to a preset lower limit (i.e., a preset value for turning off the VDMOS power transistor), the control module outputs a low level VSS to turn off the VDMOS power transistor, and the voltage across the VDMOS power transistor is restored to V againF1the charge pump circuit continues to pump up the voltage to charge the first capacitor C1. Finally, the voltage drop across the VDMOS power tube is VF1and VF2To switch between. The preset upper limit and the preset lower limit of the capacitor C1 are the preset upper limit and the preset lower limit of the VDMOS power tube, and are set by the voltage detection circuit, and the theoretical value of the preset upper limitThe value of the preset lower limit is to make the VDMOS power tube fully conducted even if the on-resistance is as small as possible.
Since the VDMOS power tube needs to be turned on with larger driving capability, the driving circuit is used for enhancing the driving capability of the output signal of the voltage detection circuit and then is connected to the grid electrode of the VDMOS power tube to control the VDMOS power tube. The charge pump circuit comprises a multi-stage charge pump unit, the stage number of the charge pump circuit can be designed according to the value of preset driving voltage, when larger driving voltage is needed, a multi-stage charge pump can be designed, CP is VDD (N +1), and N is the stage number of the charge pump.
Fig. 3 is a waveform diagram of an output of a voltage detection control circuit for a bypass switch according to the present invention. Setting a period as T and the time of starting a VDMOS power tube as T1the closing time of the VDMOS power tube is T2the duty ratio of the on of the VDMOS power tube is shown by the formula:
The average conduction voltage drop of the voltage detection control circuit of the bypass switch is shown as the formula:
Vave＝m*VF1+(1-m)*VF2
Due to VF1The conduction voltage drop of the proximity diode is much larger than VF2And the duty cycle m is usually small, so the average conduction voltage drop Vavemuch smaller than the conduction voltage drop of the diode.
fig. 5 is a schematic diagram of the output of the voltage detection circuit according to the present invention. Voltages V1 and V2 are the preset upper limit and the preset lower limit of the capacitor C1, and the charge pump charging time is T as the effective driving voltage1Discharge time of T2. The efficiency of the charge pump is:
in summary, compared with the conventional schottky bypass diode, the voltage detection control circuit provided by the invention is used for the bypass switch of the VDMOS power tube as the main switching tube, and has the advantages of obviously reduced average conduction voltage drop, higher reverse withstand voltage, smaller leakage current and the like; the invention carries out the design of the bypass switch module based on the charge pump, realizes the charging stage and the discharging stage through alternate operation, and the charge pump converts an input voltage source into a driving voltage to drive the VDMOS power tube, thereby improving the driving efficiency of the bypass switch, obviously reducing the average conduction voltage drop, and enabling the bypass switch control circuit to have higher reverse withstand voltage value and realize smaller electric leakage by adopting the VDMOS power tube and the high-voltage withstand voltage tube. The traditional bypass switch module changes the preset voltage by adopting the change of the collector voltage, the pump-up voltage of the charge pump is easy to vibrate when the voltage is higher because the fluctuation is larger, and the voltage detection circuit adopts the structure of a built-in comparator to ensure the reliability of the preset voltage aiming at the problem of false triggering of the preset voltage of the bypass switch module caused by larger power supply ripple.
it is to be understood that the invention is not limited to the precise arrangements and components shown above. Various modifications and optimizations may be made to the order of the steps, details and operations of the methods and structures described above without departing from the scope of protection of the claims.

Claims (3)

1. A voltage detection control circuit for a bypass switch, wherein the bypass switch uses a VDMOS power transistor as a main switching transistor, and the voltage detection control circuit comprises a first capacitor (C1) and a control module, wherein the control module comprises three control terminals and an output terminal, the first control terminal is connected to the source of the VDMOS power transistor and to a power Voltage (VDD), the second control terminal is connected to the drain of the VDMOS power transistor, the third control terminal is connected to the gate of the VDMOS power transistor, the output terminal is connected to one end of a first capacitor (C1), and the other end of the first capacitor (C1) is grounded; the conduction voltage drop of the VDMOS power body diode is taken as the power supply Voltage (VDD);
The control module comprises an oscillator, a charge pump circuit, a voltage detection circuit, a drive circuit, a first resistor (R1), a second resistor (R2) and a high-voltage PMOS (MP40),
The power supply ends of the oscillator and the charge pump circuit are connected with the first control end and are powered by the power supply Voltage (VDD);
The input end of the charge pump circuit is connected with the output end of the oscillator, the output voltage of the charge pump circuit is connected with the input end of the voltage detection circuit, the output voltage of the charge pump circuit is used for generating a supply Voltage (VDDH) of the voltage detection circuit, and the supply Voltage (VDDH) is connected with the power supply end of the driving circuit and the output end of the control module;
The output end of the voltage detection circuit is connected with the input end of the driving circuit and the clock control end of the oscillator, and is connected with the grid electrode of a high-voltage PMOS (MP40) after passing through a second resistor (R2);
the output end of the driving circuit is connected with the third control end;
A first resistor (R1) is connected between the first control end and the grid electrode of the high-voltage PMOS tube (MP 40);
The drain electrode of the high-voltage PMOS tube (MP40) is connected with the second control end, and the source electrode of the high-voltage PMOS tube is grounded;
The voltage detection circuit comprises a detection module, a band-gap reference source module and a comparator module, wherein the band-gap reference source module is used for generating a band-gap reference voltage (Vref) and outputting the voltage to a first input end of the comparator module,
The detection module comprises a first NMOS (N-channel metal oxide semiconductor) tube (MN1), a second NMOS tube (MN2), a third NMOS tube (MN3), a fourth NMOS tube (MN4), a fifth NMOS tube (MN5), a first PMOS tube (MP1), a second PMOS tube (MP2), a third PMOS tube (MP3), a fourth PMOS tube (MP4), a fifth PMOS tube (MP5), a sixth PMOS tube (MP6), a seventh PMOS tube (MP7), a third resistor (R3), a fourth resistor (R4) and a fifth resistor (R5),
the drain electrode of the seventh PMOS tube (MP7) is used as the input end of the voltage detection circuit, the source electrode of the seventh PMOS tube (MP7) generates the supply Voltage (VDDH), and the grid electrode of the seventh PMOS tube (MP7) is connected with the grid electrodes of the fourth NMOS tube (MN4), the fifth PMOS tube (MP5), the first NMOS tube (MN1) and the first PMOS tube (MP1), and the drain electrodes of the fourth PMOS tube (MP4) and the third NMOS tube (MN 3);
the source electrodes of the first PMOS tube (MP1), the second PMOS tube (MP2), the third PMOS tube (MP3), the fourth PMOS tube (MP4), the fifth PMOS tube (MP5) and the sixth PMOS tube (MP6) are connected with the supply Voltage (VDDH);
a fourth resistor (R4) and a fifth resistor (R5) are connected in series and in parallel between the supply Voltage (VDDH) and the second input of the comparator block, a third resistor (R3) is connected between the second input of the comparator block and ground;
the grid electrode of the second PMOS tube (MP2) is connected with the drain electrodes of the first PMOS tube (MP1) and the first NMOS tube (MN1), and the drain electrode of the second PMOS tube is connected with the series connection point of a fourth resistor (R4) and a fifth resistor (R5) after passing through a sixth resistor (R6);
The grid electrode of the second NMOS tube (MN2) is connected with the grid electrode of the third PMOS tube (MP3) and the output end of the comparator module, the source electrode of the second NMOS tube is connected with the source electrodes of the first NMOS tube (MN1), the third NMOS tube (MN3), the fourth NMOS tube (MN4) and the fifth NMOS tube (MN5) and is grounded, and the drain electrode of the second NMOS tube is connected with the drain electrode of the third PMOS tube (MP3), the third NMOS tube (MN3) and the grid electrode of the fourth PMOS tube (MP 4);
the grid electrode of the fifth NMOS tube (MN5) is connected with the grid electrode of the sixth PMOS tube (MP6), the drain electrode of the fourth NMOS tube (MN4) and the drain electrode of the fifth PMOS tube (MP5), and the drain electrode of the fifth NMOS tube (MN5) is connected with the drain electrode of the sixth PMOS tube (MP6) and serves as the output end of the voltage detection circuit.
2. The voltage detection control circuit for the bypass switch according to claim 1, wherein the bandgap reference source module comprises a seventh resistor (R7), an eighth resistor (R8), a first transistor (Q1), a second transistor (Q2), an eighth PMOS transistor (MP8), a ninth PMOS transistor (MP9), a tenth PMOS transistor (MP10), and an eleventh PMOS transistor (MP11),
the grid and the drain of the tenth PMOS tube (MP10) are in short circuit and are connected with the grid electrode of the eleventh PMOS tube (MP11) and the source electrode of the eighth PMOS tube (MP8), and the source electrode of the tenth PMOS tube (MP10) is connected with the source electrode of the eleventh PMOS tube (MP11) and the power supply Voltage (VDDH);
The gate of the ninth PMOS tube (MP9) is connected with the gate and the drain of the eighth PMOS tube (MP8) and the collector of the second triode (Q2), the source of the ninth PMOS tube is connected with the drain of the eleventh PMOS tube (MP11), the drain of the ninth PMOS tube is connected with the base and the collector of the first triode (Q1) and the base of the second triode (Q2) and serves as the output end of the band-gap reference source module;
The seventh resistor (R7) and the eighth resistor (R8) are connected in series and in parallel between the emitter of the second triode (Q2) and the ground, and the series point of the seventh resistor (R7) and the eighth resistor (R8) is connected with the emitter of the first triode (Q1).
3. The voltage detection control circuit for the bypass switch of claim 2, wherein the comparator module comprises a sixth NMOS transistor (MN6), a seventh NMOS transistor (MN7), an eighth NMOS transistor (MN8), a twelfth PMOS transistor (MP12), a thirteenth PMOS transistor (MP13), a fourteenth PMOS transistor (MP14), a fifteenth PMOS transistor (MP15), a sixteenth PMOS transistor (MP16), and a seventeenth PMOS transistor (MP17),
A gate of a sixteenth PMOS transistor (MP16) is used as a first input terminal of the comparator module, a source thereof is connected to a drain of the fifteenth PMOS transistor (MP15) and a source of the seventeenth PMOS transistor (MP17), and a drain thereof is connected to a gate and a drain of a sixth NMOS transistor (MN6) and a gate of a seventh NMOS transistor (MN 7);
The grid electrode of a seventeenth PMOS tube (MP17) is used as the second input end of the comparator module, and the drain electrode of the seventeenth PMOS tube is connected with the drain electrode of a seventh NMOS tube (MN7) and the grid electrode of an eighth NMOS tube (MN 8); the sources of the sixth NMOS transistor (MN6), the seventh NMOS transistor (MN7) and the eighth NMOS transistor (MN8) are grounded;
the drain electrode of a thirteenth PMOS tube (MP13) is connected with the drain electrode of an eighth NMOS tube (MN8) and serves as the output end of the comparator module, the grid electrode of the thirteenth PMOS tube is connected with the grid electrode of a fifteenth PMOS tube (MP15) and the grid electrode of an eighth PMOS tube (MP8) in the band-gap reference source module, and the source electrode of the thirteenth PMOS tube is connected with the drain electrode of a fourteenth PMOS tube (MP 14);
the gate of the twelfth PMOS tube (MP12) is connected with the gate of the fourteenth PMOS tube (MP14) and the source of the eighth PMOS tube (MP8) in the bandgap reference source module, the drain of the twelfth PMOS tube is connected with the source of the fifteenth PMOS tube (MP15), and the source of the twelfth PMOS tube is connected with the source of the fourteenth PMOS tube (MP14) and is connected with the supply Voltage (VDDH).
CN201810382381.2A 2018-04-26 2018-04-26 voltage detection control circuit for bypass switch Expired - Fee Related CN108471225B (en)

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CN111565022B (en) * 2020-07-15 2020-11-10 上海南麟电子股份有限公司 Multi-stage series power generation unit group and bypass protection circuit thereof
CN114172363B (en) * 2020-09-10 2023-11-03 瑞昱半导体股份有限公司 charge pump device
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CN113848368B (en) * 2021-09-22 2022-07-08 苏州锴威特半导体股份有限公司 Voltage difference value real-time detection and dynamic adjustment circuit
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