CN115864834A

CN115864834A - Relaxation oscillator suitable for DC-DC converter

Info

Publication number: CN115864834A
Application number: CN202211603170.XA
Authority: CN
Inventors: 吴敏; 艾科; 王壮
Original assignee: Individual
Current assignee: Individual
Priority date: 2022-12-13
Filing date: 2022-12-13
Publication date: 2023-03-28

Abstract

The invention discloses a relaxation oscillator suitable for a DC-DC converter, which comprises a bias circuit, a trimming circuit, a five-tube operational amplifier circuit, a current source branch circuit, a current mirror circuit, a voltage division network circuit, a voltage comparator and a phase inverter circuit, wherein the voltage division network circuit comprises a voltage divider and a voltage divider; the circuit designed by the invention only adopts one voltage comparator to realize the comparison of high and low threshold voltages, thereby realizing low cost and low power consumption; the invention provides the output clock frequency of two modes, realizes the purpose of changing the frequency by changing the internal comparison voltage of the oscillator, can reduce the switching loss in a light load mode, and improves the conversion efficiency of a system; according to the invention, the bias current is accurately copied through the cascode structure, and the current trimming circuit is provided, so that the accurate current can be provided for the circuit under the influence of temperature, process and power supply voltage; the invention is not only suitable for DC-DC converter, but also can be used for circuits such as digital-to-analog converter, motor driving circuit and the like.

Description

Relaxation oscillator suitable for DC-DC converter

Technical Field

The invention relates to the technical field of analog integrated circuits, in particular to a relaxation oscillator suitable for a DC-DC converter.

Background

In a DC-DC converter chip, an oscillator is one of essential key modules, and provides a stable clock signal for a system, and the stable and accurate clock signal can ensure that a logic circuit outputs a correct duty cycle under the modulation of a control signal to turn on or off a power tube, so as to achieve the purpose of regulating an output voltage. The main indicator of the oscillator is the output frequency accuracy.

Since the load of the DC-DC converter is light load, i.e. the output current is very small, the switching loss of the DC-DC converter operating under light load becomes large due to the frequency of the single system, thereby seriously affecting the conversion efficiency of the system. For the condition of modulating frequency according to load requirements, the existing solution is mainly to increase a light-load mode control circuit or change a chip peripheral device to reduce the system clock frequency, but this greatly increases the system design difficulty, and has large area and high cost.

Disclosure of Invention

It is an object of the present invention to provide a relaxation oscillator suitable for a DC-DC converter to solve the problems mentioned in the background art.

In order to achieve the purpose, the invention provides the following technical scheme: a relaxation oscillator suitable for a DC-DC converter comprises a bias circuit, a trimming circuit, a five-tube operational amplifier circuit, a current source branch circuit, a current mirror circuit, a voltage division network circuit, a voltage comparator and a phase inverter circuit, wherein the five-tube operational amplifier circuit is electrically connected with the bias circuit, the trimming circuit, the current source branch circuit and the current mirror circuit respectively, the bias circuit is electrically connected with the trimming circuit, the current source branch circuit is electrically connected with the current mirror circuit, the voltage division network circuit is electrically connected with the current source branch circuit and the current mirror circuit respectively, the input end of the voltage comparator is electrically connected with the current mirror circuit and the voltage division network circuit respectively, and the output end of the voltage comparator is electrically connected with the phase inverter circuit.

Preferably, the five-transistor operation and discharge circuit includes PMOS transistors MP2, MP3, and MP4, NMOS transistors MN11 and MN12, a drain of MP2 is connected to sources of MP3 and MP4, a common drain of MP3 and MN11, a gate of MP3 is connected to a positive phase input terminal FB, a common drain of MP4 and MN12, a gate of MP4 is connected to a negative phase input terminal Vs, a drain of MN12 is connected to a gate of MN18, a gate of MN18 is connected to a gate of MN13, a drain of MN13 is connected to the current source branch circuit, a drain of MN11 is connected to the gate, a common gate of MN11 and MN12, common sources of MN11, MN12, MN18, and MN13, and a source of MN12 is grounded and is respectively connected to the bias circuit, the trimming circuit, and the current mirror circuit.

Preferably, the bias circuit includes NMOS transistors MN1, MN2, MN3, MN4 and PMOS transistors MP1, the MN1 and MN2 share a gate, a drain of the MN1 is connected to the current source I and connected to the gate, the MN3 and MN4 share a gate, the MN3, MN4 and MN12 share a common source, a drain of the MN3 is connected to the gate and connected to a source of the MN1, a drain of the MN4 is connected to a source of the MN2, the MN2 and MP1 share a drain, a gate of the MP1 is connected to the drain, the MP1 is connected to the MP11, the MP1 and MP11 share a common source and a common drain, the MP11 and MP2 share a common source and are connected to a high level VDD, a gate of the MP11 is connected to the EN enable signal terminal, and a drain of the MP11 is connected to a gate of the MP 2.

Preferably, the trimming circuit includes NMOS transistors MN5, MN6, MN7, MN8, MN9, MN10, MN19, MN20, and MN21, and MN3, MN6, MN8, and MN10 share a gate and a common source, MN1, MN5, MN7, and MN9 share a gate, MP11, MN19, MN20, and MN21 share a drain, a source of MN19 is connected to a drain of MN5, a source of MN5 is connected to a drain of MN6, a source of MN20 is connected to a drain of MN7, a source of MN7 is connected to a drain of MN8, a source of MN21 is connected to a drain of MN9, a source of MN9 is connected to a drain of MN10, a gate of MN19 is connected to a control terminal F1, a gate of MN20 is connected to a control terminal F2, and a gate of MN21 is connected to a control terminal F3.

Preferably, the current source branch circuit includes PMOS transistors MP5, MP6, MP7, MP8, MP9 and MP10, and MP2, MP5, MP6, MP7, MP8, MP9 and MP10 share a gate and a common source, and MP6, MP10 and MN18 share a drain and are connected to the source of MP13, MP5, MP7 and MN13 share a drain and are connected to the source of MP14, MP8 and MP14 share a drain, and MP9 and MP13 share a drain and are connected to a mirror circuit, and MP13 and MP14 share a gate and are connected to a voltage divider network circuit.

Preferably, the current mirror circuit includes NMOS transistors MN14, MN15, MN16, and MN17, the drain of MN14 and MP8 is common, the drain of MN15 and MP9 is common, the drain of MN15 is connected to the gate, the gate of MN14 and MN15 is common, the source of MN14 is connected to the drain of MN16, the drain of MN14 is connected to the negative input terminal of the voltage comparator, the source of MN15 is connected to the drain of MN17, the common source of MN16, MN17, and MN13, the source of MN16 is connected to the capacitor C1, the other end of the capacitor C1 is connected to the drain of MN14, the gate of MN15 is connected to the control signal SS terminal, and the gate of MN17 is connected to the VDD terminal.

Preferably, the voltage divider network circuit comprises resistors R1, R2 and R3, one end of R3 is connected to the source of MN17, the other end is connected to R2 and the positive input end of the voltage comparator, the other end of R2 is connected to the gates of R1 and MP14 and the positive input end of the voltage comparator, and the other end of R1 is connected to the reference voltage Vref.

Preferably, the inverter circuit includes inverters INV1, INV2 and INV3, and the output of the voltage comparator is connected to the input terminal of INV1, the output terminal of INV1 is connected to the input terminal of INV2, the output terminal of INV2 is connected to the input terminal of INV3, and the output terminal of INV3 is connected to the output terminal OSC.

Preferably, the voltage comparator includes PMOS transistors MP12, MP13, MP14, MP15, MP16, MP17 and MP18, NMOS transistors MN22, MN23, MN24 and MN25, MP13, MP14 and MP15 common source, the source of MP14 is connected to the drain of MP12, the gate of MP12 is connected to terminal Vb, the common sources of MP12, MP16 and MP17 are connected to terminal VDD, MP16 and MP17 common gate, the gate of MP16 is connected to the drain, the gate of MP16 is connected to the common drain of MN22, the gate of MN22 is connected to the common gate of MN23, the gate of MN23 is connected to the source, the drain of MN23, MP13 and MP18 is connected to the common drain of MN17 and MN25, the gate of MN25 is connected to the gate of MN24, the gate of MN24 is connected to the source, the gate of MN24 and MP15 common drain, the gate of MN22, MN23, MN24 and MN25 is connected to the source of MP14, the drain of MP14 is connected to the source of MP18, and the common source of MP18 is connected to the common source of MP 18.

Compared with the prior art, the invention has the beneficial effects that: the circuit designed by the invention only adopts one voltage comparator to realize the comparison of high and low threshold voltages, thereby realizing low cost and low power consumption; the invention provides the output clock frequency of two modes, realizes the purpose of changing the frequency by changing the internal comparison voltage of the oscillator, can reduce the switching loss in a light load mode, and improves the conversion efficiency of a system; according to the invention, the bias current is accurately copied through the cascode structure, and the current trimming circuit is provided, so that the accurate current can be provided for the circuit under the influence of temperature, process and power supply voltage; the invention is not only suitable for DC-DC converter, but also can be used for circuits such as digital-to-analog converter, motor driving circuit and the like.

Drawings

FIG. 1 is an overall circuit block diagram of the present invention;

FIG. 2 is an overall circuit schematic of the present invention;

FIG. 3 is a schematic diagram of a voltage comparator circuit of the present invention;

FIG. 4 is a graph of square wave signals of the present invention;

FIG. 5 is a sawtooth signal diagram of the present invention;

in the figure: 1. a bias circuit; 2. a trimming circuit; 3. a five-tube operational amplifier circuit; 4. a current source branch circuit; 5. a current mirror circuit; 6. a voltage divider network circuit; 7. a voltage comparator; 8. an inverter circuit.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.

Referring to fig. 1-5, an embodiment of the present invention is shown: a relaxation oscillator suitable for a DC-DC converter comprises a bias circuit 1, a trimming circuit 2, a five-tube operational amplifier circuit 3, a current source branch circuit 4, a current mirror circuit 5, a voltage division network circuit 6, a voltage comparator 7 and a phase inverter circuit 8, wherein the five-tube operational amplifier circuit 3 is respectively electrically connected with the bias circuit 1, the trimming circuit 2, the current source branch circuit 4 and the current mirror circuit 5, the bias circuit 1 is electrically connected with the trimming circuit 2, the current source branch circuit 4 is electrically connected with the current mirror circuit 5, the voltage division network circuit 6 is respectively electrically connected with the current source branch circuit 4 and the current mirror circuit 5, the input end of the voltage comparator 7 is respectively electrically connected with the current mirror circuit 5 and the voltage division network circuit 6, and the output end of the voltage comparator 7 is electrically connected with the phase inverter circuit 8; the five-transistor operational amplifier circuit 3 comprises PMOS transistors MP2, MP3 and MP4, NMOS transistors MN11 and MN12, the drain electrode of the MP2 is connected with the source electrodes of the MP3 and MP4, the common drain electrode of the MP3 and the MN11 is connected with the grid electrode of the MP3, the common drain electrode of the MP4 and the MN12 is connected with the grid electrode of the positive-phase input end FB, the grid electrode of the MP4 is connected with the negative-phase input end Vs, the drain electrode of the MN12 is connected with the grid electrode of the MN18, the grid electrode of the MN18 is connected with the grid electrode of the MN13, the drain electrode of the MN13 is connected with the current source branch circuit 4, the drain electrode of the MN11 is connected with the grid electrode of the MN12, the common source electrodes of the MN11, the MN12, the MN18 and the MN13 are connected with the common source electrode of the MN12, and the source electrode of the MN12 is connected with the bias circuit 1, the trimming circuit 2 and the current mirror circuit 5 respectively; the bias circuit 1 comprises NMOS tubes MN1, MN2, MN3, MN4 and PMOS tubes MP1, the MN1 and the MN2 share a grid electrode, the drain electrode of the MN1 is connected with a current source I and is connected with the grid electrode, the MN3 and the MN4 share a grid electrode, the MN3, the MN4 and the MN12 share a common source electrode, the drain electrode of the MN3 is connected with the grid electrode and is connected with the source electrode of the MN1, the drain electrode of the MN4 is connected with the source electrode of the MN2, the MN2 and the MP1 share a drain electrode, the grid electrode of the MP1 is connected with the drain electrode, the MP1 is connected with the MP11, the MP1 and the MP11 share a common source electrode and a common drain electrode, the MP11 and the MP2 share a common source electrode and are connected with a high level VDD, the grid electrode of the MP11 is connected with an EN enabling signal end, and the drain electrode of the MP11 is connected with the grid electrode of the MP 2; the trimming circuit 2 comprises NMOS tubes MN5, MN6, MN7, MN8, MN9, MN10, MN19, MN20 and MN21, wherein the NMOS tubes MN3, MN6, MN8 and MN10 share a grid electrode and a common source electrode, the NMOS tubes MN1, MN5, MN7 and MN9 share a grid electrode, the NMOS tubes MP11, MN19, MN20 and MN21 share a drain electrode, the source electrode of the NMOS tube MN19 is connected with the drain electrode of the NMOS tube MN5, the source electrode of the NMOS tube MN5 is connected with the drain electrode of the NMOS tube MN6, the source electrode of the NMOS tube MN20 is connected with the drain electrode of the NMOS tube MN7, the source electrode of the NMOS tube MN7 is connected with the drain electrode of the NMOS tube MN8, the source electrode of the NMOS tube MN21 is connected with the drain electrode of the NMOS tube MN9, the source electrode of the NMOS tube MN9 is connected with the drain electrode of the NMOS tube MN10, the gate electrode of the NMOS tube MN19 is connected with a control end F1, the gate electrode of the NMOS tube MN20 is connected with a control end F2, and the gate electrode of the NMOS tube 21 is connected with a control end F3; the current source branch circuit 4 comprises PMOS transistors MP5, MP6, MP7, MP8, MP9 and MP10, and the common gates and common sources of MP2, MP5, MP6, MP7, MP8, MP9 and MP10, and the common drains of MP6, MP10 and MN18, and is connected to the source of MP13, the common drains of MP5, MP7 and MN13, and is connected to the source of MP14, the common drains of MP8 and MP14, and the common drains of MP9 and MP13, and is connected to the common gates of the current mirror circuit 5, MP13 and MP14, and is connected to the voltage dividing network circuit 6; the current mirror circuit 5 comprises NMOS transistors MN14, MN15, MN16 and MN17, the MN14 and MP8 share a drain electrode, the MN15 and MP9 share a drain electrode, the drain electrode of the MN15 is connected with a grid electrode, the MN14 and MN15 share a grid electrode, the source electrode of the MN14 is connected with the drain electrode of the MN16, the drain electrode of the MN14 is connected with the negative electrode input end of the voltage comparator 7, the source electrode of the MN15 is connected with the drain electrode of the MN17, the MN16, the MN17 and MN13 share a common source electrode, the source electrode of the MN16 is connected with a capacitor C1, the other end of the capacitor C1 is connected with the drain electrode of the MN14, the grid electrode of the MN15 is connected with a control signal SS end, and the grid electrode VDD of the MN17 is connected with a VDD end; the voltage division network circuit 6 comprises resistors R1, R2 and R3, one end of the R3 is connected with the source electrode of the MN17, the other end of the R3 is connected with the R2 and the positive input end of the voltage comparator 7, the other end of the R2 is connected with the grids of the R1 and the MP14 and the positive input end of the voltage comparator 7, and the other end of the R1 is connected with a reference voltage Vref end; the inverter circuit 8 comprises inverters INV1, INV2 and INV3, the output end of the voltage comparator 7 is connected with the input end of INV1, the output end of INV1 is connected with the input end of INV2, the output end of INV2 is connected with the input end of INV3, and the output end of INV3 is connected with the output end OSC; the voltage comparator 7 comprises PMOS transistors MP12, MP13, MP14, MP15, MP16, MP17 and MP18, NMOS transistors MN22, MN23, MN24 and MN25, common source of MP13, MP14 and MP15, source of MP14 connected to drain of MP12, gate of MP12 connected to terminal Vb, common source of MP12, MP16 and MP17 connected to terminal VDD, common gate of MP16 and MP17, and gate of MP16 connected to drain, common drain of MP16 and MN22, common gate of MN22 and MN23, and gate of MN23 connected to source, common drain of MN23, common drain of MP17 and MN25, common gate of MN25 and MN24, and gate of MN24 connected to source, common drain of MN24 and MP15, common source of MN22, MN23, MN24 and MN25, and source grounded, gate of MP14 connected to terminal PL, drain of MP14 connected to source of MP18, and gate of MP18 connected to OUT.

The working principle is as follows: when the invention is used, the bias circuit 1 provides current for the whole circuit, and MN 1-MN 4 are cascode structures, so that the current can be more accurately copied, and the precision of the output frequency of the system is ensured; the trimming circuit 2 controls the on and off of the three branches through the control ports F1, F2 and F3, so that the magnitude of the trimming bias current is realized, and the influence of the process, the temperature and the power supply voltage on the oscillator circuit is counteracted; the current source branch circuit 4 is used for charging and discharging the capacitor C1; in the current mirror circuit 5, MN16 is a switch MOS for controlling the charging and discharging of a capacitor, and the width-length ratio of MN14 is n times of MN15, so that after being mirrored, the current flowing through MN14 is n times of MN 15; the voltage division network circuit 6 is used for providing two threshold voltages for the voltage comparator 7; the voltage comparator 7 compares the voltage on the capacitor C1 with two threshold voltagesComparing and outputting square wave signals; the inverter circuit 8 is used for shaping the square wave signal and outputting a clock signal OSC with fixed frequency; in the voltage comparator 7, the MP12 provides current for the core comparator circuit through biasing, the MP13 is positive phase input, the MP15 is negative phase input, on the basis, the other positive phase input end MP14 is added, the MP18 is negative phase end selection switch, and the comparison result is output through the current mirror load of MN22 to MN25 and the MP16 and MP17, so that the structure can be simply and easily realized, the situation of using two comparators is avoided, and the area is greatly reduced; in the five-tube operational amplifier circuit 3, vs is a positive phase input end, a reference voltage Vref is connected, FB is a negative phase input end, and two voltage values fed back by a connected system according to a light load and a heavy load are connected; the feedback value is FB _ H (the FB _ H voltage value is larger than Vref) during heavy load, the feedback value is FB _ L (the FB _ L voltage value is smaller than Vref) during light load, the output OUT of the five-tube operational amplifier circuit 3 is at low level during heavy load, MN13 and MN18 are closed, and MN13 and MN18 are conducted during light load; in a normal mode, namely a heavy-load mode, the five-transistor operational amplifier circuit 3 turns off the MN13 and the MN18 by comparing the Vs voltage and the FB voltage, and combines the currents of the MP5, MP7 and MP8 branches into I ₁ The current of the MP6 branch, the MP9 branch and the MP10 branch are combined into I ₂ And I is ₁ ＝I ₂ (ii) a When the EN enable signal is high-level, all the branches in the circuit start to work, the branch current is obtained by copying a current source I through a cascode current mirror circuit 5, at this time, the negative phase input end of the connecting capacitor C1 is low level, the same phase end is high level, so the voltage comparator 7 outputs OUT _ COPM as high level, the control signal SS obtained through the inverter INV1 of the inverter circuit 8 turns off the MN16, and the current I ₁ Starting to charge the capacitor C1, the voltage VC on the capacitor C1 immediately starts to continuously rise and is sent to the negative phase input end of the voltage comparator 7 to be compared with two high and low thresholds, when the voltage VC is higher than an upper threshold VH, the output level of the voltage comparator 7 is reversed, the output end OSC is high level, the control signal SS is high level, the MN16 is conducted, the capacitor starts to discharge, the voltage starts to fall, the output level of the voltage comparator 7 is reversed until the voltage falls below a lower threshold VL, the output end OSC is low level, the control signal SS is low level, the MN16 is closed, the capacitor C1 starts to charge, and the charging is continuously and repeatedly carried out in such a way that the charging is carried out continuously and repeatedlyDischarging and comparing to obtain a stable clock signal with fixed frequency; since the fixed capacitor charge C1 is discharged using a constant current, the voltage versus current equation for the capacitor C1 is: it = CV the charging time of the capacitor C1 is given by:

the discharge time of the capacitor is:

the period of the oscillator thus obtained is:

/>

finally, the frequency of the oscillator is obtained as follows:

when the system needs to reduce the clock signal after the frequency, through the change of the voltage value of the FB terminal, MN13 and MN18 can be turned on, and the branch currents of MP5, MP6, MP7 and MN10 are discharged to the ground, so as to reduce the current for charging and discharging the capacitor C1, as can be seen from the above formula (4), the current is reduced, the frequency is also reduced, as shown in fig. 4-5, the voltage on the capacitor C1 is charged and discharged to form a sawtooth wave voltage signal, and then the sawtooth wave voltage signal is compared with two threshold voltages to output a square wave clock signal, wherein OSC in the graph is a square wave signal, VC is a sawtooth wave signal, and VH and VL are high and low threshold voltages; the relaxation oscillator suitable for the DC-DC converter provided by the invention provides output clock frequencies of two modes, and realizes the purpose of changing the frequency by changing the internal comparison voltage of the oscillator, so that the system has proper clock frequency no matter under the condition of light load or heavy load, the switching loss under the light load mode can be reduced, and the conversion efficiency of the system is improved.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims

1. A relaxation oscillator suitable for a DC-DC converter comprises a bias circuit (1), a trimming circuit (2), a five-transistor operational amplifier circuit (3), a current source branch circuit (4), a current mirror circuit (5), a voltage division network circuit (6), a voltage comparator (7) and a phase inverter circuit (8), and is characterized in that: the five-tube operational amplifier circuit (3) is electrically connected with the bias circuit (1), the trimming circuit (2), the current source branch circuit (4) and the current mirror circuit (5) respectively, the bias circuit (1) is electrically connected with the trimming circuit (2), the current source branch circuit (4) is electrically connected with the current mirror circuit (5), the voltage division network circuit (6) is electrically connected with the current source branch circuit (4) and the current mirror circuit (5) respectively, the input end of the voltage comparator (7) is electrically connected with the current mirror circuit (5) and the voltage division network circuit (6) respectively, and the output end of the voltage comparator (7) is electrically connected with the phase inverter circuit (8).

2. A relaxation oscillator suitable for use in a DC-DC converter as claimed in claim 1, characterized in that: the five-transistor operational amplifier circuit (3) comprises PMOS transistors MP2, MP3 and MP4, NMOS transistors MN11 and MN12, the drain electrode of the MP2 is connected with the source electrodes of the MP3 and MP4, the MP3 and the MN11 share the drain electrode, the grid electrode of the MP3 is connected with the positive phase input end FB, the MP4 and the MN12 share the drain electrode, the grid electrode of the MP4 is connected with the negative phase input end Vs, the drain electrode of the MN12 is connected with the grid electrode of the MN18, the grid electrode of the MN18 is connected with the grid electrode of the MN13, the drain electrode of the MN13 is connected with the current source branch circuit (4), the drain electrode of the MN11 is connected with the grid electrode, the MN11 and the MN12 share the grid electrode, the MN11 and the common source electrodes of the MN18 and the MN13, and the source electrode of the MN12 is grounded and is respectively connected with the bias circuit (1), the trimming circuit (2) and the current mirror circuit (5).

3. A relaxation oscillator for use in a DC-DC converter as claimed in claim 2, wherein: the bias circuit (1) comprises NMOS tubes MN1, MN2, MN3, MN4 and PMOS tubes MP1, wherein the MN1 and the MN2 share a grid electrode, the drain electrode of the MN1 is connected with a current source I and is connected with the grid electrode, the MN3 and the MN4 share a grid electrode, the MN3, the MN4 and the MN12 share common sources, the drain electrode of the MN3 is connected with the grid electrode and is connected with the source electrode of the MN1, the drain electrode of the MN4 is connected with the source electrode of the MN2, the MN2 and the MP1 share a drain electrode, the grid electrode of the MP1 is connected with the drain electrode, the MP1 is connected with the MP11, the MP1 and the MP11 share common sources and drains, the MP11 and the MP2 share common sources and is connected with a high level VDD, the grid electrode of the MP11 is connected with an EN enabling signal end, and the drain electrode of the MP11 is connected with the grid electrode of the MP 2.

4. A relaxation oscillator suitable for use in a DC-DC converter as claimed in claim 2, characterized in that: the trimming circuit (2) comprises an NMOS tube MN5, MN6, MN7, MN8, MN9, MN10, MN19, MN20 and MN21, wherein the MN3, the MN6, the MN8 and the MN10 share a grid electrode and a common source electrode, the MN1, the MN5, the MN7 and the MN9 share a grid electrode, the MP11, the MN19, the MN20 and the MN21 share a drain electrode, a source electrode of the MN19 is connected with a drain electrode of the MN5, a source electrode of the MN5 is connected with a drain electrode of the MN6, a source electrode of the MN20 is connected with a drain electrode of the MN7, a source electrode of the MN7 is connected with a drain electrode of the MN8, a source electrode of the MN21 is connected with a drain electrode of the MN9, a source electrode of the MN9 is connected with a drain electrode of the MN10, a gate electrode of the MN19 is connected with a control end F1, a gate electrode of the MN20 is connected with a control end F2, and a gate electrode of the MN21 is connected with a control end F3.

5. A relaxation oscillator for use in a DC-DC converter as claimed in claim 2, wherein: the current source branch circuit (4) comprises PMOS tubes MP5, MP6, MP7, MP8, MP9 and MP10, a common gate and a common source of MP2, MP5, MP6, MP7, MP8, MP9 and MP10, a common drain of MP6, MP10 and MN18, a source connected with MP13, a common drain of MP5, MP7 and MN13, a source connected with MP14, a common drain of MP8 and MP14, a common drain of MP9 and MP13, a current mirror circuit (5), a common gate of MP13 and MP14, and a voltage dividing network circuit (6).

6. A relaxation oscillator suitable for use in a DC-DC converter as claimed in claim 2, characterized in that: the current mirror circuit (5) comprises NMOS tubes MN14, MN15, MN16 and MN17, wherein the MN14 and the MP8 share a drain electrode, the MN15 and the MP9 share a drain electrode, the drain electrode of the MN15 is connected with a grid electrode, the MN14 and the MN15 share a grid electrode, the source electrode of the MN14 is connected with the drain electrode of the MN16, the drain electrode of the MN14 is connected with a negative electrode input end of a voltage comparator (7), the source electrode of the MN15 is connected with the drain electrode of the MN17, the MN16, the MN17 and an MN13 share a common source electrode, the source electrode of the MN16 is connected with a capacitor C1, the other end of the capacitor C1 is connected with the drain electrode of the MN14, the grid electrode of the MN15 is connected with a control signal SS end, and the grid electrode of the MN17 is connected with a VDD end.

7. A relaxation oscillator as claimed in claim 5, adapted for use in a DC-DC converter, characterized in that: the voltage division network circuit (6) comprises resistors R1, R2 and R3, one end of the R3 is connected with the source electrode of the MN17, the other end of the R3 is connected with the R2 and the positive input end of the voltage comparator (7), the other end of the R2 is connected with the grids of the R1 and the MP14 and the positive input end of the voltage comparator (7), and the other end of the R1 is connected with a reference voltage Vref end.

8. A relaxation oscillator suitable for use in a DC-DC converter as claimed in claim 1, characterized in that: the inverter circuit (8) comprises inverters INV1, INV2 and INV3, the output end of the voltage comparator (7) is connected with the input end of INV1, the output end of INV1 is connected with the input end of INV2, the output end of INV2 is connected with the input end of INV3, and the output end of INV3 is connected with the output end OSC.

9. A relaxation oscillator suitable for use in a DC-DC converter as claimed in claim 8, characterized in that: the voltage comparator (7) comprises PMOS tubes MP12, MP13, MP14, MP15, MP16, MP17 and MP18, NMOS tubes MN22, MN23, MN24 and MN25, common source of MP13, MP14 and MP15, source of MP14 connected with drain of MP12, gate of MP12 connected with Vb terminal, common source of MP12, MP16 and MP17 connected with VDD terminal, common gate of MP16 and MP17, and gate of MP16 connected with drain, common drain of MP16 and MN22, common gate of MN22 and MN23, and gate of MN23 connected with source, common drain of MN23, common drain of MP13 and MP18, common drain of MP17 and MN25, common gate of MN25 and MN24, and gate of MN24 connected with source, common drain of MN24 and MP15, common drain of MN22, MN23, common drain of MN24 and MN25, and source grounded, gate of MP14 connected with PL terminal, drain of MP14 connected with source of MP18, and common source of MP18 connected with OUT terminal.