CN101257289B - Low-power consumption double-capacitance spread type CMOS oscillator - Google Patents
Low-power consumption double-capacitance spread type CMOS oscillator Download PDFInfo
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- CN101257289B CN101257289B CN2008100471837A CN200810047183A CN101257289B CN 101257289 B CN101257289 B CN 101257289B CN 2008100471837 A CN2008100471837 A CN 2008100471837A CN 200810047183 A CN200810047183 A CN 200810047183A CN 101257289 B CN101257289 B CN 101257289B
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Abstract
The invention discloses a double-capacitance relax-expansion type CMOS oscillator, comprising a double-capacitance circuit, a RS trigger and a comparison circuit. The comparison circuit is composed of a comparator (Comp3) and a trigger D, the two output ends of the double-capacitance circuit are respectively connected with two in-phase input ends of a comparator, the inverting-phase input end of the comparator is connected with a reference voltage. The output end of the comparator is connected with the triggering edge of trigger D, the two output ends of trigger D are respectively connected with the R and S ends of RS trigger, the two output ends of RS trigger are respectively connected with two input ends of the double-capacitance circuit, and one output end of the trigger D is used as a main output end. Compared with prior art, the comparator (Comp3) and the comparator (Comp1 or Comp2) consumes same electric current, whereas, because all the tubes of the trigger D are in open-close state without the needs of biasing circuit, the comparator (Comp3) has less quiescent power drain than that of the comparator (Comp1 or Comp2).The invention has simple circuit structure, small occupation, low power consumption and high efficiency.
Description
Technical field
The invention belongs to switch power technology, be specially a kind of low-power consumption double-capacitance spread type CMOS oscillator, is a kind of CMOS oscillator of simple in structure, low-power consumption, is particularly useful in the portable set.
Background technology
Pierce circuit can be seen in many applications of electronic circuitry.Development of electronic technology as DC/DC converter, capacitive transducer, audio receiver and FM (frequency modulation(FM)) generator etc., just develops towards small size, highly integrated direction at present.As the requisite pierce circuit of these equipment, also promptly helping integrated direction more and developing towards taking still less chip area.The quality of pierce circuit directly has influence on the performance of switch power supply system, so also more and more higher to the requirement of pierce circuit.
Oscillator roughly can be divided into tuned oscillator and nonresonant oscillator two big classes.Tuned oscillator produces and is similar to sinusoidal wave output, and the output of nonresonant oscillator is generally square wave and triangular wave.Because the nonresonant oscillator does not need a lot of discrete components and is suitable in the integrated circuit very much.The nonresonant oscillator roughly has two kinds of constituted modes: a kind of is to utilize comparator to realize; Another kind is to utilize self-excitation mechanism to realize by the oscillating loop that CMOS constitutes.The spread type oscillator utilizes comparator to realize, it has good frequency linearity control ability.Low-power consumption, high efficiency are a trend of Switching Power Supply and portable set, so how reducing power consumption, raising the efficiency also is the challenge that the spread type oscillator is faced.
Fig. 1 has described a kind of circuit theory diagrams of typical double-capacitance spread type oscillator.Two condenser networks 1 are the output for the control comparison circuit 2 that replaces, and the frequency of oscillator is to be determined by constant-current source IO.But the power consumption of the pierce circuit shown in this figure is bigger, and very high to the comparator C omp1 and the comparator C omp2 requirement of comparing in the circuit 2, otherwise the disorder on the logical sequence will occur.
Summary of the invention
The object of the present invention is to provide a kind of low-power consumption double-capacitance spread type CMOS oscillator, this oscillator structure is simple, can reduce power consumption, raises the efficiency.
Low-power consumption double-capacitance spread type CMOS oscillator provided by the invention comprises two condenser networks and rest-set flip-flop; It is characterized in that: it also comprises comparison circuit, comparison circuit is made of comparator and d type flip flop, two outputs of two condenser networks meet two in-phase input end INP1 of comparator respectively, INP2, the inverting input INN of comparator connects reference voltage Vref, the output Cout of comparator connects the triggering edge of d type flip flop, two output Q1 of d type flip flop, Q1 ~ connect respectively two input R of rest-set flip-flop, S, two output Q2 of rest-set flip-flop, Q2 ~ connect two inputs of two condenser networks respectively, one of them output Q1 ~ conduct of d type flip flop is output end vo ut always;
Comparator circuit comprises biasing circuit, NMOS pipe MN20, MN21, MN22, MN23, MN24 and MN26, and PMOS pipe MP21, MP22, MP23 and MP24; Biasing circuit comprises PMOS pipe MP25 and NMOS pipe MN25; The source electrode of PMOS pipe MP25 meets supply voltage VDD, and grid meets the input offset voltage VB of comparator, and drain electrode connects the drain electrode of NMOS pipe MN25; The source ground of NMOS pipe MN25, the drain electrode of grid, drain electrode and PMOS pipe MP25 connects altogether; The grid difference of NMOS pipe MN21, MN22 and MN20 is inverting input INN, in-phase input end INP1 and the INP2 of device as a comparison; Their source electrode connects altogether, connects the drain electrode of NMOS pipe MN26; The drain electrode of NMOS pipe MN21 connects the drain electrode of PMOS pipe MP21, and the drain electrode of NMOS pipe MN22 and MN20 connects altogether, connects the drain electrode of PMOS pipe MP22; The grid of NMOS pipe MN26 connects the grid of NMOS pipe MN25, source ground, and drain electrode connects the source electrode of NMOS pipe MN21; The source electrode of NMOS pipe MN23 and MN24 connects ground connection altogether; The drain electrode of grid and NMOS pipe MN23 connects altogether, connects the drain electrode of PMOS pipe MP23; The drain electrode of NMOS pipe MN24 is the output Cout of device as a comparison; The grid of the grid of PMOS pipe MP21, drain electrode and PMOS pipe MP23 connects altogether, connects the drain electrode of NMOS pipe MN21; Their source electrode connects altogether, meets supply voltage VDD; The drain electrode of PMOS pipe MP23 connects the drain electrode of NMOS pipe MN23; The grid of the grid of PMOS pipe MP22, drain electrode and PMOS pipe MP24 connects altogether, connects the drain electrode of NMOS pipe MN22; Their source electrode also connects altogether, meets supply voltage VDD; The drain electrode of PMOS pipe MP24 meets the output Cout of comparator.
Comparison circuit of the present invention has low-power consumption, high efficiency advantage compared with prior art.Comparison circuit among the present invention is made of a comparator and a d type flip flop, and in existing technology, comparison circuit is made of two comparators.Comparator C omp3 institute's consumed current and comparator C omp1 and Comp2 institute consumed current difference are little, but the d type flip flop in the comparison circuit of the present invention is a digital units, the transistor of its inside all is to be operated on off state, quiescent current is very little, and need not any biasing circuit, so power consumption is very low.And the transistor among comparator C omp1 and the comparator C omp2 all is to be operated in the saturation region, and needs extra biasing circuit.In a word, double-capacitance spread type oscillator circuit structure novelty of the present invention, simple compared with prior art, greatly reduces power consumption, has improved efficient.
Description of drawings
Fig. 1 is the circuit theory diagrams of existing double-capacitance spread type oscillator;
Fig. 2 is the physical circuit figure of comparator among Fig. 1;
Fig. 3 is the circuit theory diagrams of double-capacitance spread type oscillator of the present invention;
Fig. 4 is the circuit diagram corresponding to first kind of execution mode of comparator among Fig. 3;
Fig. 5 is the circuit diagram of second kind of execution mode of comparator among corresponding and Fig. 3;
Fig. 6 is the circuit diagram corresponding to a kind of embodiment of Fig. 3.
Embodiment
The present invention is further detailed explanation below in conjunction with accompanying drawing and example.
As shown in Figure 3, double-capacitance spread type oscillator of the present invention is made of two condenser networks 1, comparison circuit 3 and rest-set flip-flop.Wherein, comparison circuit 3 is made of comparator C omp3 and d type flip flop, two outputs of two condenser networks 1 meet two in-phase input end INP1 and the INP2 of comparator C omp3 respectively, the inverting input INN of comparator C omp3 connects reference voltage Vref, the output Cout of comparator C omp3 connects the triggering edge of d type flip flop, the output Q1 of d type flip flop and Q1 ~ connect respectively input R, the S of rest-set flip-flop, the output Q2 of rest-set flip-flop and Q2 ~ connect two inputs of two condenser networks 1 respectively, the output Q1 ~ conduct of d type flip flop is output end vo ut always.
In the foregoing circuit, the charge and discharge of the electric capacity in two condenser networks 1 are by the output Q2 of rest-set flip-flop and Q2 ~ control.When Q2 output high level " 1 ", Q2 ~ output low level " 0 ", NMOS pipe MN1 ends, the MN2 conducting, and PMOS pipe MP1 conducting, MP2 end, at this moment, constant-current source IO charges to capacitor C 1 by PMOS pipe MP1, and capacitor C 2 is discharged by NMOS pipe MN2.And the process of discharge is very fast, mainly depends on the breadth length ratio of discharge tube.Therefore, when V2 drops to reference voltage Vref when following, V1 can't rise to reference voltage Vref, so comparator C omp3 output low level in this time " 0 ".Along with the continuation of V1 is risen, when V1 surpasses reference voltage Vref, comparator C omp3 will overturn and export high level " 1 ", this is equivalent to rising edge of d type flip flop, make the Q1 end upset of d type flip flop export high level " 1 ", Q1 ~ end upset output low level, thus rest-set flip-flop output Q2 upset is output as low level " 0 ", Q2 ~ upset is output as high level " 1 ".So NMOS pipe MN1 conducting, MN2 end, capacitor C 1 is by NMOS pipe MN1 discharge, and constant-current source IO charges to capacitor C 2 by PMOS pipe MP2.Thereby voltage V1 begins to descend, and voltage V2 begins to rise.Because discharge process is very fast, so V1 drops to reference voltage Vref when following, V2 can't rise to reference voltage Vref, so the Comp3 upset is output as low level " 0 ".Along with the continuation of V2 is risen, when V2 surpasses reference voltage Vref, comparator C omp3 will overturn and export high level " 1 ", this is equivalent to rising edge of d type flip flop, make the Q1 of d type flip flop hold upset output low level " 0 ", Q1 ~ end upset output high level " 1 ", thus making rest-set flip-flop output Q2 overturn once more is output as high level " 1 ", Q2 ~ upset is output as low level " 0 " once more.So go round and begin again, will obtain at output end vo ut place one accurately duty ratio be 50% square wave.After it should be noted that capacitance voltage V1 (or V2) rises to reference voltage Vref, can't descend immediately, it can continue a period of time of rising because of propagation delay Td.Here said propagation delay Td is meant that reaching reference voltage Vref and trigger at capacitance voltage V1 (or V2) carries out the transition period, existing delay in conducting with between disconnecting.The generation of propagation delay Td be by electronic component itself intrinsic delay cause, the time that is spent when for example the comparator C omp3 in the comparison circuit 3 compares input signal, the time that state exchange spent that is used for d type flip flop and rest-set flip-flop, and time of being spent when changing between conducting and shutoff with NMOS pipe MN1 and MN2 of PMOS pipe MP1 and MP2 etc.
As shown in Figure 4, implement circuit for first kind of the comparator C omp3 among the present invention and comprise that biasing circuit 4, NMOS manage MN7, MN8, MN9, MN10 and MN11, and PMOS pipe MP7, MP8 and MP10.Biasing circuit 4 comprises NMOS pipe MN11 and PMOS pipe MP11.The drain electrode of the grid of NMOS pipe MN11, drain electrode and PMOS pipe MP11 connects source ground altogether.The grid of PMOS pipe MP11 meets the input offset voltage VB of biasing circuit 4, and source electrode meets supply voltage VDD, and drain electrode connects the drain electrode of NMOS pipe MN11.The grid difference of NMOS pipe MN7, MN8 and MN9 is inverting input INN, in-phase input end INP1 and the INP2 of device Comp3 as a comparison; Their source electrode connects altogether, is connected on the drain electrode of NMOS pipe MN12; The drain electrode of NMOS pipe MN7 connects the drain electrode of PMOS pipe MP7, and the drain electrode of NMOS pipe MN8 and MN9 connects altogether, is connected on the drain electrode of PMOS pipe MP8.The drain electrode of the grid of PMOS pipe MP7 and MP8 and PMOS pipe MP7 connects altogether, is connected on the drain electrode of NMOS pipe MN7; Their source electrode connects altogether, is connected on the supply voltage VDD; The drain electrode of PMOS pipe MP8 connects the drain electrode of NMOS pipe MN8 and MN9.The grid of PMOS pipe MP10 connects the drain electrode of PMOS pipe MP8, and source electrode meets supply voltage VDD, and the output Cout of device Comp3 as a comparison drains.The grid of NMOS pipe MN12 and MN10 connects altogether, connects the grid of NMOS pipe MN11; Their source electrode also connects altogether, ground connection; The drain electrode of NMOS pipe MN12 connects the source electrode of NMOS pipe MN7, and the drain electrode of NMOS pipe MN10 meets the output Cout of comparator C omp3.
In comparator C omp3 shown in Figure 4, biasing circuit 4 provides offset signal for other parts.Wherein, NMOS pipe MN12 and MN10 are exactly the image current that obtains from biasing circuit by current mirror action, and coming provides bias current for NMOS pipe MN7, MN8, MN9 and MN10.Input INN is the end of oppisite phase of comparator C omp3, and input INP1 and INP2 are two in-phase ends of comparator C omp3.PMOS pipe MP7 and MP8 are respectively the active loads of comparator input pipe, with the output impedance of raising first order circuit, and simultaneously double-end signal are converted into single-ended signal, are transported to the grid of PMOS pipe MP10.As in-phase end input signal INP1 (or INP2) during greater than inverting input signal INN, output Cout is a high level just; As in-phase end input signal INP1 and INP2 during all less than inverting input signal INN, output Cout is a low level just.
As shown in Figure 5, implement circuit for second kind of the comparator circuit Comp3 among the present invention and comprise biasing circuit 5, NMOS pipe MN20, MN21, MN22, MN23, MN24 and MN26, and PMOS pipe MP21, MP22, MP23 and MP24.Biasing circuit 5 comprises PMOS pipe MP25 and NMOS pipe MN25.The source electrode of PMOS pipe MP25 meets supply voltage VDD, and grid meets the input offset voltage VB of comparator C omp3, and drain electrode connects the drain electrode of NMOS pipe MN25; The source ground of NMOS pipe MN25, the drain electrode of grid, drain electrode and PMOS pipe MP25 connects altogether.The grid difference of NMOS pipe MN21, MN22 and MN20 is inverting input INN, in-phase input end INP1 and the INP2 of device Comp3 as a comparison; Their source electrode connects altogether, connects the drain electrode of NMOS pipe MN26; The drain electrode of NMOS pipe MN21 connects the drain electrode of PMOS pipe MP21, and the drain electrode of NMOS pipe MN22 and MN20 connects altogether, connects the drain electrode of PMOS pipe MP22.The grid of NMOS pipe MN26 connects the grid of NMOS pipe MN25, source ground, and drain electrode connects the source electrode of NMOS pipe MN21.The source electrode of NMOS pipe MN23 and MN24 connects ground connection altogether; The drain electrode of grid and NMOS pipe MN23 connects altogether, connects the drain electrode of PMOS pipe MP23; The drain electrode of NMOS pipe MN24 is the output Cout of device Comp3 as a comparison.The grid of the grid of PMOS pipe MP21, drain electrode and PMOS pipe MP23 connects altogether, connects the drain electrode of NMOS pipe MN21; Their source electrode connects altogether, meets supply voltage VDD; The drain electrode of PMOS pipe MP23 connects the drain electrode of NMOS pipe MN23.The grid of the grid of PMOS pipe MP22, drain electrode and PMOS pipe MP24 connects altogether, connects the drain electrode of NMOS pipe MN22; Their source electrode also connects altogether, meets supply voltage VDD; The drain electrode of PMOS pipe MP24 meets the output Cout of comparator C omp3.
In comparator C omp3 shown in Figure 5, the effect of the biasing circuit 4 among the effect of biasing circuit 5 and the comparator C omp3 shown in Figure 4 is the same.
Can obtain from Fig. 3, the charging interval of capacitor C 1 (or C2) is:
In the following formula, V
HRefer to the high level of capacitance voltage V1 (or V2), equal reference voltage Vref; V
LRefer to the low level of capacitance voltage V1 (or V2), equal 0; C refers to capacitor C 1 (equal'sing C2) value; I
0The value that refers to constant-current source IO.Therefore, the output frequency of oscillator:
Wherein, t
rBe the charging interval of electric capacity, t
dBe the propagation delay time.
Comparison diagram 1 and Fig. 3 as can be seen, in the double-capacitance spread type pierce circuit principle shown in Figure 3, comparator C omp3 in the comparison circuit 3 and d type flip flop have replaced two comparator C omp1 and the Comp2 in the comparison circuit 2 among Fig. 1.The shared chip area of comparison circuit 2 and comparison circuit 3 is about the same.From Fig. 2 and Fig. 4 as can be seen, comparator C omp3 is only than the NMOS pipe in comparator Comp1 (or Comp2) many places, so comparator C omp1 (or Comp2) almost is the same with comparator C omp3 institute consumed current.But the d type flip flop in the comparison circuit 3 is a simple digital circuit, and its all metal-oxide-semiconductors all are operated on off state, and need not any biasing circuit, so its quiescent dissipation is very little.And the metal-oxide-semiconductor among the comparator C omp1 (or Comp2) all must operate at the saturation region, all needs biasing circuit ability operate as normal separately.So the power consumption of comparator C omp1 (or Comp2) is big more a lot of than d type flip flop.
In a word, compared to Figure 1 Fig. 3 though increased a d type flip flop circuit, has reduced by a comparator circuit, and this makes Fig. 3 take under chip area and Fig. 1 situation about the same, has reduced power consumption greatly and has improved efficient.
For example the present invention is made further detail analysis below.
As shown in Figure 6, the constant-current source circuit in two condenser networks 1 comprises PMOS pipe MP12, MP13 and MP14, and fixing bias current sources I1.Except constant-current source circuit, two condenser networks 1 also comprise PMOS pipe MP1 and MP2, NMOS pipe MN1 and MN2, and capacitor C 1 and C2.Bias current sources I1 negativing ending grounding, the drain electrode of positive termination PMOS pipe MP12.The source electrode of PMOS pipe MP12, MP13 and MP14 connects altogether, meets supply voltage VIN; Grid also connects altogether, connects the drain electrode of PMOS pipe MP12; The drain electrode of PMOS pipe MP13 and MP14 connects the source electrode of PMOS pipe MP1 and the source electrode of PMOS pipe MP2 respectively.The source electrode of NMOS pipe MN1 and MN2 connects ground connection altogether; Their drain electrode connects the drain electrode of PMOS pipe MP1 and the drain electrode of MP2 respectively, and grid connects the Q2 ~ output and the Q2 output of rest-set flip-flop respectively.The grid of PMOS pipe MP1 connects the grid of NMOS pipe MN1, drain electrode, the source electrode that meets NMOS pipe MN1 that drain connects the drain electrode that PMOS manages MP13.The grid of PMOS pipe MP2 connects the grid of NMOS pipe MN2, drain electrode, the source electrode that meets NMOS pipe MN2 that drain connects the drain electrode that PMOS manages MP14.The bottom crown of capacitor C 1 and C2 connects altogether, ground connection; Top crown connects the grid of NMOS pipe MN8 and MN9 respectively.
The formation of comparator C omp3 in the comparison circuit 3 is identical with structure shown in Figure 4.Wherein, input signal VB and Vref are the bias voltages that inserts from other module.
The circuit structure of the d type flip flop in the comparison circuit 3 can be realized with existing typical circuit structure.The clock input signal CP that its rising edge triggers connects the output of comparator C omp3; Input D and the output Q1 of self ~ connect altogether, meet the output signal Vout of oscillator; Output Q1 meets the input R of rest-set flip-flop.
The circuit structure of rest-set flip-flop can be realized with existing typical circuit structure.Its input R connects the Q1 output of d type flip flop in the comparison circuit 3; Input S connect the output Q1 of d type flip flop in the comparison circuit 3 ~; Output Q2 connects the grid of NMOS pipe MN2; The grid of output Q2 ~ connect NMOS pipe MN1.
PMOS pipe MP13 and MP14 in two condenser networks 1 obtain constant electric current I O by current mirror, give capacitor C 1 and C2 charging respectively.Charging current is B*I1, and wherein, B is a constant, the breadth length ratio of its expression PMOS pipe MP13 (or MP14) and PMOS pipe MP12, and I1 represents the bias current fixed.If the initial condition Q2 of rest-set flip-flop is a high level, Q2 ~ be low level, then NMOS pipe MN1 is by, MN2 conducting, and PMOS manages MP1 and MP13 conducting, MP2 and MP14 end.Capacitor C 1 charging, C1 discharge.Because discharge process is very fast, so when V2 drops to reference voltage Vref when following, V1 can't rise to Vref, so comparator C omp3 in this time output low level still.Along with the continuation of V1 is risen, will reach Vref, at this moment, comparator C omp3 will overturn, the output high level.The input signal CP of d type flip flop is by low transition during to high level, output Q1 and Q1 ~ all can overturn, and export high level and low level respectively.At this moment, the output signal Vout of oscillator is a low level by original high level upset also.So, the output Q2 of rest-set flip-flop and Q2 ~ will and then overturn difference output low level and high level.This makes NMOS pipe MN1 conducting, MN2 end.Capacitor C 1 discharge, C2 charging.Because discharge process is very fast, so when V1 dropped to reference voltage Vref, V2 can't rise to Vref, this moment the comparator C omp3 output low level of can overturning.When V2 rises to reference voltage Vref, the comparator C omp3 output high level that will overturn.Make the output Q1 of d type flip flop and Q1 ~ upset simultaneously, output low level and high level respectively.At this moment, oscillator output Vout overturns once more and is high level.So, the output Q2 of rest-set flip-flop and Q2 ~ also be turned into simultaneously once more high level and low level.This gets back to initial condition again, so repeatedly, just can obtain duty ratio and be 50% output square wave.
In existing double-capacitance spread type oscillator, if because the imbalance of circuit or technology causes comparator C omp1 and comparator C omp2 well not to mate, the output of these two comparators just can not be overturn simultaneously so, two inputs of rest-set flip-flop just might keep moment with a kind of level " 1 " or " 0 ", and this is that double-capacitance spread type oscillator institute is unallowed.Therefore, in the existing technology, very high to the precision and the requirement of the matching degree between them of comparator Comp1 and Comp2 circuit.And in comparison circuit of the present invention, because a comparator C omp3 is only arranged, so just do not have the matching problem.This has just reduced the difficulty of comparator C omp3 design, thereby can utilize simple circuit configuration to reduce its power consumption.In comparison circuit, INN is the inverting input of device Comp3 as a comparison, and INP1 and INP2 difference be the in-phase input end of device Comp3 as a comparison; Cout is the output of comparator C omp3.As the in-phase input end signal INP1 of comparator C omp3 and INP2 during all less than inverting input signal INN, the output end vo ut of comparator C omp3 is a low level just; As in-phase input end signal INP1 (or INP2) during greater than inverting input signal INN, the output Cout of comparator C omp3 is a high level just.When the output end vo ut of comparator C omp3 is high level by low transition, will give rising edge signal of CP input of d type flip flop, make two output Q1 of d type flip flop and Q1 ~ overturn.In addition, the d type flip flop in the double-capacitance spread type oscillator of the present invention in the comparison circuit is an existing typical circuit, and its quiescent dissipation is almost nil.
Claims (1)
1. a low-power consumption double-capacitance spread type CMOS oscillator comprises two condenser networks (1) and rest-set flip-flop; It is characterized in that: it also comprises comparison circuit (3), comparison circuit (3) is made of comparator and d type flip flop, two outputs of two condenser networks (1) meet two in-phase input end INP1 of comparator respectively, INP2, the inverting input INN of comparator connects reference voltage Vref, the output Cout of comparator connects the triggering edge of d type flip flop, two output Q1 of d type flip flop, Q1 ~ connect respectively two input R of rest-set flip-flop, S, two output Q2 of rest-set flip-flop, Q2 ~ connect two inputs of two condenser networks (1) respectively, one of them output Q1 ~ conduct of d type flip flop is output end vo ut always;
Comparator circuit comprises biasing circuit (5), NMOS pipe MN20, MN21, MN22, MN23, MN24 and MN26, and PMOS pipe MP21, MP22, MP23 and MP24; Biasing circuit (5) comprises PMOS pipe MP25 and NMOS pipe MN25; The source electrode of PMOS pipe MP25 meets supply voltage VDD, and grid meets the input offset voltage VB of comparator, and drain electrode connects the drain electrode of NMOS pipe MN25; The source ground of NMOS pipe MN25, the drain electrode of grid, drain electrode and PMOS pipe MP25 connects altogether; The grid difference of NMOS pipe MN21, MN22 and MN20 is inverting input INN, in-phase input end INP1 and the INP2 of device as a comparison; Their source electrode connects altogether, connects the drain electrode of NMOS pipe MN26; The drain electrode of NMOS pipe MN21 connects the drain electrode of PMOS pipe MP21, and the drain electrode of NMOS pipe MN22 and MN20 connects altogether, connects the drain electrode of PMOS pipe MP22; The grid of NMOS pipe MN26 connects the grid of NMOS pipe MN25, source ground, and drain electrode connects the source electrode of NMOS pipe MN21; The source electrode of NMOS pipe MN23 and MN24 connects ground connection altogether; The drain electrode of grid and NMOS pipe MN23 connects altogether, connects the drain electrode of PMOS pipe MP23; The drain electrode of NMOS pipe MN24 is the output Cout of device as a comparison; The grid of the grid of PMOS pipe MP21, drain electrode and PMOS pipe MP23 connects altogether, connects the drain electrode of NMOS pipe MN21; Their source electrode connects altogether, meets supply voltage VDD; The drain electrode of PMOS pipe MP23 connects the drain electrode of NMOS pipe MN23; The grid of the grid of PMOS pipe MP22, drain electrode and PMOS pipe MP24 connects altogether, connects the drain electrode of NMOS pipe MN22; Their source electrode also connects altogether, meets supply voltage VDD; The drain electrode of PMOS pipe MP24 meets the output Cout of comparator.
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| CN104993808A (en) * | 2015-07-01 | 2015-10-21 | 东南大学 | RS trigger composed of GaN-based low-leakage-current cantilever beam switch NOR gates |
| CN105048999A (en) * | 2015-07-01 | 2015-11-11 | 东南大学 | GaN-based low-leakage current dual-cantilever beam switch NOR gate RS trigger |
| CN104935297B (en) * | 2015-07-01 | 2017-06-09 | 东南大学 | Based on silicon substrate low-leakage current double cantilever beam can moving grid nor gate rest-set flip-flop |
| CN105048999B (en) * | 2015-07-01 | 2017-09-15 | 东南大学 | Gallium nitride base low-leakage current double cantilever beam switchs the rest-set flip-flop of nor gate |
| CN104993808B (en) * | 2015-07-01 | 2017-09-15 | 东南大学 | The rest-set flip-flop of gallium nitride base low-leakage current cantilever switch nor gate |
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| CN101257289A (en) | 2008-09-03 |
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