CN115333510A - Relaxation oscillator sharing comparator - Google Patents
Relaxation oscillator sharing comparator Download PDFInfo
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- CN115333510A CN115333510A CN202211002370.XA CN202211002370A CN115333510A CN 115333510 A CN115333510 A CN 115333510A CN 202211002370 A CN202211002370 A CN 202211002370A CN 115333510 A CN115333510 A CN 115333510A
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- Prior art keywords
- comparator
- signal
- relaxation oscillator
- clocks
- module
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
- H03K3/0231—Astable circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
- Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses a relaxation oscillator sharing a comparator, belonging to the technical field of relaxation oscillators sharing a comparator, and comprising: an oscillator core module including a current source I OSC Capacitor C 1 And a capacitor C 2 The operation is that two phases of clocks ph1 and ph2 which are not overlapped are input, and the processed clocks are output as voltages V1 and V2 on two capacitors; the alternative MUX module is operated on the input voltages V1 and V2 and outputs a processed voltage V12; the comparator is operated on the voltage V12 output by the input alternative MUX module, and when the voltage V12 reaches the reference direct-current voltage Vref of the negative terminal of the comparator, the output of the comparator is inverted from low to high; the rising edge-to-pulse module is operated to acquire a signal which is overturned from low to high and simultaneously generate a pulse output signal RS; a one-to-two DEMUX module. Book (I)The relaxation oscillator of the invention shares one comparator, and can solve the problems of double power consumption and larger chip area caused by using two comparators in the traditional circuit.
Description
Technical Field
The invention belongs to the technical field of design of analog integrated circuits, and particularly relates to a relaxation oscillator sharing a comparator.
Background
Clocks are required in most integrated circuits. The source of the on-chip clock, except for the off-chip input, must be generated by an integrated oscillator module. Figure 1 is a circuit diagram of a relaxation oscillator using two capacitors that are alternately charged and discharged. In the conventional circuit, two comparators are used to control the maximum voltage amplitude reached at the end of charging the two capacitors, respectively. The capacitors C1 and C2 are alternately charged and discharged. If the input offset voltage (input offset voltage) and the output inverting delay of the two comparators are ignored, the current charges the voltage V1 (or) V2 on the capacitor C1 (or) C2 from zero at each charging, and the other capacitor C2 (or) C1 maintains the discharging state, and the voltage V2 (or) V1 is stopped at zero.
As mentioned above, the comparator has two main non-ideal factors, namely input offset voltage and output flip-flop delay. In practical chip designs, non-idealities of these two comparators adversely affect oscillator performance, such as temperature drift which increases frequency. Therefore, to reduce the adverse effects, it is necessary to reduce the input offset voltage and output flip-flop delay of the comparator. Improving both of these performances of the comparator requires a significant increase in power consumption and area of the comparator.
In addition, the input offset voltage and the output flip-flop delay of the two comparators have the problem of mismatch (mismatch) respectively. When the frequency of the oscillator is higher and a precise duty-cycle is required, the power consumption and area of the comparator are also required to be further increased in order to reduce the performance loss caused by mismatch.
Disclosure of Invention
The invention aims to provide a relaxation oscillator sharing a comparator, which aims to solve the problems of double power consumption and larger chip area caused by using two comparators in the relaxation oscillator.
In order to achieve the purpose, the invention provides the following technical scheme: a relaxation oscillator sharing a comparator, the relaxation oscillator comprising:
an oscillator core module including a current source I OSC Capacitor C 1 And a capacitorC 2 The operation is that two phases of clocks ph1 and ph2 which are not overlapped are input, and the processed clocks are output as voltages V1 and V2 on two capacitors;
an alternative MUX module, operating on the input voltages V1 and V2, and outputting a processed voltage V12;
the comparator is operated on the voltage V12 output by the input alternative MUX module, and when the voltage V12 reaches the reference direct-current voltage Vref of the negative terminal of the comparator, the output of the comparator is turned from low to high;
the rising edge-to-pulse module is operated to acquire a signal which is overturned from low to high and simultaneously generate a pulse output signal RS;
a one-to-two DEMUX module for receiving the pulse output signal RS and sequentially and alternately decomposing the RS pulse signal into R reset And S set A signal;
and the RS latch is operated on the input R and S signals, processes the R and S signals and outputs two-phase overlapped clocks ph1 and ph2 and reversed clocks ph1b and ph2b of the two-phase overlapped clocks.
Preferably, the relaxation oscillator further comprises:
and the delay module is operated to input two phases of non-overlapping clocks ph1 and ph2 and input two phases of non-overlapping clocks ph1d and ph2d to the one-by-two DEMUX module after processing.
Preferably, the operation timing of the relaxation oscillator is divided into an disabled state and an enabled state.
Preferably, when the relaxation oscillator is in the non-enabled operating state, the enable signal en is low, the inverse signal enb thereof is high, and the clocks ph1d and ph2d are both low.
Preferably, when the relaxation oscillator is in an enabled state, one oscillation period of the operation of the relaxation oscillator consists of a first half oscillation period and a second half oscillation period.
Compared with the prior art, the invention has the beneficial effects that:
1) The relaxation oscillator of the invention shares the comparator, thereby saving the area and power consumption of a chip.
2) The relaxation oscillator avoids clock duty ratio errors caused by mismatching between the two comparators, such as input offset voltage and output turnover delay.
3) The relaxation oscillator has the advantages of simple and reliable circuit implementation, only a small amount of switch digital logic is added, and the power consumption and the area of the relaxation oscillator can be ignored.
4) The relaxation oscillator converts the rising edge output by the comparator into narrow pulse, and completes the DEMUX function through the delayed switch, thereby skillfully solving the technical problem in the invention.
5) The present invention, like the above design techniques, can also be used in other different chips.
Drawings
Figure 1 is a conventional relaxation oscillator using two comparators;
figure 2 is a relaxation oscillator of the present invention sharing one comparator;
figure 3 is a functional block diagram of a relaxation oscillator of the present invention;
figure 4 is a timing diagram of internal signals of a relaxation oscillator of the present invention;
figure 5 is a circuit diagram of the pulse generation and clock delay of the relaxation oscillator of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
Fig. 2 is a circuit diagram of a relaxation oscillator sharing a comparator according to an embodiment of the present invention, and fig. 3 is a functional principle and a signal control and generation diagram of the relaxation oscillator according to the present invention.
Principle the oscillator core block in fig. 3 is formed by the current source I in the circuit diagram 2 OSC Capacitor C 1 And C 2 And a switch S 1 ～S 4 And (4) forming. As shown in FIG. 4, the input of the module is two non-overlapping clocks ph1 and ph2, and the output is two capacitorsAnd voltages V1 and V2. The alternative MUX module of FIG. 3 is composed of the switch S of FIG. 2 5 And S 6 Forming; the inputs to the module are voltages V1 and V2 and the output is voltage V12 shown in fig. 4.
The output of the comparator flips from low to high whenever the positive side input voltage V12 of the comparator reaches its negative side reference dc voltage Vref. At this time, the rising edge pulse-to-pulse module after the comparator will generate a very narrow (e.g. about 1 nanosecond) pulse output signal RS.
The DEMUX module after the pulse generation module takes charge of sequentially and alternately decomposing the RS pulse signal into R reset And S set The signal is used as the input of the RS latch afterwards. DEMUX Module in FIG. 3, by switch S in FIG. 2 7 ～S 10 And (4) forming. The initial states of the R and S signals (i.e. when the enable signal en is low and its inverse signal enb is high), via the switch S 11 And S 12 Set to a low potential and a high potential, respectively.
And finally, the output of the RS latch is the two-phase overlapped clocks ph1 and ph2 and the inverted clocks ph1b and ph2b thereof. The specific signal timing and control relationships are shown in fig. 4.
The operation timing of the relaxation oscillator of the present invention is shown in fig. 3 and described as follows:
when the oscillator is in the disabled state, nodes R and S are respectively connected via switch S 11 And S 12 Set to a low potential and a high potential. Therefore, in the initial state, the clocks ph1, ph1d, ph2b are all high, and ph2, ph2d, ph1b are all low.
When the oscillator starts to be enabled, switch S 1 And S 4 Closing, S 2 And S 3 And (4) disconnecting. Current source I OSC Starting to the capacitor C 1 Charging, on which the voltage V1 starts to rise, and the capacitor C 2 In the discharged state, the voltage V1 thereon is kept at zero.
At this time switch S s Closing, S 6 Off, so the alternative MUX outputs voltage V12= V1. When the capacitance C 1 Continuously charging to voltage V12= V ref When the output of the comparator is from low to lowHigh flip, then rising edge to the rising edge of the pulse conversion module output pulse. At this time, the switch controlled by the clock ph1d is still closed, so the signal R generates a rising edge, further triggering the output of the RS latch to flip, i.e., the clock ph1 goes low and ph2 goes high. The first half of the oscillation period ends.
When clock ph2 goes high and ph1 goes low, capacitor C 1 Is rapidly discharged, and the capacitor C 2 Charging, the second half of the oscillation cycle begins. The second half of the oscillation period is similar to the first half period described previously. When the latter oscillation period ends, the next oscillation period is started again.
It should be noted that in order to let the narrow pulse RS pass through the switch S 7 Or S 6 Control switch S 7 ～S 10 The delay (delay) of the clocks ph1d and ph2d with respect to the clocks ph1 and ph2 must be larger than the width of the pulse RS. Drawing (A) 5 This is an example of an implementation of the narrow pulse RS and the delayed clocks ph1d and ph2d generation circuit. In fig. 5, the clock delay is about twice the narrow pulse width. For example, the width of the narrow pulse RS is 1ns, and the delay of ph1d and ph2d relative to the clocks ph1 and ph2 is 2ns. In addition, when the oscillator of the present invention is not enabled, i.e., en is low and enb is high, both clocks ph1d and ph2d are low to turn the switch S on 7 ～S 10 All are disconnected. As before, nodes R and S are now connected through switch S 11 And S 12 Set to a low potential and a high potential.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all changes and modifications that fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (5)
1. A comparator-shared relaxation oscillator, comprising:
an oscillator core module including a current source I OSC Capacitor C 1 And a capacitor C 2 The operation is that two phases of clocks ph1 and ph2 which are not overlapped are input, and the processed clocks are output as voltages V1 and V2 on two capacitors;
the alternative MUX module is operated on the input voltages V1 and V2 and outputs a processed voltage V12;
the comparator is operated on the voltage V12 output by the input alternative MUX module, and when the voltage V12 reaches the reference direct-current voltage Vref of the negative terminal of the comparator, the output of the comparator is inverted from low to high;
the rising edge-to-pulse module is operated to acquire a signal which is overturned from low to high and simultaneously generate a pulse output signal RS;
the one-to-two DEMUX module is operated to receive the pulse output signal RS and sequentially and alternately decompose the RS pulse signal into an R signal and an S signal;
and the RS latch is operated on the input R signal and the S signal, processes the R signal and the S signal and outputs two-phase overlapped clocks ph1 and ph2 and inverted clocks ph1b and ph2b thereof.
2. The comparator-shared relaxation oscillator of claim 1, further comprising:
and the delay module is operated to input two phases of non-overlapping clocks ph1 and ph2 and input two phases of non-overlapping clocks ph1d and ph2d to the one-by-two DEMUX module after processing.
3. The relaxation oscillator with shared comparator as claimed in claim 2, wherein the operation timing of the relaxation oscillator is divided into an disabled state and an enabled state.
4. The relaxation oscillator of claim 3 wherein when the relaxation oscillator is in the disabled state, the enable signal en is low and its inverted signal enb is high, and the clocks ph1d and ph2d are both low.
5. The relaxation oscillator of claim 3 wherein the relaxation oscillator operates with an oscillation period consisting of a first half oscillation period and a second half oscillation period when the relaxation oscillator is enabled.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211002370.XA CN115333510A (en) | 2022-08-19 | 2022-08-19 | Relaxation oscillator sharing comparator |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211002370.XA CN115333510A (en) | 2022-08-19 | 2022-08-19 | Relaxation oscillator sharing comparator |
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| CN115333510A true CN115333510A (en) | 2022-11-11 |
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| CN202211002370.XA Pending CN115333510A (en) | 2022-08-19 | 2022-08-19 | Relaxation oscillator sharing comparator |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101257289A (en) * | 2008-03-28 | 2008-09-03 | 华中科技大学 | Low-power consumption double-capacitance spread type CMOS oscillator |
| US20130234801A1 (en) * | 2012-03-12 | 2013-09-12 | Freescale Semiconductor, Inc. | Oscillator circuit |
| EP2887545A1 (en) * | 2013-12-17 | 2015-06-24 | ams AG | Oscillator circuit |
| US10734975B1 (en) * | 2019-05-08 | 2020-08-04 | Nxp Usa, Inc. | Current-controlled oscillator |
| EP3852268A4 (en) * | 2019-11-19 | 2021-07-21 | Shenzhen Goodix Technology Co., Ltd. | Oscillation circuit, chip, and electronic device |
| CN113922813A (en) * | 2021-10-18 | 2022-01-11 | 苏州聚元微电子股份有限公司 | Frequency calibration method of numerical control oscillator |
| CN113938115A (en) * | 2021-10-18 | 2022-01-14 | 苏州聚元微电子股份有限公司 | Method for synchronizing clocks of switch type DC converter |
-
2022
- 2022-08-19 CN CN202211002370.XA patent/CN115333510A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101257289A (en) * | 2008-03-28 | 2008-09-03 | 华中科技大学 | Low-power consumption double-capacitance spread type CMOS oscillator |
| US20130234801A1 (en) * | 2012-03-12 | 2013-09-12 | Freescale Semiconductor, Inc. | Oscillator circuit |
| EP2887545A1 (en) * | 2013-12-17 | 2015-06-24 | ams AG | Oscillator circuit |
| US10734975B1 (en) * | 2019-05-08 | 2020-08-04 | Nxp Usa, Inc. | Current-controlled oscillator |
| EP3852268A4 (en) * | 2019-11-19 | 2021-07-21 | Shenzhen Goodix Technology Co., Ltd. | Oscillation circuit, chip, and electronic device |
| CN113922813A (en) * | 2021-10-18 | 2022-01-11 | 苏州聚元微电子股份有限公司 | Frequency calibration method of numerical control oscillator |
| CN113938115A (en) * | 2021-10-18 | 2022-01-14 | 苏州聚元微电子股份有限公司 | Method for synchronizing clocks of switch type DC converter |
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