CN113938115A - Method for synchronizing clocks of switch type DC converter - Google Patents

Method for synchronizing clocks of switch type DC converter Download PDF

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CN113938115A
CN113938115A CN202111211886.0A CN202111211886A CN113938115A CN 113938115 A CN113938115 A CN 113938115A CN 202111211886 A CN202111211886 A CN 202111211886A CN 113938115 A CN113938115 A CN 113938115A
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ramp
oscillator
clock
chip
frequency
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CN113938115B (en
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宋文星
韩兴成
万海军
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Suzhou Powerlink Microelectronics Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1582—Buck-boost converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention discloses a method for synchronizing clocks of a switch-mode DC-DC converter, belonging to the technical field of chip design and comprising the following steps: techniques based on synchronizing the on-chip clock-generating relaxation oscillator (relaxation oscillator) to the off-chip input clock. The invention keeps the Duty Cycle (DC) of the voltage ramp (voltage ramp) required by the on-chip clock and current control mode; and the relaxation oscillator shares one comparator, so that the area and the power consumption of a chip are saved, and the extra precision loss caused by the difference of offset voltages of the two comparators is eliminated. Compared with the traditional method which needs a phase-locked loop, the invention greatly saves the area and the power consumption of a chip and simultaneously uses the frequency programmable oscillator to keep the flexibility of synchronizing the clock frequency.

Description

Method for synchronizing clocks of switch type DC converter
Technical Field
The invention belongs to a synchronization method of a clock of a switch type direct current converter on a chip under a Pulse Width Modulation (PWM) working state, belongs to the technical field of chip design, and particularly relates to a synchronization method of an on-chip switch clock and an off-chip input clock, which saves chip area and power consumption.
Background
In some applications of the switching type dc converter, it is necessary to synchronize a switching clock of the switching type dc converter (Buck, Boost, Buck-Boost, etc.) with an off-chip input clock for the reasons of reducing electromagnetic interference, controlling noise, etc. The most straightforward, and most common, method of clock synchronization is to use a phase-locked loop circuit. The off-chip input clock is used as the reference clock of the phase-locked loop, and the output clock of the oscillator in the phase-locked loop is used as the switch control of the direct current converter. The disadvantage of this conventional approach is that the phase locked loop occupies a large chip area and consumes power. Especially when the bandwidth of the pll is small, the capacitor in the loop filter occupies a large chip area, and even additional package pins and off-chip capacitors are required. Another important drawback of using a phase-locked loop is that due to the limitations of the bandwidth of the phase-locked loop, the output oscillator clock may not keep up with the fast transitions of the reference clock if the frequency of the reference clock is modulated.
Disclosure of Invention
The present invention is directed to a clock synchronization method for a switch-mode dc converter, which saves chip area and power consumption and has no limitation of frequency conversion bandwidth, so as to solve the problems mentioned in the background art.
In order to achieve the purpose, the invention provides the following technical scheme: a method of synchronizing a clock of a switching-mode DC-DC converter, the method comprising:
by adjusting the capacitance CrampAnd CoffCharging current I offreq_tuneThe self-oscillation frequency calibration and the frequency setting of the oscillator are realized;
neglecting input offset voltage and time delay of comparator, period T of oscillatoroscThe calculation is as follows:
Figure BDA0003309179170000011
Figure BDA0003309179170000012
Figure BDA0003309179170000013
because of the capacitance CrampAnd CoffIs fixed, the output clock CK _ int of the oscillator and the ramp voltage VrampIs not changed with calibration or setting of the frequency, and has the value of the precise capacitance ratio:
Figure BDA0003309179170000021
simultaneously charging the two capacitorsrampAnd VoffArranged to share a comparator when the voltage V isrampAnd VoffIs charged to VrefWhen the comparator is started, the output of the comparator is inverted;
when the oscillator is not enabled, 4 switches controlled by input ends ph1d and ph2d of the R-S trigger are all opened, the R-S trigger is cleared by closing two enb-controlled switches, and the capacitor C is simultaneously cleared by closing the other two enb-controlled switchesrampAnd CoffDischarging;
when the pulse generator (one-shot) detects the rising edge of the off-chip input clock CK _ ext, the oscillator switch ph1 is opened, the ph2 is closed, and the capacitor C is startedoffCharging period T ofsync_off(ii) a It can be seen that the oscillator output clock has a C frequency in the synchronous and natural oscillation working modesoffIs the same, i.e.:
Tsync_off＝Tosc_off (8)
when V isoffFrom zero up to VrefWhen the voltage is higher than the low potential, the output voltage of the comparator is inverted from the low potential to the high potential; after the R-S trigger is turned over, ph2 is opened, ph1 is closed, and the capacitor C starts to be connectedrampUntil the next rising edge of the clock CK _ ext, the charging cycle of (a) is terminated temporarily, so its duration is:
Tsync_ramp＝TCK_ext-Tsync_off (9)
the capacitor C is started after the rising edge of the enable control en comesrampWhen the oscillator is in a self-oscillation mode, the two capacitors are alternately charged and discharged; otherwise, when the oscillator is in the clock synchronization mode, the capacitor CoffStart of charging (i.e. capacitor C)rampEnd of charging) is controlled by the rising edge of the off-chip input clock CK _ ext;
frequency f of an off-chip input clockCK_extWith the natural frequency f of the on-chip oscillatoroscThe relative error of (d) is noted as:
Figure BDA0003309179170000022
thus, when the on-chip oscillator and voltage ramp are synchronized with the off-chip input clock, the duty cycle is:
Figure BDA0003309179170000023
preferably, at CoffAt the end of the charging cycle, VrampMay be higher or lower than VrefDepending on whether the period of the input clock CK _ ext is longer or shorter than the period of the oscillator's natural oscillation.
Preferably, for differentiation, is VrampOr VoffGo up to VrefThe operation timing of the oscillator at the start of circuit enabling is determined by the switch control.
Preferably, the method of synchronizing the clocks of the switched mode dc converter is insensitive to frequency deviations between the off-chip input clock and the on-chip oscillator.
Compared with the prior art, the invention has the beneficial effects that:
(1) the invention does not need a phase-locked loop, thereby saving area and power consumption.
(2) The synchronized on-chip clock of the invention is aligned with the external input clock in each period. There is no limit to the pll bandwidth in the conventional approach when tracking the frequency converted external clock.
(3) The oscillator part in the invention adopts two charging and discharging capacitors with fixed values, so that the duty ratio of an output clock and a voltage ramp is fixed and does not change along with frequency calibration or frequency setting.
(4) The oscillator part in the invention shares one voltage comparator, thereby not only saving the power consumption and the area of a chip, but also eliminating the extra duty ratio error introduced by the input offset voltage of the two comparators when the two comparators are used.
(5) In the invention, when the clocks are synchronous, the time for outputting the clocks and the voltage ramp to be 'empty' is set to be fixed, namely the same as the time when the clocks are not synchronous. Therefore, the duty ratio of the output clock and the voltage ramp is not sensitive to the frequency error when the external input clock and the internal oscillator are not synchronous.
(6) The internal clock of the present invention can be set at a number of different frequencies by current programming, thereby maintaining the flexibility of synchronizing the frequency of the external clock.
Drawings
Fig. 1 is a dc booster Boost circuit diagram in current control mode;
FIG. 2 is a diagram of a conventional phase-locked loop based clock synchronization;
FIG. 3 is a circuit diagram of the oscillator and clock synchronization of the present invention;
FIG. 4 is a clock synchronization enable logic diagram of the present invention;
FIG. 5 is a timing diagram of the clock and voltage ramp synchronization of the present invention;
FIG. 6 is a timing diagram of the oscillator enable for the shared comparator of the present invention;
FIG. 7 is a graph of the relationship between the synchronous clock and voltage ramp duty cycle and the frequency error of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 shows a typical switching type dc converter, i.e. a dc Boost converter (Boost) in current control mode. The dc converter operates in two states, Pulse Width Modulation (PWM) or Pulse Frequency Modulation (PFM), depending on the magnitude of the load current. If the input and output voltages of Boost are V respectivelyinAnd VoutThen, the duty cycle of the gate driving voltage of the grounded switch (low-side switch) in the PWM operating state is:
Figure BDA0003309179170000041
thus, depending on the application, the minimum input voltage VinAnd a maximum output voltage VoutWe can calculate the maximum duty cycle:
Figure BDA0003309179170000042
in order to satisfy the stability of the current control mode Boost loop, an equivalent ramp current needs to be generated as slope compensation (slope compensation) and is superposed on the induced conduction current of the grounding switch (namely the current on the inductor L); therefore, it is necessary to generate a ramp voltage V which is synchronous with the internal clock and has the same duty ratiorampThe duty cycle requirement of the oscillator output to generate the internal clock and ramp voltage is at least as great as the value calculated in equation (2), i.e.
DCosc≥DCboost_max (3)
In some applications of the switching type dc converter, it is necessary to synchronize a switching clock of the switching type dc converter (Buck, Boost, Buck-Boost, etc.) with an off-chip input clock for the reasons of reducing electromagnetic interference, controlling noise, etc. Because the duty ratio of the input clock generally cannot satisfy the requirement of equation (3), and more importantly, another reason is that the period of the clock needs to be arbitrarily expanded in the PFM operating state, we cannot directly use the clock input from the outside of the chip as the Boost internal clock and generate the Boost internal clockVramp。
FIG. 2 shows a conventional clock synchronization method, i.e., using a phase-locked loop to synchronize an input clock with a Boost internal clock and VrampAnd (6) synchronizing. The traditional method has the disadvantages that the phase-locked loop occupies larger chip area and power consumption, and particularly when the bandwidth of the phase-locked loop is small, the capacitor in the loop filter occupies larger chip area, and even needs additional packaging pins and capacitors outside the chip; another important drawback of using a phase-locked loop is that due to the limitation of the bandwidth of the phase-locked loop, if the frequency of the reference clock is modulated, the output oscillator clock may not follow the fast transition of the reference clock, and in order to overcome the aforementioned drawbacks of the conventional method, the present invention provides a better new clock synchronization method.
Fig. 3 is a circuit diagram of the oscillator and clock synchronization circuit of the present invention. Firstly, the self-oscillation frequency calibration and frequency setting of the oscillator are realized by adjusting the capacitor CrampAnd CoffCharging current of (I)freq_tuneAnd then the operation is finished. Neglecting input offset voltage and time delay of comparator, period T of oscillatoroscThe calculation is as follows:
Figure BDA0003309179170000051
Figure BDA0003309179170000052
Figure BDA0003309179170000053
because of the capacitance CrampAnd CoffIs fixed, the output clock CK _ int of the oscillator and the ramp voltage VrampIs not changed with calibration or setting of the frequency, and has the value of the precise capacitance ratio:
Figure BDA0003309179170000054
to further save chip area and power consumption, the charging voltage, V, of the two capacitors in FIG. 3rampAnd VoffSharing one comparator. When C is presentrampAnd CoffUpper voltage (i.e. V)rampAnd Voff) Is charged to VrefWhen the comparator is started, the output of the comparator is inverted; to distinguish which voltage has risen to VrefThe operation timing of the oscillator at the start of circuit enabling is determined by the switch control.
FIG. 4 is a clock synchronization enable logic diagram of the present invention. When the oscillator is not enabled, 4 switches controlled by input ends ph1d and ph2d of the R-S trigger in the figure 3 are all opened, and the R-S trigger is cleared by closing two enb-controlled switches; at the same time, the capacitor C is switched on by closing the other two enb-controlled switchesrampAnd CoffAnd (4) discharging.
FIG. 5 is a timing diagram of the clock and voltage ramp synchronization of the present invention. When the pulse generator (one-shot) detects the rising edge of the off-chip input clock CK _ ext, the oscillator switch ph1 is opened, the ph2 is closed, and the capacitor C is startedoffCharging period of (D), Tsync_off(ii) a It can be seen that the oscillator output clock has a C frequency in the synchronous and natural oscillation working modesoffIs the same, i.e.:
Tsync_off＝Tosc_off (8)
when V isoffFrom zero up to VrefWhen the voltage is higher than the low potential, the output voltage of the comparator is inverted from the low potential to the high potential; after the R-S trigger is turned over, ph2 is opened, ph1 is closed, and the capacitor C starts to be connectedrampUntil the next rising edge of the clock CK _ ext comes to an end, so its duration is:
Tsync_ramp＝TCK_ext-Tsync_off (9)
at CoffAt the end of the charging cycle, VrampMay be slightly higher or lower than VrefDepending on whether the period of the input clock CK _ ext is longer or shorter than the period of the oscillator's natural oscillation.
Fig. 6 is a timing diagram of an enable signal of the oscillator. The capacitor C is started after the rising edge of the enable control en comesrampA charging period (i.e., a voltage ramp period); when the oscillator is in a self-oscillation mode, the two capacitors are alternately charged and discharged; and when the oscillator is in the clock synchronization mode, the capacitor CoffStart of charging (i.e. capacitor C)rampEnd of charging) is controlled by the rising edge of the off-chip input clock CK _ ext.
Frequency f of an off-chip input clockCK_extWith the natural frequency f of the on-chip oscillatoroscThe relative error of (d) is noted as:
Figure BDA0003309179170000061
thus, when the on-chip oscillator and voltage ramp are synchronized with the off-chip input clock, the duty cycle is:
Figure BDA0003309179170000062
FIG. 7 shows the fer vs. DC in equation (11)syncThe influence of (c). Here the duty cycle of the oscillator at self-oscillation DC osc80%. As can be seen from fig. 5, when the frequency error is ± 15%, the duty ratio of the synchronized internal clock and the voltage ramp changes by only ± 3% compared with the self-oscillation mode; therefore, the clock synchronization method is insensitive to the frequency deviation between the off-chip input clock and the on-chip oscillator; the clock synchronization function of the switch-type dc converter is not affected as long as the frequency of the on-chip oscillator is sufficiently programmable and can be set within an error range of ± 15% (or even larger) of the frequency of the off-chip input clock.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims (4)

1. A method of synchronizing a clock of a switching-mode DC-DC converter, the method comprising:
by adjusting the capacitance CrampAnd CoffCharging current I offreq_tuneThe self-oscillation frequency calibration and the frequency setting of the oscillator are realized;
neglecting input offset voltage and time delay of comparator, period T of oscillatoroscThe calculation is as follows:
Figure FDA0003309179160000011
Figure FDA0003309179160000012
Figure FDA0003309179160000013
because of the capacitance CrampAnd CoffIs fixed, the output clock CK _ int of the oscillator and the ramp voltage VrampIs not changed with calibration or setting of the frequency, and has the value of the precise capacitance ratio:
Figure FDA0003309179160000014
simultaneously charging the two capacitorsrampAnd VoffArranged to share a comparator when the voltage V isrampAnd VoffIs charged to VrefWhen the comparator is started, the output of the comparator is inverted;
when the oscillator is not enabled, the 4 switches controlled by the input ends ph1d and ph2d of the R-S trigger are all opened, the R-S trigger is cleared by closing the two enb-controlled switches, and the other two enb-controlled switches are closedA capacitor CrampAnd CoffDischarging;
when the pulse generator (one-shot) detects the rising edge of the off-chip input clock CK _ ext, the oscillator switch ph1 is opened, the ph2 is closed, and the capacitor C is startedoffCharging period T ofsync_off(ii) a It can be seen that the oscillator output clock has a C frequency in the synchronous and natural oscillation working modesoffIs the same, i.e.:
Tsync_off＝Tosc_off (8)
when V isoffFrom zero up to VrefWhen the voltage is higher than the low potential, the output voltage of the comparator is inverted from the low potential to the high potential; after the R-S trigger is turned over, ph2 is opened, ph1 is closed, and the capacitor C starts to be connectedrampUntil the next rising edge of the clock CK _ ext, the charging cycle of (a) is terminated temporarily, so its duration is:
Tsync_ramp＝TCK_ext-Tsync_off (9)
the capacitor C is started after the rising edge of the enable control en comesrampWhen the oscillator is in a self-oscillation mode, the two capacitors are alternately charged and discharged; otherwise, when the oscillator is in the clock synchronization mode, the capacitor CoffStart of charging (i.e. capacitor C)rampEnd of charging) is controlled by the rising edge of the off-chip input clock CK _ ext;
frequency f of an off-chip input clockCK_extWith the natural frequency f of the on-chip oscillatoroscThe relative error of (d) is noted as:
Figure FDA0003309179160000021
thus, when the on-chip oscillator and voltage ramp are synchronized with the off-chip input clock, the duty cycle is:
Figure FDA0003309179160000022
。
2. according to claim 1The method for synchronizing the clocks of the switch type DC converter is characterized in that C isoffAt the end of the charging cycle, VrampMay be higher or lower than VrefDepending on whether the period of the input clock CK _ ext is longer or shorter than the period of the oscillator's natural oscillation.
3. Method for synchronizing the clocks of a switched-mode DC converter according to claim 1, characterized in that for the purpose of distinguishing between V and VrampOr VoffGo up to VrefThe operation timing of the oscillator at the start of circuit enabling is determined by the switch control.
4. Method for synchronizing a clock of a switched mode dc-converter according to claim 1, characterized in that the method for synchronizing a clock of a switched mode dc-converter is insensitive to frequency deviations between the off-chip input clock and the on-chip oscillator.
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CN115118373A (en) * 2022-04-27 2022-09-27 广东威灵电机制造有限公司 Asynchronous serial communication method, device, controller, storage medium and household appliance
CN115333510A (en) * 2022-08-19 2022-11-11 苏州聚元微电子股份有限公司 A relaxation oscillator with a shared comparator

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Cited By (2)

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Publication number Priority date Publication date Assignee Title
CN115118373A (en) * 2022-04-27 2022-09-27 广东威灵电机制造有限公司 Asynchronous serial communication method, device, controller, storage medium and household appliance
CN115333510A (en) * 2022-08-19 2022-11-11 苏州聚元微电子股份有限公司 A relaxation oscillator with a shared comparator

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