CN112181038A

CN112181038A - Band-gap reference circuit for inhibiting ripples

Info

Publication number: CN112181038A
Application number: CN202011127076.2A
Authority: CN
Inventors: 程坤; 张际宝; 苏兆明; 阿基列什万科特
Original assignee: Datang NXP Semiconductors Co Ltd
Current assignee: Datang NXP Semiconductors Co Ltd
Priority date: 2020-10-20
Filing date: 2020-10-20
Publication date: 2021-01-05

Abstract

The invention provides a band-gap reference circuit for inhibiting ripples, and relates to the field of semiconductors. The band-gap reference circuit is a band-gap reference circuit with a chopper-stabilized amplifier, and comprises: a band gap reference unit, a low-pass filter unit and a switched capacitor notch filter unit; the band-gap reference unit is used for generating reference voltage, the reference voltage contains square ripples, and the square ripples are ripples to be inhibited; the low-pass filtering unit is used for converting the square ripple waves into triangular ripple waves; the switched capacitor notch filter unit samples and averages the midpoint position of the triangular ripple to make the output of the triangular ripple 0, thereby suppressing the ripple of the reference direct-current voltage. The band-gap reference circuit can enable the output of the triangular ripple to be 0, so that the square ripple of the reference direct-current voltage is well inhibited, a large-area capacitor and resistor are not needed in the low-pass filtering unit, and the layout area of a semiconductor is greatly reduced.

Description

Band-gap reference circuit for inhibiting ripples

Technical Field

The invention relates to the field of semiconductors, in particular to a band-gap reference circuit for inhibiting ripples.

Background

The bandgap reference circuit has the advantages of low temperature coefficient, low power supply voltage, compatibility with a CMOS (complementary metal oxide semiconductor) process and the like, and is widely applied to digital-analog conversion, analog-digital conversion, memories, switching power supplies and other digital-analog hybrid circuit systems. The stability and the anti-noise capability of the output voltage of the band-gap reference circuit are key factors influencing the precision of various application systems, and the requirements on the temperature, the voltage and the stability of the process of the band-gap reference circuit are higher and higher along with the improvement of the precision of the application systems.

At present, in order to overcome the problem of unstable output voltage of a band-gap reference circuit, the band-gap reference circuit with a chopper-stabilized amplifier is provided, and the band-gap reference circuit cancels errors caused by the offset of an input device on the output reference voltage by periodically exchanging the polarities of the input and output devices.

However, such bandgap reference circuits require chopping, the use of a chopping clock introduces ripple of a chopping frequency at an output end of the bandgap reference circuit, and due to inevitable device mismatch in a production process, under different mismatch conditions, although the average value of an output voltage improves accuracy due to mutual cancellation of a positive half cycle and a negative half cycle, different mismatches may cause ripples of different sizes.

Disclosure of Invention

In view of the above problems, the present invention provides a bandgap reference circuit capable of suppressing ripples, and the ripples are well suppressed.

The embodiment of the invention provides a band-gap reference circuit for inhibiting ripples, which is a band-gap reference circuit with a chopper-stabilized amplifier, and comprises:

a band gap reference unit, a low-pass filter unit and a switched capacitor notch filter unit;

the band-gap reference unit is connected with the low-pass filtering unit and used for generating reference voltage, the reference voltage contains square ripples, and the square ripples are ripples to be suppressed;

the low-pass filtering unit is connected with the switched capacitor notch filtering unit and is used for converting the square ripple waves into triangular ripple waves;

the switched capacitor notch filtering unit samples and averages the midpoint position of the triangular ripple to enable the output of the triangular ripple to be 0, so that the ripple of the reference voltage is suppressed;

wherein the switched capacitor notch filter unit comprises: a non-overlapping clock generating circuit and a switched capacitor notch filter circuit;

the non-overlapping clock generation circuit generates a sampling signal based on a chopping clock signal in the band-gap reference unit and outputs the sampling signal to the switched capacitor notch filter circuit;

the switched capacitor notch filter circuit samples and averages the midpoint position of the triangular ripple according to the sampling signal so as to enable the output of the triangular ripple to be 0, and therefore the ripple of the reference voltage is suppressed;

the frequency of the sampling signal is equal to the frequency of the chopping clock signal, and the phase difference is 90 degrees.

Optionally, the switched capacitor notch filter circuit comprises: the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the first capacitor, the second capacitor and the third capacitor are connected in series;

the grid electrode of the first PMOS tube is connected with the non-overlapping clock generation circuit, the source electrode of the first PMOS tube is respectively connected with the output end of the low-pass filtering unit and the source electrode of the third PMOS tube, and the drain electrode of the first PMOS tube is respectively connected with the first end of the first capacitor and the source electrode of the second PMOS tube;

the grid electrode of the second PMOS tube is connected with the non-overlapping clock generation circuit, and the drain electrode of the second PMOS tube is respectively connected with the first end of the third capacitor and the drain electrode of the fourth PMOS tube;

the grid electrode of the third PMOS tube is connected with the non-overlapping clock generation circuit, and the drain electrode of the third PMOS tube is respectively connected with the first end of the second capacitor and the source electrode of the fourth PMOS tube;

the grid electrode of the fourth PMOS tube is connected with the non-overlapping clock generation circuit;

the second end of the first capacitor, the second end of the second capacitor and the second end of the third capacitor are all grounded;

and the drain electrode of the second PMOS tube and the drain electrode of the fourth PMOS tube are both output ends of the band-gap reference circuit.

Optionally, the non-overlap clock generating circuit includes: the logic circuit consists of an OR gate, a NOT gate and a NAND gate;

the first input end of the OR gate takes the chopped wave clock signal after 90-degree phase shift as an input signal, and the output signal of the output end of the NOT gate is the input signal of the second input end of the OR gate;

the output signal of the output end of the OR gate is a first sampling signal in the sampling signals, and meanwhile, the first sampling signal is an input signal of the first input end of the NAND gate;

the second input end of the NAND gate takes the chopped wave clock signal phase-shifted by 90 degrees as an input signal;

the output signal of the output end of the NAND gate is a second sampling signal in the sampling signals;

and the input end of the NOT gate takes the second sampling signal as an input signal.

Optionally, the chopping clock signal comprises: a first chopping clock signal and a second chopping clock signal;

the frequency of the first chopping clock signal is the same as that of the first sampling signal, and the phase difference is 90 degrees;

the frequency of the second chopping clock signal is the same as that of the second sampling signal, and the phase difference is 90 degrees;

the first chopping clock signal and the second chopping clock signal are signals with opposite high and low levels;

the first sampling signal and the second sampling signal are signals with opposite high and low levels.

Optionally, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor have the same size, parameter, and shape.

Optionally, the capacitance values of the first capacitor and the second capacitor are equal.

Optionally, when the first sampling signal is a low-level signal, the second sampling signal is a high level, and at this time, the first PMOS transistor and the fourth PMOS transistor are turned on;

when the second sampling signal is a low level signal, the first sampling signal is a high level signal, and at the moment, the second PMOS tube and the third PMOS tube are conducted.

Optionally, when the first PMOS transistor and the fourth PMOS transistor are turned on, a first voltage output by an output end of the low-pass filtering unit is sampled and stored in the first capacitor;

when the second PMOS tube and the third PMOS tube are conducted, a second voltage output by the output end of the low-pass filtering unit is sampled and stored in the second capacitor, and meanwhile, the charge stored in the first capacitor charges or discharges the third capacitor through the second PMOS tube.

Optionally, when a second voltage output by the output end of the low-pass filtering unit is sampled and stored in the second capacitor, and the first PMOS transistor and the fourth PMOS transistor are turned on, the third capacitor is charged or discharged by the charge stored in the second capacitor through the fourth PMOS transistor.

Optionally, if the first voltage and the second voltage are equal in size, the output of the triangular ripple on the third capacitor is 0, that is, the output of the triangular ripple is made to be 0, so as to suppress the ripple of the reference voltage;

if the first voltage and the second voltage are not equal in magnitude, the voltage of the triangular ripple on the third capacitor depends on the voltage difference between the first voltage and the second voltage and the ratio of the capacitance values of the first capacitor, the second capacitor and the third capacitor.

The invention provides a band-gap reference circuit for inhibiting ripples, which generates reference direct-current voltage by a band-gap reference unit with a chopper-stabilized amplifier, since the reference dc voltage contains square ripple, the square ripple is first converted into triangular ripple by the low pass filter unit, because the midpoint voltage values of the rising period and the falling period of the triangular ripple are equal, by utilizing the fact that the frequency of the sampling signal is equal to the frequency of the chopping clock signal and the phase difference is 90 degrees, the non-overlapping clock generating circuit generates the sampling signal and outputs the sampling signal to the switched capacitor notch filter circuit, and the switched capacitor notch filter circuit can obtain the voltage difference value according to the sampling signal, the sampling and averaging processing is carried out on the midpoint position of the triangular ripple, so that the output of the triangular ripple contained in the reference voltage is 0, and the square ripple of the reference voltage is well inhibited. And because the switched capacitor notch filter unit is introduced, the low-pass filter unit does not need a larger capacitance and resistance product, namely, the low-pass filter unit does not need a larger-area capacitance and resistance, and compared with a band-gap reference circuit which realizes the same ripple rejection ratio effect and does not comprise the switched capacitor notch filter unit, the band-gap reference circuit greatly reduces the layout area of a semiconductor.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

FIG. 1 is a schematic diagram of a current bandgap reference circuit with a low pass filter;

FIG. 2 is a waveform diagram of a current bandgap reference circuit with a low pass filter;

FIG. 3 is a schematic diagram of a ripple-suppressed bandgap reference circuit according to an embodiment of the present invention;

FIG. 4 is a waveform diagram of a triangular ripple in an embodiment of the present invention;

FIG. 5 is a schematic diagram of a preferred configuration of a switched capacitor notch filter circuit in an embodiment of the present invention;

FIG. 6 is a schematic diagram of a preferred structure of a non-overlap clock generation circuit according to an embodiment of the present invention;

FIG. 7 is a high-low state diagram of the chopping clock signal, the first sampling signal and the second sampling signal according to the embodiment of the present invention;

fig. 8 shows input waveforms and output waveforms of the switched capacitor notch filter unit 3 obtained by a set of practical simulation experiments in the embodiment of the present invention;

fig. 9 is a waveform diagram of the embodiment of the present invention, which is implemented by using only a low-pass filtering unit, and takes the chopping frequency of 62.5Khz as an example, and a ripple rejection ratio of 40dB (100 times) needs to be obtained;

fig. 10 is a waveform diagram of a ripple suppression ratio of 40dB (100 times) that is required to be obtained by taking a chopping frequency of 62.5Khz as an example, and the ripple suppression bandgap reference circuit according to the present invention is used for realizing the waveform diagram;

FIG. 11 is a schematic diagram of the layout area of a bandgap reference circuit employing a low pass filter unit alone;

fig. 12 is a schematic layout area diagram of a bandgap reference circuit with ripple suppression according to an embodiment of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention, but do not limit the invention to only some, but not all embodiments.

The inventor finds that, at present, due to unavoidable device mismatch in the manufacturing process, although the average value of the output voltage improves the accuracy due to mutual cancellation of the positive half cycle and the negative half cycle under different mismatch conditions, different mismatches may cause ripples of different sizes, that is, the final output voltage of the bandgap reference circuit may contain a dc voltage and an ac voltage, and this ac voltage is a square ripple having a peak value of several millivolts to several tens millivolts, which is a problem that cannot be ignored for semiconductors requiring precise reference voltages, and therefore this square ripple needs to be suppressed, and only the dc voltage is finally output.

The inventor further researches and discovers that the current solution to the above problem is to add a low-pass filter after the bandgap reference circuit to achieve the suppression of square ripple.

Referring to fig. 1, there is shown a schematic diagram of a current bandgap reference circuit with a low pass filter, where Vbg represents the output voltage of the bandgap reference circuit, which includes: the dc voltage and the square ripple (the square ripple is ac voltage and needs to be suppressed), the resistor R1 and the capacitor C4 together form a low-pass filter, and Vc is the dc voltage after the ripple is suppressed by the low-pass filter. The dotted box 1 represents the currently existing bandgap reference circuit.

In general, during the high level duration of the square ripple, the voltage Vc across the capacitor C1 will increase slowly, and if the product of the resistor R1 and the capacitor C4 is large enough, the high level state will disappear when Vc has not reached the steady state value, and will become the low level state in the second half period, at which time the capacitor C4 will discharge slowly and Vc will begin to decay slowly. Therefore, the increase and the decay of Vc change exponentially, but when the product of the resistor R1 and the capacitor C4 is large enough, the change curve is still in the initial stage of the exponential curve, which can be approximated to a straight line, so that the ripple waveform of the output voltage changes from square ripple to triangular ripple.

Specific waveform diagrams can be seen in fig. 2, and the theory can be reflected more intuitively. T/2 represents a half cycle, Vbg is a square ripple contained in the output voltage of the band-gap reference circuit, when the Vbg is in a high level state, Vc will slowly increase, if the product of a resistor R1 and a capacitor C4 is large enough, Vc can not reach a steady state value, the high level state of the Vbg already disappears, the Vbg becomes a low level state of the second half cycle, at this time, a capacitor C4 will slowly discharge, and Vc begins to slowly decay. Therefore, the increase and the decay of Vc change according to an exponential law, and the waveform of the output voltage changes from a square ripple to a triangular ripple.

However, the above theory has a problem that if the frequency of the chopper clock is at a low frequency, in order to ensure that the effect that the triangular ripple is similar to a straight line is achieved, the product of the resistor R1 and the capacitor C4 in the low-pass filter needs to be larger than that of a high frequency, and the product of the larger resistor R1 and the capacitor C4 needs to select a larger-area resistor and capacitor, which causes an excessively large layout area of the bandgap reference circuit, which obviously cannot meet the current trend of miniaturization of semiconductor devices.

In order to overcome the above problems, the inventors have conducted extensive research, simulation and practical tests to inventively provide the ripple-suppressed bandgap reference circuit of the present invention, and the following describes the technical solution of the present invention in detail.

Referring to fig. 3, a schematic diagram of a bandgap reference circuit for suppressing ripple according to an embodiment of the present invention is shown, the bandgap reference circuit including: a band gap reference unit 1, a low pass filter unit 2, and a switched capacitor notch filter unit 3; the bandgap reference unit 1 is a currently existing bandgap reference circuit with a chopper-stabilized amplifier, and its chopper clock signal includes: the first chopping clock signal and the second chopping clock signal are represented by Chop clkD and Chop clkB, respectively, and are signals having the same frequency and opposite high and low levels. The bandgap reference cell 1 generates a reference voltage comprising: the dc voltage and the square ripple are directly input to the low pass filter unit 2.

The low-pass filtering unit 2 includes: the resistor R1 and the capacitor C4, of course, the low-pass filtering unit 2 may be formed by any other components known at present for implementing the low-pass filtering function. The output voltage containing the square ripple is converted into the output voltage containing the triangular ripple after passing through the low pass filter unit 2. The output voltage containing the triangular ripple is used as the input of the switched capacitor notch filter unit 3.

For the triangular ripple, it is characterized in that the midpoint voltage values of the rising period and the falling period thereof are equal. For example, as shown in fig. 4 (T/4 in fig. 4 represents a quarter cycle), the midpoint voltage value V1 of the triangular ripple rising period is equal to the midpoint voltage value V2 of the triangular ripple falling period, i.e., the voltage value V1 at the time T1 is equal to the voltage value V2 at the time T2. Based on this idea, the switched capacitor notch filter unit 3 samples the voltage values of the triangular ripples at the time t1 and the time t2, respectively, so that the triangular ripple output in the final output voltage of the switched capacitor notch filter unit 3 is 0, thereby achieving the goal of suppressing the ripples.

One preferred structure of the switched capacitor notch filter circuit in switched capacitor notch filter unit 3 can be seen with reference to fig. 5, which includes: the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, the fourth PMOS transistor P4, the first capacitor C1, the second capacitor C2 and the third capacitor C3. The gate of the first PMOS transistor P1 is connected to the non-overlap clock generating circuit, and the first sampling signal NF _ clkB generated by the non-overlap clock generating circuit is used as a control signal for the gate, and the non-overlap clock generating circuit is described in detail in the corresponding place below, which is not described herein again.

The source of the first PMOS transistor P1 is connected to the output terminal (IN fig. 5) of the low-pass filter unit 2 and the source of the third PMOS transistor P3, i.e., a dc voltage with triangular ripples is input to the source of the first PMOS transistor P1 and the source of the third PMOS transistor P3, and the drain of the first PMOS transistor P1 is connected to the first end of the first capacitor C1 and the source of the second PMOS transistor P2.

The grid electrode of the second PMOS pipe P2 is connected with the non-overlapping clock generation circuit, and a second sampling signal NF _ clkD generated by the non-overlapping clock generation circuit is used as a control signal of the grid electrode; the drain of the second PMOS transistor P2 is connected to the first end of the third capacitor C3 and the drain of the fourth PMOS transistor P4, respectively.

The grid electrode of the third PMOS pipe P3 is connected with the non-overlapping clock generation circuit, and the second sampling signal NF _ clkD generated by the non-overlapping clock generation circuit is used as a control signal of the grid electrode; the drain of the third PMOS transistor P3 is connected to the first end of the second capacitor C2 and the source of the fourth PMOS transistor P4, respectively.

The grid electrode of the fourth PMOS pipe P4 is connected with the non-overlapping clock generating circuit, and a first sampling signal NF _ clkB generated by the non-overlapping clock generating circuit is used as a control signal of the grid electrode; the drain of the second PMOS transistor P2 and the drain of the fourth PMOS transistor P4 are output terminals (OUT in fig. 5) of the bandgap reference circuit, and the output terminals finally output the dc voltage Vref with ripple suppressed.

The second terminal of the first capacitor C1, the second terminal of the second capacitor C2, and the second terminal of the third capacitor C3 are all grounded.

In order to ensure that the switched capacitor notch filter circuit suppresses ripples, the sizes, parameters and shapes of the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3 and the fourth PMOS transistor P4 are all the same, and the capacitance values of the first capacitor C1 and the second capacitor C2 are equal.

Referring to fig. 6, a schematic diagram of a preferred structure of a non-overlap clock generation circuit in an embodiment of the present invention is shown, where the non-overlap clock generation circuit includes: an or gate 601, a not gate 602, and a nand gate 603; the first input end of the or gate 601 uses the chopped clock signals Chop clkD and Chop clkB phase-shifted by 90 degrees as input signals, so that the phase of the chopped clock signals needs to be shifted by 90 degrees, which is to ensure that the sampling time of the first sampling signal NF _ clkB and the second sampling signal NF _ clkD generated by the non-overlapping clock generation circuit falls at the midpoint of the triangular ripple, and simultaneously avoid the overlapping of sampling and the overlapping of holding periods. A high-low state diagram of the chopped clock signals Chop clkD and Chop clkB, and the first and second sampling signals NF _ clkB and NF _ clkB may be seen in fig. 7.

Since the frequency of the first chopping clock signal Chop clkB is the same as the frequency of the first sampling signal NF _ clkB, the phase differs by 90 degrees; the frequency of the second chopping clock signal Chop clkD is the same as that of the second sampling signal NF _ clkD, the phase difference is 90 degrees, and the first chopping clock signal Chop clkB and the second chopping clock signal Chop clkD are signals with opposite high and low levels; the first and second sampling signals NF _ clkB and NF _ clkD are also opposite signals.

The output signal of the output terminal of the not gate 602 is the input signal of the second input terminal of the or gate 601; an output signal of the output end of the or gate 601 is a second sampling signal NF _ clkD in the sampling signals, and the second sampling signal NF _ clkD is an input signal of the first input end of the nand gate 603; the second input end of the nand gate 603 also takes the chopped wave clock signal phase-shifted by 90 degrees as an input signal; the output signal of the output end of the nand gate 603 is a first sampling signal NF _ clkB in the sampling signals; the input of the not-gate 602 takes the first sampling signal NF _ clkB as an input signal.

Since the second sampling signal NF _ clkD is at a high level when the first sampling signal NF _ clkB is at a low level, the first PMOS transistor P1 and the fourth PMOS transistor P4 are turned on, and the second PMOS transistor P2 and the third PMOS transistor P3 are turned off, so that the first voltage (i.e. the midpoint voltage value of the rising period of the triangular ripple) output by the output terminal of the low-pass filter unit 2 is sampled and stored in the first capacitor C1, and in conjunction with fig. 4, assuming that at time t1, the first PMOS transistor P1 and the fourth PMOS transistor P4 are turned on, and the first voltage V1 output by the output terminal of the low-pass filter unit 2 is sampled and stored in the first capacitor C1.

Then, when the second sampling signal NF _ clkD is a low level signal, the first sampling signal NF _ clkB is at a high level, and at this time, the second PMOS transistor P2 and the third PMOS transistor P3 are turned on, and the first PMOS transistor P1 and the fourth PMOS transistor P4 are turned off, so that the second voltage (i.e., the midpoint voltage value of the falling period of the triangular ripple) output by the output terminal of the low-pass filtering unit 2 is sampled and stored in the second capacitor C2, and at the time t2 in conjunction with fig. 4, the second PMOS transistor P2 and the third PMOS transistor P3 are turned on, the second voltage V2 output by the output terminal of the low-pass filtering unit 2 is sampled and stored in the second capacitor C2, and at the same time, since the second PMOS transistor P2 is turned on, the charge stored in the first capacitor C1 at the time t1 charges or discharges the third capacitor C3 through the turned on second PMOS transistor P2. Assuming that the first voltage V1 and the second voltage V2 are completely equal, the output voltage of the triangular ripple on the third capacitor C3 is finally 0, so that the output of the triangular ripple is 0, i.e. there is no ripple, and the purpose of suppressing the ripple of the reference voltage is achieved.

If the first voltage V1 and the second voltage V2 are not equal, the voltage of the triangular ripple on the third capacitor C3 depends on the voltage difference between the first voltage V1 and the second voltage V2 and the ratio of the capacitance values of the first capacitor C1, the second capacitor C2, and the third capacitor C3.

In the same principle as described above, when the second voltage V2 output from the output terminal of the low pass filter unit 2 is sampled and stored in the second capacitor C2, and the first PMOS transistor P1 and the fourth PMOS transistor P4 are turned on, the charge stored in the second capacitor C2 at time t2 charges or discharges the third capacitor C3 through the fourth PMOS transistor P4 turned on at this time. Since the magnitude of the midpoint voltage value of the rising period of the triangular ripple and the magnitude of the midpoint voltage value of the falling period thereof are equal, the ripple can be finally suppressed, and the dc voltage Vref with the ripple suppressed is output.

Referring to fig. 8, an input waveform and an output waveform of the switched capacitor notch filter unit 3 obtained by a set of practical simulation experiments in the embodiment of the present invention are shown, where the abscissa represents time in us, and the ordinate represents a voltage value in V; the lower solid line NF _ clk in fig. 8 is a sampling signal; the waveform formed by the upper broken line IN fig. 8 is an input waveform (IN fig. 8), i.e., a waveform including a triangular ripple; the waveform formed by the solid line at the upper part in fig. 8 is the output waveform (OUT in fig. 8), i.e. Vref which is finally output, and therefore, the ripple-suppressed bandgap reference circuit of the embodiment of the invention can effectively suppress the ripple. It should be noted that the Vref output in fig. 8 is not a complete dc waveform, but a square wave with a very small peak-to-peak value (shown by a hollow circle in fig. 8), because the input waveform (waveform including triangular ripple) is not an ideal triangular wave, and the midpoint values of the rising edge and the falling edge are not equal, so that the product value of the resistance and the capacitance of the low-pass filter can be increased appropriately to make the input waveform reach the reference voltage containing the ideal triangular wave.

According to the invention, the switched capacitor notch filtering unit 3 is added behind the low-pass filtering unit 2, and the switched capacitor notch filtering unit 3 is used for sampling and averaging the midpoint position of the triangular ripple, so that even under the condition of low chopping frequency, the low-pass filtering unit 2 does not need to have a larger product of a resistor and a capacitor, and does not need to select a resistor and a capacitor with larger areas naturally, and only needs to select a smaller PMOS tube and a smaller capacitor which are needed by the switched capacitor notch filtering unit 3, so that the layout area of the whole ripple-restraining band gap reference circuit is greatly reduced.

In summary, in the bandgap reference circuit for suppressing the ripple according to the embodiment of the present invention, the low-pass filtering unit converts the square ripple contained in the reference voltage into the triangular ripple, and since the midpoint voltage values of the rising period and the falling period of the triangular ripple are equal, the non-overlapping clock generating circuit generates the sampling signal by using the frequency of the sampling signal and the frequency of the chopping clock signal and the phase difference is 90 degrees and outputs the sampling signal to the switched capacitor notch filtering circuit, and the switched capacitor notch filtering circuit can perform sampling and averaging processing on the midpoint position of the triangular ripple according to the sampling signal, so that the output of the triangular ripple contained in the reference voltage is 0, thereby well suppressing the square ripple of the reference voltage. And because the switched capacitor notch filter unit is introduced, the low-pass filter unit does not need a larger capacitance and resistance product, namely, the low-pass filter unit does not need a larger-area capacitance and resistance, and compared with a band-gap reference circuit which realizes the same ripple rejection ratio effect and does not comprise the switched capacitor notch filter unit, the band-gap reference circuit greatly reduces the layout area of a semiconductor. In addition, the whole band gap reference circuit has fewer added components, lower cost, strong compatibility, high operation reliability and higher practicability.

To further prove the practicability and the final effect of the present invention, the inventor assumes that a ripple rejection ratio of 40dB (100 times) needs to be obtained by taking a chopping frequency of 62.5Khz as an example, and if only a low-pass filter unit is used, the low-pass filter unit actually needs a resistance of 1M Ω and a capacitance of 400 pF. The final waveform is shown in fig. 9, the abscissa represents time in us, and the ordinate represents voltage in V; the upper solid line in fig. 9 is the reference dc voltage (v/BG in fig. 9) containing square ripples, and the lower solid line in fig. 9 is the output voltage (v/Vc in fig. 9) of the low-pass filter unit containing triangular ripples.

Under the same condition, if the bandgap reference circuit for suppressing the ripple is adopted, the square ripple (BG) is converted into the triangular ripple (Vc2) only by a resistor of 1M Ω and a capacitor of 3pF, and then a switched capacitor notch filter unit (only a capacitor of 20pF is needed) is added to realize the ripple suppression ratio of the same degree. The final waveform is shown in fig. 10, the abscissa represents time in us, and the ordinate represents voltage in V; the upper solid line in fig. 10 is the reference dc voltage (v/BG in fig. 10) containing square ripples, the middle solid line in fig. 10 is the output voltage of the low-pass filter unit (v/Vc 2 in fig. 10) containing triangular ripples, and the lower solid line in fig. 10 is one sampling signal (v/NF in fig. 10).

The band-gap reference circuit for inhibiting the ripple waves has the layout area which is only one tenth of that of a single low-pass filtering unit; for example, as shown in FIG. 11: the area of the layout occupied by the resistor and the capacitor when only the low-pass filter unit is used is 250um to 175um (the process condition is 140nm, the capacitor uses an N well and polysilicon as an upper polar plate and a lower polar plate, and the capacitance value of the unit area is about 0.1pF/100um 2); FIG. 12 is a layout occupied by the low-pass filter unit and the switched capacitor notch filter unit according to the embodiment of the present invention, and the area of the layout is 42um 145um (process condition: 140nm process, capacitor using N-well and polysilicon as upper and lower plates, unit area capacitance value is about 0.1pF/100um 2); therefore, the layout area of the band-gap reference circuit for inhibiting the ripple is greatly reduced, and an effective solution is provided for miniaturization of semiconductors.

While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.

While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A bandgap reference circuit with ripple rejection, wherein the bandgap reference circuit is a bandgap reference circuit with chopper-stabilized amplifier, and wherein the bandgap reference circuit comprises:

2. The bandgap reference circuit of claim 1, wherein the switched capacitor notch filter circuit comprises: the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the first capacitor, the second capacitor and the third capacitor are connected in series;

3. The bandgap reference circuit of claim 1, wherein the non-overlap clock generating circuit comprises: an OR gate, a NOT gate, and a NAND gate;

the output signal of the output end of the OR gate is a second sampling signal in the sampling signals, and meanwhile, the second sampling signal is an input signal of the first input end of the NAND gate;

the output signal of the output end of the NAND gate is a first sampling signal in the sampling signals;

the input end of the NOT gate takes the first sampling signal as an input signal.

4. The bandgap reference circuit of claim 3, wherein the chopped clock signal comprises: a first chopping clock signal and a second chopping clock signal;

5. The bandgap reference circuit of claim 2, wherein the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are identical in size, parameter, and shape.

6. The bandgap reference circuit of claim 2, wherein the capacitance values of the first and second capacitors are equal.

7. The bandgap reference circuit of claim 4, wherein when the first sampling signal is a low level signal, the second sampling signal is a high level signal, and the first PMOS transistor and the fourth PMOS transistor are turned on;

8. The bandgap reference circuit according to claim 7, wherein when the first PMOS transistor and the fourth PMOS transistor are turned on, a first voltage output from the output terminal of the low-pass filtering unit is sampled and stored in the first capacitor, and the first voltage is a midpoint voltage value of a rising period of the triangular ripple;

when the second PMOS tube and the third PMOS tube are conducted, a second voltage output by the output end of the low-pass filtering unit is sampled and stored in the second capacitor, meanwhile, the third capacitor is charged or discharged by the charges stored in the first capacitor through the second PMOS tube, and the second voltage is a midpoint voltage value of the triangular ripple reduction period.

9. The bandgap reference circuit of claim 8, wherein when a second voltage outputted from the output terminal of the low pass filtering unit is sampled and stored in the second capacitor, and the first PMOS transistor and the fourth PMOS transistor are turned on, the third capacitor is charged or discharged by the charge stored in the second capacitor through the fourth PMOS transistor.

10. The bandgap reference circuit according to claim 9, wherein if the first voltage and the second voltage are equal in magnitude, the output of the triangular ripple on the third capacitor is 0, that is, the output of the triangular ripple is 0, so as to suppress the ripple of the reference voltage;