CN114815947A - Band gap reference circuit - Google Patents
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- CN114815947A CN114815947A CN202110114864.6A CN202110114864A CN114815947A CN 114815947 A CN114815947 A CN 114815947A CN 202110114864 A CN202110114864 A CN 202110114864A CN 114815947 A CN114815947 A CN 114815947A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
Abstract
The invention provides a band gap reference circuit, which comprises a first MOS tube, a second MOS tube, a first triode, a second triode, a first switched capacitor network, a second switched capacitor network and an operational amplifier, wherein: the source electrodes of the first MOS tube and the second MOS tube are connected with an input power supply, and the grid electrodes of the first MOS tube and the second MOS tube are interconnected and are connected with the drain electrode of the first MOS tube; the emitting electrode of the first triode is connected with the drain electrode of the first MOS tube, and the emitting electrode of the second triode is connected with the drain electrode of the second MOS tube; the emitter of the first triode and the emitter of the second triode are both connected with the first switched capacitor network and the second switched capacitor network; the first switched capacitor network is connected with the second switched capacitor network through the operational amplifier, and the second switched capacitor network outputs band-gap reference voltage. The invention improves the precision of the band-gap reference circuit and improves the temperature coefficient.
Description
Technical Field
The invention belongs to the field of integrated circuits, and particularly relates to a band-gap reference circuit.
Background
Voltage reference circuits are fundamental modules of analog, mixed-signal, and even digital circuits. The reference circuit is an essential part for bias circuits, data conversion circuits and even almost most electronic systems. It is most typically characterized by providing a voltage that is insensitive to temperature and supply voltage variations, has good temperature stability, and has high supply rejection.
The existing typical bandgap reference circuit needs to realize the function of reference voltage output by using a resistor. The realization of low power consumption requires that the current in the circuit is as small as possible, which makes the resistance value of the resistor in the reference circuit usually larger. The large resistance resistor is not beneficial to reducing the circuit area. In addition, in a standard CMOS manufacturing process, a typical value of the resistance matching accuracy is 0.4%, and a typical value of the absolute value error of the resistance is 20%, and the error of the resistance further causes an error of the reference voltage.
Disclosure of Invention
Technical problem to be solved
In view of the above-mentioned shortcomings of the prior art, the present invention provides a bandgap reference circuit, which improves the accuracy of the bandgap reference circuit and improves the temperature coefficient.
(II) technical scheme
The invention provides a band gap reference circuit, which comprises a first MOS tube M1, a second MOS tube M2, a first triode Q1, a second triode Q2, a first switched capacitor network SCN1, a second switched capacitor network SCN2 and an operational amplifier A, wherein: the sources of the first MOS transistor M1 and the second MOS transistor M2 are both connected with an input power supply, and the gates of the first MOS transistor M1 and the second MOS transistor M2 are interconnected and are both connected with the drain of the first MOS transistor M1; an emitter electrode of the first triode Q1 is connected with a drain electrode of the first MOS tube M1, and an emitter electrode of the second triode Q2 is connected with a drain electrode of the second MOS tube M2; an emitter of the first triode Q1 and an emitter of the second triode Q2 are both connected to a first switched capacitor network SCN1 and a second switched capacitor network SCN 2; the first switched capacitor network SCN1 is connected to the second switched capacitor network SCN2 through an operational amplifier a, and the second switched capacitor network SCN2 outputs a bandgap reference voltage.
Optionally, the operational amplifier a is an amplifier with unity gain negative feedback.
Optionally, the first switched capacitor network SCN1 is connected to the positive input of the operational amplifier a, and the negative input and output of the operational amplifier a are connected to the second switched capacitor network SCN 2.
Optionally, the base and collector of the first transistor Q1 and the second transistor Q2 are both grounded.
Optionally, the first MOS transistor M1 and the second MOS transistor M2 have the same size.
Optionally, the second transistor Q2 is composed of a plurality of transistors connected in parallel with each other and having the same size as the first transistor Q1.
Optionally, the first switched capacitor network SCN1 is formed by a first capacitor C 1，1 A second capacitor C 2，1 A third capacitor C 3，1 A fourth capacitor C 4，1 A first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, and a sixth switch S6, wherein: the input end of the first switched capacitor network SCN1 is connected with a first input contact V BE1 A second input contact V BE2 And a third input contact GND, the output terminal is a first output contact V ref，1 Said first input contact V BE1 Has two; the first input contact V BE1 Is connected to the first capacitor C via a second switch S2 1，1 Said second input contact V BE2 Is connected to the second capacitor C through a first switch S1 2，1 The first terminal of, the second capacitor C 2，1 Is connected to the first capacitor C 1，1 Said second input contact V BE2 Is also connected to the first capacitance C through a third switch S3 1，1 A second end of (a); the second capacitor C 2，1 Is further connected to the third input contact GND via a fourth switch S4, and the third capacitor C 3，1 First end of the first switch is connected to the third input contactGND, the second capacitance C 2，1 Is further connected to said third capacitor C via a fifth switch S5 3，1 The second terminal of (C), the third capacitor C 3，1 Is connected to the fourth capacitor C 4，1 The first terminal of (C), the first capacitor C 1，1 Is connected to the fourth capacitor C via a sixth switch S6 4，1 The second end of (a).
Optionally, the first input contact V BE1 Are connected to the emitter of the first triode Q1, and the second input contact V BE2 The emitter of the second triode Q2 is connected, the third input joint GND is grounded, and the first output joint V is connected ref，1 Connecting the third capacitor C 3，1 Said first input contact V BE1 Another of which is connected to the fourth capacitance C 4，1 The second end of (a).
Optionally, the second switched capacitor network SCN2 includes 6 switches and 4 capacitors, the circuit structure of the 6 switches and the circuit structure of the 4 capacitors are the same as that of the first switched capacitor network SCN1, and the input terminal of the second switched capacitor network SCN2 is connected to the fourth input node V BE1 The fifth input contact V BE2 And a sixth input contact V TEMP_COMP The output end is a second output contact V ref Said fourth input contact V BE1 Has two, wherein: the fourth input contact V BE1 Are connected to the emitter of the first triode Q1, and the fifth input contact V BE2 The emitter of the second triode Q2 is connected, and the sixth input contact V TEMP_COMP The output end of the operational amplifier A is accessed, and the second output joint V ref For outputting a bandgap reference voltage.
Optionally, all switches in the first switched capacitor network SCN1 and the second switched capacitor network SCN2 are identical in structure and size.
(III) advantageous effects
The invention provides a band-gap reference circuit, which utilizes a switched capacitor circuit to realize the output of band-gap reference voltage, and can improve the precision of reference voltage generated by the band-gap circuit because the absolute value precision and matching precision of the switched capacitor are greatly improved compared with that of a resistor. In addition, the invention adopts a mode of mutual compensation of two reference voltages, improves the temperature characteristic and reduces the temperature coefficient of the band-gap reference circuit.
Drawings
Fig. 1 schematically shows a circuit configuration diagram of a bandgap reference circuit of an embodiment of the present invention.
Fig. 2A and 2B schematically show circuit configuration diagrams of the first switched capacitor network and the second switched capacitor network, respectively, according to an embodiment of the present invention.
[ description of reference ]
M1-first MOS tube; m2-second MOS tube; q1-first triode; q2-second transistor; SCN1 — first switched capacitor network; SCN 2-second switched capacitor network; a-an operational amplifier; v ref -a bandgap reference voltage; c 1，1 -a first capacitance; c 2，1 -a second capacitance; c 3，1 -a third capacitance; c 4，1 -a fourth capacitance; s1 — a first switch; s2 — a second switch; s3 — a third switch; s4-a fourth switch; s5-a fifth switch; s6-a sixth switch; v BE1 -a first input contact; v BE2 -a second input contact; GND-third input contact; v ref，1 -a first output contact; c 1，2 -a fifth capacitance; c 2，2 -a sixth capacitance; c 3，2 -a seventh capacitance; c 4，2 -an eighth capacitance; s7-seventh switch; s8-eighth switch; s9-ninth switch; s10-tenth switch; s11-eleventh switch; s12-sixth switch; v BE1 -a fourth input contact; v BE2 -a fifth input contact; v TEMP_COMP -a sixth input contact; v ref -a third output contact; SCN1 — first switched capacitor network; SCN 2-second switched capacitor network.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a band gap reference circuit, which utilizes a switched capacitor circuit to realize the output of band gap reference voltage and utilizes two switched capacitor networks to complete the temperature compensation of the band gap reference voltage.
Fig. 1 schematically shows a circuit configuration diagram of a bandgap reference circuit of an embodiment of the present invention.
As shown in fig. 1, the bandgap reference circuit may include: the circuit comprises a first MOS tube M1, a second MOS tube M2, a first triode Q1, a second triode Q2, a first switched capacitor network SCN1, a second switched capacitor network SCN2 and an operational amplifier A.
The sources of the first MOS transistor M1 and the second MOS transistor M2 are both connected to the input power supply, and the gates of the first MOS transistor M1 and the second MOS transistor M2 are interconnected and both connected to the drain of the first MOS transistor M1. The emitter of the first triode Q1 is connected with the drain of the first MOS tube M1, and the emitter of the second triode Q2 is connected with the drain of the second MOS tube M2.
The emitter of the first transistor Q1 and the emitter of the second transistor Q2 are both connected to a first switched capacitor network SCN1 and a second switched capacitor network SCN 2. The first switched capacitor network SCN1 is connected to the second switched capacitor network SCN2 through operational amplifier a, and the second switched capacitor network SCN2 outputs a bandgap reference voltage.
Further, the first switched capacitor network SCN1 is connected to the positive input terminal of the operational amplifier a, and the negative input terminal and the output terminal of the operational amplifier a are connected to the second switched capacitor network SCN 2.
In the embodiment of the invention, the operational amplifier A is an amplifier with unity gain negative feedback.
As shown in fig. 1, the base and collector of the first transistor Q1 and the second transistor Q2 are both grounded.
In the embodiment of the invention, the first MOS transistor M1 and the second MOS transistor M2 have the same size.
In the embodiment of the invention, the second triode Q2 is composed of a plurality of triodes which are connected in parallel and have the same size as the first triode Q1.
Fig. 2A and 2B schematically show circuit configuration diagrams of the first switched capacitor network and the second switched capacitor network, respectively, according to an embodiment of the present invention.
For convenience of description, referring to the drawings, in the embodiments of the present invention, the upper ends of all the capacitance elements are collectively set as the first ends, and correspondingly, the lower ends of all the capacitance elements are set as the second ends.
As shown in FIG. 2A, the first switched capacitor network SCN1 is formed by a first capacitor C 1，1 A second capacitor C 2，1 A third capacitor C 3，1 A fourth capacitor C 4，1 The switch comprises a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5 and a sixth switch S6.
Wherein the input terminal of the first switched capacitor network SCN1 is connected to the first input node V BE1 A second input contact V BE2 And a third input contact GND, the output terminal is a first output contact V ref，1 。
First input contact V BE1 Has two first input contacts V BE1 Is connected to the first capacitor C via a second switch S2 1，1 First end of (2), second input contact V BE2 Is connected to the second capacitor C through the first switch S1 2，1 A first terminal of a second capacitor C 2，1 Is connected with the first capacitor C 1，1 First end of (2), second input contact V BE2 Is also connected to the first capacitor C through a third switch S3 1，1 The second end of (a).
Second capacitor C 2，1 Is further connected to a third input contact GND and a third capacitor C via a fourth switch S4 3，1 A first end of the first capacitor is connected to a third input contact GND and a second capacitor C 2，1 Is further connected to a third capacitor C via a fifth switch S5 3，1 A second terminal of, a third capacitor C 3，1 Is connected with a fourth capacitor C 4，1 A first terminal of (C), a first capacitor C 1，1 Is connected to the fourth capacitor C via a sixth switch S6 4，1 The second end of (a).
In the first place, combining FIG. 1 and FIG. 2AIn the off-capacitor network SCN1, the first input contact V BE1 Are connected to the emitter of a first triode Q1 and a second input contact V BE2 The emitter of the second triode Q2 is connected, the third input joint GND is grounded, and the first output joint V ref，1 Connecting a third capacitor C 3，1 A first input contact V BE1 Another one of them is connected with a fourth capacitor C 4，1 The second end of (a).
Similarly, the second switched capacitor network SCN2 includes 6 switches and 4 capacitors, and the circuit configuration of the 6 switches and 4 capacitors is the same as that of the first switched capacitor network SCN 1.
Specifically, as shown in FIG. 2B, second switched-capacitor network SCN2 is formed by a fifth capacitor C 1，2 A sixth capacitor C 2，2 A seventh capacitor C 3，2 An eighth capacitor C 4，2 A seventh switch S7, an eighth switch S8, a ninth switch S9, a tenth switch S10, an eleventh switch S11, and a sixth switch S12.
Wherein the input terminal of the second switched capacitor network SCN2 is connected to the fourth input node V BE1 The fifth input contact V BE2 And a sixth input contact V TEMP_COMP The output end is a second output contact V ref 。
The fourth input contact V BE1 Having two, fourth input contacts V BE1 Is connected to the fifth capacitor C via an eighth switch S8 1，2 First end of (2), fifth input contact V BE2 Is connected to a sixth capacitor C through a seventh switch S7 2，2 First terminal of (1), sixth capacitor C 2，2 Is connected with a fifth capacitor C 1，2 First end of (2), fifth input contact V BE2 Is also connected to a fifth capacitor C through a ninth switch S9 1，2 A second end of (a).
Sixth capacitor C 2，2 Is further connected to a sixth input contact V via a tenth switch S10 TEMP_COMP Seventh capacitance C 3，2 First end of the first input terminal is connected to a sixth input contact V TEMP_COMP Sixth capacitor C 2，2 Is connected to a seventh capacitor C via an eleventh switch S11 3，2 Second end, seventh endCapacitor C 3，2 Is connected with an eighth capacitor C 4，2 First terminal of (1), fifth capacitor C 1，2 Is connected to an eighth capacitor C through a twelfth switch S12 4，2 The second end of (a). Fourth input contact V BE1 Another one of them is connected with an eighth capacitor C 4，2 The second end of (a).
Referring to fig. 1 and 2B, in the second switched capacitor network SCN2, the fourth input node V BE1 Are connected to the emitter of the first triode Q1 and the fifth input contact V BE2 The emitter of the second triode Q2 is connected, and the sixth input contact V TEMP_COMP Connected to the output of the operational amplifier A, a second output contact V ref For outputting a bandgap reference voltage.
In the embodiment of the present invention, all switches in the first switched capacitor network SCN1 and the second switched capacitor network SCN2 have the same structure and size.
So far, the basic structure of the bandgap reference circuit provided by the embodiment of the present invention has been completely described, and the operating principle of the bandgap reference circuit is further described below.
As shown in fig. 2A, in the first switched capacitor network SCN1, a first switch S1, a second switch S2 and a third switch S3 form a first phase clock signal that is turned on and off at the same time, a fourth switch S4, a fifth switch S5 and a sixth switch S6 form a second phase clock signal that is turned on and off at the same time, and the first phase clock signal and the second phase clock signal form a two-phase non-overlapping clock.
In the embodiment of the invention, first, the first phase clock signal is closed at the same time, the second phase clock signal is opened at the same time, and at the moment, the charge of the switched capacitor network under the first phase clock signal is calculated. Then, the first phase clock signal is turned off at the same time, the second phase clock signal is turned on at the same time, the charge of the switched capacitor network under the second phase clock signal is calculated, and the difference of the charge amounts of the two non-overlapping clocks obtained by charge conservation is as follows:
wherein, N represents the number of the second triode Q2 connected in parallel.
As shown in fig. 2B, in the second switched capacitor network SCN2, the seventh switch S7, the eighth switch S8 and the ninth switch S9 constitute a third phase clock signal that is turned on and off at the same time, the tenth switch S10, the eleventh switch S11 and the sixth switch S12 constitute a fourth phase clock signal that is turned on and off at the same time, and the third phase clock signal and the fourth phase clock signal also constitute a two-phase non-overlapping clock.
In the embodiment of the invention, firstly, the third phase clock signal is simultaneously closed, the fourth phase clock signal is simultaneously opened, and at the moment, the charge of the switched capacitor network under the third phase clock signal is calculated. Then, the third phase clock signal is simultaneously turned off, the fourth phase clock signal is simultaneously turned on, the charge of the switched capacitor network under the fourth phase clock signal is calculated, and the difference of the charge amount of the two non-overlapping clocks obtained by charge conservation is as follows:
with continued reference to FIG. 1, since the first switched capacitor network SCN1 and the second switched capacitor network SCN2 are connected through a unity gain negative feedback amplifier A, a single-stage negative feedback amplifier is obtained
In a circuit implementation, C may be selected 1，2 ＜＜C 2，2 Thereby making
Then, as can be seen from the above, the bandgap reference circuit provided by the embodiment of the present invention generates the reference voltage of
Wherein, V ref，2 Representing the charge increment of the second switched-capacitor network SCN 2.
It can be understood that the maximum error of the reference voltage circuit implemented by using the switched capacitor network provided by the embodiment of the present invention comes from the ripple voltage caused by the switch during switching, and the ripple voltage can be improved by adjusting the on-off timing of the two-phase non-overlapping clock.
Further, compared with the traditional band-gap reference circuit, the invention has the following advantages: in the conventional bandgap reference circuit, a typical value of the resistance matching accuracy is 0.4%, and a typical value of the resistance absolute value error is 20%. However, through tests, in the bandgap reference circuit of this embodiment shown in fig. 1, a typical value of the capacitance matching accuracy is 0.05%, and a typical value of the capacitance absolute value error is 10%. In addition, the temperature characteristic is improved by adopting a mode of superposition compensation of two reference voltages consisting of the first switched capacitor network SCN1 and the second switched capacitor network SCN 2. Therefore, the error rate of the band gap reference voltage of the invention is reduced 1/8 compared with the traditional structure, and the temperature coefficient is reduced to 1/2 of the traditional structure.
In summary, the embodiments of the present invention provide a bandgap reference circuit, which adopts a different implementation structure from that of an existing bandgap reference circuit, and improves the precision of the reference voltage generated by the bandgap reference circuit by using the characteristics of high capacitance matching precision and low absolute value error. In addition, the invention adopts a mode of mutual compensation of two reference voltages, improves the temperature characteristic and reduces the temperature coefficient of the band-gap reference circuit.
It should also be noted that directional terms, such as "upper", "lower", "front", "rear", "left", "right", and the like, used in the embodiments are only directions referring to the drawings, and are not intended to limit the scope of the present disclosure. Throughout the drawings, like elements are represented by like or similar reference numerals. Conventional structures or constructions will be omitted when they may obscure the understanding of the present disclosure. And the shapes and sizes of the respective components in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure.
It should be noted that the use of "first", "second", "third", etc. in this disclosure is only for distinguishing between different objects and does not imply any particular sequential relationship between the objects. Furthermore, in the present invention, the terms "include" and "comprise," along with their derivatives, mean inclusion without limitation; the term "or" is inclusive, meaning and/or.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A bandgap reference circuit, comprising a first MOS transistor (M1), a second MOS transistor (M2), a first transistor (Q1), a second transistor (Q2), a first switched capacitor network (SCN1), a second switched capacitor network (SCN2), and an operational amplifier (A), wherein:
the sources of the first MOS transistor (M1) and the second MOS transistor (M2) are both connected with an input power supply, and the gates of the first MOS transistor (M1) and the second MOS transistor (M2) are interconnected and are both connected with the drain of the first MOS transistor (M1);
the emitter of the first triode (Q1) is connected with the drain of the first MOS tube (M1), and the emitter of the second triode (Q2) is connected with the drain of the second MOS tube (M2);
the emitter electrode of the first triode (Q1) and the emitter electrode of the second triode (Q2) are connected with a first switched capacitor network (SCN1) and a second switched capacitor network (SCN 2);
the first switched capacitor network (SCN1) is connected with the second switched capacitor network (SCN2) through an operational amplifier (A), and the second switched capacitor network (SCN2) outputs a band gap reference voltage.
2. The bandgap reference circuit according to claim 1, wherein the operational amplifier (a) is a unity gain negative feedback amplifier.
3. The bandgap reference circuit according to claim 1, wherein the first switched capacitor network (SCN1) is connected to the positive input of the operational amplifier (a), the negative input and output of the operational amplifier (a) are connected, and the first switched capacitor network (SCN2) is connected.
4. The bandgap reference circuit of claim 1, wherein the base and collector of the first transistor (Q1) and the second transistor (Q2) are both grounded.
5. The bandgap reference circuit according to claim 1, wherein the first MOS transistor (M1) and the second MOS transistor (M2) have the same size.
6. The bandgap reference circuit according to claim 1, wherein the second transistor (Q2) is composed of a plurality of transistors connected in parallel and having the same size as the first transistor (Q1).
7. The bandgap reference circuit according to claim 1, wherein the first switched capacitor network (SCN1) is formed by a first capacitor (C) 1，1 ) A second capacitor (C) 2，1 ) A third capacitor (C) 3，1 ) A fourth capacitor (C) 4，1 ) A first switch (S1), a second switch (S2), a third switch (S3), a fourth switch (S4), a fifth switch (S5), and a sixth switch (S6), wherein:
the input terminal of the first switched capacitor network (SCN1) is connected with a first input contact (V) BE1 ) A second input contact (V) BE2 ) And a third input contact (GND), the output terminal being a first output contact (V) ref，1 ) Said first input contact (V) BE1 ) Has two;
the first input contact (V) BE1 ) Is connected to the first capacitance (C) via a second switch (S2) 1，1 ) Said second input contact (V) BE2 ) Is connected to the second power through a first switch (S1)Capacitor (C) 2，1 ) Said second capacitor (C) 2，1 ) Is connected to said first capacitor (C) 1，1 ) Said second input contact (V) BE2 ) Is also connected to the first capacitance (C) through a third switch (S3) 1，1 ) A second end of (a);
the second capacitance (C) 2，1 ) Is further connected to the third input contact (GND) via a fourth switch (S4), the third capacitor (C) 3，1 ) Is connected to the third input contact (GND), the second capacitor (C) 2，1 ) Is further connected to said third capacitance (C) through a fifth switch (S5) 3，1 ) The second terminal of (C), the third capacitance (C) 3，1 ) Is connected to said fourth capacitance (C) 4，1 ) Said first capacitor (C) 1，1 ) Is connected to the fourth capacitance (C) via a sixth switch (S6) 4，1 ) The second end of (a).
8. Bandgap reference circuit according to claim 7, characterized in that the first input contact (V) BE1 ) Are connected to the emitter of the first transistor (Q1), the second input contact (V) BE2 ) The emitter of the second triode (Q2) is connected, the third input contact (GND) is grounded, and the first output contact (V) ref，1 ) Connecting the third capacitor (C) 3，1 ) Said first input contact (V) BE1 ) Is connected to said fourth capacitance (C) 4，1 ) The second end of (a).
9. The bandgap reference circuit according to claim 7, wherein the second switched capacitor network (SCN2) comprises 6 switches and 4 capacitors, the circuit structure of the 6 switches and 4 capacitors is the same as that of the first switched capacitor network (SCN1), and the input terminal of the second switched capacitor network (SCN2) is connected to the fourth input node (V) BE1 ) A fifth input contact (V) BE2 ) And a sixth input contact (V) TEMP_COMP ) The output terminal is a second output contact (V) ref ) Said fourth input contact (V) BE1 ) Has twoA, wherein:
the fourth input contact (V) BE1 ) Are connected to the emitter of the first triode (Q1), and the fifth input contact (V) BE2 ) The emitter of the second triode (Q2) and the sixth input contact (V) TEMP_COMP ) The second output contact (V) is connected to the output end of the operational amplifier (A) ref ) For outputting a bandgap reference voltage.
10. The bandgap reference circuit of claim 9, wherein all switches in said first switched capacitor network (SCN1) and said second switched capacitor network (SCN2) are identical in structure and size.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116107379A (en) * | 2023-04-10 | 2023-05-12 | 成都市易冲半导体有限公司 | Bandgap reference voltage source circuit, integrated circuit and electronic equipment |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116107379A (en) * | 2023-04-10 | 2023-05-12 | 成都市易冲半导体有限公司 | Bandgap reference voltage source circuit, integrated circuit and electronic equipment |
| CN116107379B (en) * | 2023-04-10 | 2023-06-23 | 成都市易冲半导体有限公司 | Bandgap reference voltage source circuit, integrated circuit and electronic equipment |
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