CN215818082U - Low-power consumption frequency comparator - Google Patents
Low-power consumption frequency comparator Download PDFInfo
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- CN215818082U CN215818082U CN202122190220.3U CN202122190220U CN215818082U CN 215818082 U CN215818082 U CN 215818082U CN 202122190220 U CN202122190220 U CN 202122190220U CN 215818082 U CN215818082 U CN 215818082U
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Abstract
The utility model discloses a low-power-consumption frequency comparator, which belongs to the field of electronic circuits and comprises a signal preprocessor, a signal conversion device and a signal comparison device. The signal preprocessor part processes the received input signal and generates two paths of voltage signals to the subsequent signal conversion part; the signal conversion device converts the current of the two paths of voltage signals and generates a voltage signal to the signal comparison device through the capacitor; the signal comparison device compares the voltage signal generated by the signal conversion device with the reference voltage signal and outputs a final logic signal. The utility model integrates the low-power consumption frequency comparator in the system on chip, realizes a resistance-free structure on the basis of not increasing the complexity of a peripheral circuit and enlarging the volume, and reduces the power consumption of the circuit to the maximum extent, thereby having the advantages of low power consumption, easy integration and the like.
Description
Technical Field
The utility model relates to the field of frequency detection, in particular to a low-power-consumption frequency comparator.
Background
The frequency comparison circuit is widely applied to the measurement technology and the communication technology, and has the function of comparing the frequencies of two input signals to obtain a result judgment size relation.
In the existing frequency comparison circuit design, one type of frequency comparison circuit mostly adopts structures such as a D trigger, a bias circuit, a Schmitt trigger, a latch and other logic gates, and the like, and the comparison circuit has poor precision, low speed and more complex structure; another type of comparator mainly employs a charge pump, a flip-flop, a logic judgment circuit, etc., which are complex in structure, and therefore, it is necessary to develop a low-power frequency comparator to solve the above problems.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a low-power-consumption frequency comparator which is used for comparing the frequency of two input signals in real time and providing a comparison result signal.
In order to solve the technical problem, the utility model provides a low-power frequency comparator, which comprises a signal preprocessor, a signal conversion device and a signal comparison device;
the signal preprocessor is used for processing and respectively receiving input signals and respectively generating two paths of voltage signals to the signal conversion device;
the signal conversion device respectively carries out current conversion on the two paths of voltage signals generated by the signal conversion device, and finally generates a voltage signal to the signal comparison device through the capacitor;
and the signal comparison device compares the voltage signal generated by the signal conversion device with the reference voltage signal and outputs a final logic signal.
Optionally, the signal preprocessor inverters INV1, INV2 and RS latches RS1, RS 2;
two paths of frequencies are used as input signals and are respectively and simultaneously connected to the input end of the inverter INV and the R input end of the RS latch;
an output end of the inverter INV1 is connected to the S end of the RS latch RS 1.
Optionally, the signal conversion device includes PMOS transistors MP1, MP2, NMOS transistors MN1, MN2, MN3, and capacitors C1, C2, and C3;
the gates of the PMOS tubes MP1 and MP2 are respectively connected with the output end Q, Q' of the RS1 in the signal preprocessor; the source electrode of the PMOS transistor MP1 is connected with the upper electrode plate of the capacitor C1 in parallel and is connected with a power supply; the drain electrode of the PMOS pipe MP1 is interconnected with the source electrode of the PMOS pipe P2 and the lower polar plate of the capacitor C1;
the gates of the NMOS tubes MN1 and MN2 are respectively connected with the output end Q, Q' of the RS2 in the signal preprocessor; the source electrode of the NMOS transistor MN1 is interconnected with the drain electrode of the NMOS transistor MN2 and the upper electrode plate of the capacitor C2; the source electrode of the NMOS transistor MN2 is interconnected with the lower plate of the capacitor C2 and grounded;
the drain electrode of the PMOS tube MP2 is interconnected with the drain electrode of the NMOS tube MN1, the drain electrode of the NMOS tube MN3 and the upper-level plate of the capacitor C3; the source electrode of the NMOS transistor MN3 is connected with the lower plate of the capacitor C3 to be grounded;
optionally, the PMOS transistor MP1 and the PMOS transistor MP2 have the same size, the NMOS transistors MN1, MN2 and MN3 have the same size, and the capacitors C1 and C2 have the same size.
Optionally, the low power consumption frequency comparator is characterized in that the signal comparison device includes PMOS transistors MP3, MP4 and a voltage comparator COMP;
the source electrode of the PMOS tube MP3 is connected with the power supply, and the drain electrode of the PMOS tube MP4 is interconnected with the grid electrode, the source electrode of the PMOS tube MP4 and the inverted input end of the voltage comparator COMP; the drain and gate of the PMOS transistor MP4 are connected to each other and to ground.
The PMOS tubes MP3 and MP4 have the same size.
The utility model has the beneficial effects that:
the low-power-consumption frequency comparator provided by the utility model comprises a signal pre-processing device, a signal conversion device and a signal comparison device. The signal preprocessor part processes the received input signal and respectively generates two paths of voltage signals to the subsequent signal conversion part; the signal conversion device respectively carries out current conversion on the two paths of voltage signals and generates a voltage signal to the signal comparison device through the capacitor; the signal comparison device compares the voltage signal generated by the signal conversion device with the reference voltage signal and outputs a final logic signal. The utility model integrates the low-power consumption frequency comparator in the system on chip, realizes a resistance-free structure on the basis of not increasing the complexity of a peripheral circuit and enlarging the volume, and reduces the power consumption of the circuit to the maximum extent, thereby having the advantages of low power consumption, easy integration and the like.
Drawings
FIG. 1 is a schematic diagram of a low power consumption frequency comparator according to the present invention;
fig. 2 is a diagram illustrating the correspondence between the upper plate voltage variation of the capacitors C1, C2 and C3 and the IN1, IN3 frequencies when the IN1 frequency is greater than the IN2 frequency.
In the figure: 101-signal preprocessor device, 102-signal conversion device and 103-signal comparison device.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
The utility model provides a low-power consumption frequency comparator, the structure of which is shown in fig. 1, and the low-power consumption frequency comparator comprises a signal preprocessor component 101, a signal conversion component 102 and a signal comparison component 103; the signal preprocessor 101 processes the received input signal and generates two voltage signals to the subsequent signal conversion device 102; the signal conversion device 102 converts the two voltage signals into current, and generates a voltage signal to the signal comparison device 103 through a capacitor; the signal comparison device 103 compares the voltage signal generated by the signal conversion device 102 with a reference voltage signal, and outputs a final logic signal.
With continued reference to fig. 1, the signal preprocessor 101 includes inverters INV1 and INV2, and RS latches RS1 and RS 2; the frequency IN1 is used as one input signal to be simultaneously connected to the input end of the inverter INV1 and the R input end of the RS latch RS1, and the frequency IN2 is used as the other input signal to be simultaneously connected to the input end of the inverter INV2 and the R input end of the RS latch RS 2; the output end of the inverter INV1 is connected with the S end of the RS latch RS1, and the output end of the inverter INV2 is connected with the S end of the RS latch RS 2; the signal pre-processing device 101 generates a pair of voltage signals having opposite phases, respectively.
The signal conversion device 102 comprises PMOS tubes MP1, MP2, NMOS tubes MN1, MN2 and MN3, and capacitors C1, C2 and C3; the gates of the PMOS transistors MP1 and MP2 are respectively connected to the output terminal Q, Q '(i.e., in fig. 1) of the RS1 in the signal preprocessor, and the gates of the NMOS transistors MN1 and MN2 are respectively connected to the output terminal Q, Q' (i.e., in fig. 1) of the RS2 in the signal preprocessor; the source electrode of the PMOS transistor MP1 and the upper electrode plate of the capacitor C1 are connected with each other and connected with a power supply in parallel; the drain electrode of the PMOS tube MP1 is interconnected with the source electrode of the PMOS tube MP2 and the lower polar plate of the capacitor C1; the drain electrode of the PMOS tube P2 is connected with the drain electrode of the NMOS tube MN1, the drain electrode of the MN3 and the upper polar plate of the capacitor C3; the source of the NMOS transistor MN1 is interconnected with the drain of the MN2 and the upper plate of the capacitor C2, the source of the NMOS transistor MN2 is interconnected with the lower plate of the capacitor C2, the source of the NMOS transistor MN3 and the lower plate of the capacitor C3 and is grounded; the sizes of the PMOS tubes MP1 and MP2 are the same, the sizes of the NMOS tubes MN1 and MN2 are the same, and the sizes of the capacitor C1 and the capacitor C2 are the same. The gates of the PMOS transistors MP1 and MP2 receive two signals with opposite phases generated by the RS latch RS1 in the signal preprocessor, respectively, the PMOS transistors MP1 and MP2 are alternately turned on, and when the PMOS transistor MP1 is turned on and the PMOS transistor MP2 is turned off, the voltage V across the capacitor C1 is appliedC1Are all equal to the supply voltage VDD; when the PMOS transistor MP1 is turned off and MP2 is turned on, the capacitors C1 and C3 are connected in series, so that the charge of the capacitor C1 is injected into the capacitor C3, resulting in the voltage V on the upper plate of the capacitor C3C3Periodically rising; when the NMOS transistor MN1 is turned on and MN2 is turned off, the capacitor C3 is interconnected with the capacitor C2, so that part of the charge on the upper plate of the capacitor C3 is injected into the upper plate of the capacitor C2, resulting in the upper plate voltage V of the capacitor C2C2The voltage V of the upper plate of the D capacitor C3 risesC3Descending; when the NMOS transistor MN1 is turned off and MN2 is turned on, the charge on the top plate of the capacitor C2 is discharged to ground through MN2, and thus the voltage V on the top plate of the capacitor C3C3As the switches of MP1, MP2, MN1, and MN2 exhibit periodic variations; due to the alternate conduction of MP1, MP2, the alternate conduction of MN1, MN2 receives the influence of the input signals IN1 and IN2, respectively, so there are three cases: when the frequency of IN1 is higher than that of IN2, the number of times that the capacitor C1 charges the upper plate of the capacitor C3 is more than the number of times that the capacitor C2 transfers the charge of the upper plate of the capacitor C3,therefore, the voltage V of the upper plate of C3C3Will increase all the time; when the frequency of IN1 is equal to the frequency of IN2, the number of times that the capacitor C1 charges the upper plate of the capacitor C3 is equal to the number of times that the capacitor C2 transfers the charges to the upper plate of the capacitor C3, and the charges on the upper plate of the capacitor C3 are kept unchanged, so that the V is equal to the frequency of the IN1C3The change is not changed; thirdly, when the IN1 frequency is less than the IN2 frequency, the charging times of the capacitor C1 to the upper plate of the capacitor C3 are less than the charge transfer times of the capacitor C2 to the capacitor C3, therefore, VC3Will become smaller; fig. 2 is a diagram illustrating the correspondence between the upper plate voltage variation of the capacitors C1, C2 and C3 and the IN1, IN3 frequencies when the IN1 frequency is greater than the IN2 frequency.
The signal comparison device 103 comprises PMOS tubes MP3, MP4 and a voltage comparator COMP; the source electrode of the PMOS tube MP3 is connected with the power supply, and the drain electrode of the PMOS tube MP4 is interconnected with the grid electrode, the source electrode of the PMOS tube MP4 and the inverted input end of the voltage comparator COMP; the drain and the gate of the PMOS tube MP4 are connected with each other and grounded; the non-inverting input of the voltage comparator COMP is connected to the upper plate of the capacitor C3 in the signal conversion device. The PMOS tubes MP3 and MP4 are inverse proportion tubes, the gates and the sources of the PMOS tubes are interconnected and work IN a sub-threshold region, the current is small, the impedance is extremely large, the MP3 and the MP4 form series voltage division, and the MP3 and the MP4 have the same size, so the obtained voltage division serving as a reference is VDD/2, IN an initial state, due to the fact that no input signal exists, the output of the voltage comparator COMP is low level, only when the input frequency of the IN1 is larger than the input frequency of the IN2, the output logic of the voltage comparator COMP is inverted, and at the moment, high level is output, and the comparison frequency is shown.
In the case of no frequency, since the output of the RS flip-flop RS1 is a dc voltage, the PMOS transistors P1 and P2 are not turned on alternately to charge the capacitor C2, and therefore the output of the voltage comparator COMP remains low and does not compare to the frequency.
In the present embodiment, the gate of the NMOS transistor N3 in the signal conversion device 102 is connected to the enable signal Ven to discharge the charge of the capacitor C3, thereby preventing the malfunction.
The MOS transistor and the capacitor are adopted, so that a resistance-free structure is realized, and the power consumption of the circuit is reduced to the greatest extent, so that the MOS transistor and the capacitor have the advantages of low power consumption, easiness in integration and the like.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A low power consumption frequency comparator is characterized by comprising a signal preprocessor component, a signal conversion component and a signal comparison component;
the signal pre-processor processes the respectively received input signals and respectively generates two paths of voltage signals to the signal conversion device;
the signal conversion device respectively carries out current conversion on the two paths of voltage signals generated by the signal conversion device, and finally generates a voltage signal to the signal comparison device through the capacitor;
and the signal comparison device compares the voltage signal generated by the signal conversion device with a reference voltage signal and outputs a final logic signal.
2. The low power consumption frequency comparator as claimed in claim 1, wherein the signal pre-processor device comprises inverters INV1, INV2 and RS latches RS1, RS 2;
two paths of frequencies are used as input signals and are respectively and simultaneously connected to the input end of the inverter INV and the R input end of the RS latch;
and the output end of the inverter INV is connected with the S end of the RS latch.
3. The low-power frequency comparator as claimed in claim 1, wherein the signal conversion device comprises PMOS transistors MP1, MP2, NMOS transistors MN1, MN2, MN3, and capacitors C1, C2, C3.
4. The low-power-consumption frequency comparator as claimed in claim 3, wherein the gates of the PMOS transistors MP1 and MP2 are respectively connected to the output end Q, Q' of RS1 in the signal preprocessor; the source electrode of the PMOS pipe MP1 is connected with the upper plate of the capacitor C1 and is connected with a power supply; the drain of the PMOS transistor MP1 is interconnected with the source of the PMOS transistor P2 and the bottom plate of the capacitor C1.
5. The low-power frequency comparator as claimed in claim 4, wherein the gates of said NMOS transistors MN1, MN2 are respectively connected to the output terminal Q, Q' of RS2 in said signal preprocessor; the source electrode of the NMOS transistor MN1 is interconnected with the drain electrode of the NMOS transistor MN2 and the upper electrode plate of the capacitor C2; the source of the NMOS transistor MN2 is connected to the lower plate of the capacitor C2 and to ground.
6. The low-power consumption frequency comparator as claimed in claim 5, wherein the drain of the PMOS transistor MP2 is interconnected with the drain of NMOS transistor MN1, the drain of NMOS transistor MN3 and the upper board of capacitor C3; the source of the NMOS transistor MN3 is interconnected with the lower plate of the capacitor C3 and to ground.
7. The low-power frequency comparator in claim 6, wherein the PMOS transistor MP1 and the PMOS transistor MP2 are the same size, the NMOS transistors MN1, MN2 and MN3 are the same size, and the capacitors C1 and C2 are the same size.
8. The low-power-consumption frequency comparator according to claim 1, wherein the signal comparison device comprises PMOS transistors MP3, MP4 and a voltage comparator COMP.
9. The low-power-consumption frequency comparator as claimed in claim 8, wherein the source of the PMOS transistor MP3 is connected to the power supply, and the drain is interconnected with the gate, the source of the PMOS transistor MP4 and the inverting input terminal of the voltage comparator COMP; the drain and gate of the PMOS transistor MP4 are connected to each other and to ground.
10. The low-power frequency comparator in accordance with claim 8, wherein the PMOS transistors MP3 and MP4 are the same size.
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| CN202122190220.3U CN215818082U (en) | 2021-09-10 | 2021-09-10 | Low-power consumption frequency comparator |
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| CN202122190220.3U CN215818082U (en) | 2021-09-10 | 2021-09-10 | Low-power consumption frequency comparator |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115664395A (en) * | 2022-10-27 | 2023-01-31 | 江苏韩娜新能源有限公司 | High-precision comparator for Boost converter and Boost converter |
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2021
- 2021-09-10 CN CN202122190220.3U patent/CN215818082U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115664395A (en) * | 2022-10-27 | 2023-01-31 | 江苏韩娜新能源有限公司 | High-precision comparator for Boost converter and Boost converter |
| CN115664395B (en) * | 2022-10-27 | 2023-11-10 | 深圳市时代创新科技有限公司 | High-precision comparator for Boost converter and Boost converter |
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