CN108390550B - Adjusting circuit for controlling conduction time - Google Patents

Adjusting circuit for controlling conduction time Download PDF

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Publication number
CN108390550B
CN108390550B CN201810348235.8A CN201810348235A CN108390550B CN 108390550 B CN108390550 B CN 108390550B CN 201810348235 A CN201810348235 A CN 201810348235A CN 108390550 B CN108390550 B CN 108390550B
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circuit
tube
resistor
pmos
reference voltage
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CN108390550A (en
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李泽宏
张成发
孙河山
熊涵风
赵念
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection

Abstract

An adjusting circuit for controlling conduction time belongs to the technical field of electronic circuits. The reference voltage generating circuit is used for generating required reference voltage, different signals are generated in the voltage sampling circuit by controlling the minimum conduction time control end of the voltage sampling circuit to be suspended or connected with a ground level or an off-chip resistor, so that the transmission gate in the conduction control circuit outputs different voltage values, and the output signals of the conduction control circuit are generated after passing through a filter consisting of a first capacitor and a first resistor; the minimum on-time output circuit generates voltage control signals with different on-times according to feedback of an output signal of the on-control circuit, an external enable signal and an output signal of the minimum on-time output circuit. The invention can accurately control the on-off of the switch tube in the switch power supply and solves the influence of the process deviation of the resistor on the on-time.

Description

Adjusting circuit for controlling conduction time
Technical Field
The invention belongs to the technical field of electronic circuits, and particularly relates to an adjusting circuit for controlling conduction time.
Background
In a power switch control circuit, due to the influence of a process and external factors, a source-drain voltage or current of a power switch tube often generates burrs or oscillation, which can cause the power switch tube to be switched on or off by mistake, thereby causing instability and poor reliability of a designed system. To solve this problem, an on-time adjustment circuit is usually added to the driver IC to reduce glitches and ringing. Conventionally, a circuit is used for conducting or adjusting the gate resistance of a driving output end in a fixed time, but different driving ICs have different device processes and types, so that the required time is different, and the method adopting the fixed time has great limitation; secondly, because the external resistor has large variation with temperature and is easily influenced by the process, the method for adjusting the gate resistor can cause the obtained result to have large deviation with the ideal value.
Disclosure of Invention
Aiming at the problems of the traditional fixed-time conduction and adjustment of the gate resistance of the driving output end, the invention provides the adjusting circuit for controlling the conduction time, the conduction time is adjusted through different connection methods of the minimum conduction time control end MOT, so that the conduction time requirements of different applications are met, the internal voltage cannot be influenced by the process deviation of the resistor, and the precision and the high reliability of the conduction time are ensured.
The technical scheme of the invention is as follows:
an adjusting circuit for controlling the conduction time comprises a voltage sampling circuit 1, a reference voltage generating circuit 2, a conduction control circuit 3 and a minimum conduction time control circuit 4,
the voltage sampling circuit 1 comprises a sampling resistor R0, one end of the sampling resistor R0 is used as a minimum on-time control end MOT, and the other end of the sampling resistor R0 is connected with the output end of the voltage sampling circuit 1;
the turn-on control circuit 3 comprises a transmission gate, a first capacitor C1, a first resistor R1 and a first hysteresis comparator,
a first input end of the transmission gate is connected with a first reference voltage VREF1, a second input end of the transmission gate is used as a first input end of the conduction control circuit 3, and an output end of the transmission gate is connected with one end of a first resistor R1;
one end of the first capacitor C1 is connected to the other end of the first resistor R1 and serves as the output end of the conduction control circuit 3, and the other end thereof is grounded;
the reverse input end of the first hysteresis comparator, which is used as the second input end of the conduction control circuit, is connected with the output end of the voltage sampling circuit 1, the positive input end of the first hysteresis comparator is connected with the bias voltage VB, and the output end of the first hysteresis comparator is connected with the control end of the transmission gate;
the input end of the minimum on-time control circuit 4 is connected with the output end of the on-time control circuit 3, and the output end of the minimum on-time control circuit is used as the output end of the adjusting circuit;
the reference voltage generation circuit 2 is configured to generate a reference voltage, which includes a first reference voltage VREF 1.
Specifically, a first input terminal of the conduction control circuit 3 is connected to a second reference voltage VREF2 and an output terminal of the voltage sampling circuit, and the second reference voltage VREF2 is generated by the reference voltage generation circuit 2.
Specifically, the voltage sampling circuit 1 further includes a second capacitor C2, a second resistor R2, a third resistor R3, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a first operational amplifier OP1, a second operational amplifier OP2, and a first reference current source IREF1,
the drain electrode of the first NMOS tube MN1 is connected with the output end of the voltage sampling circuit 1 and the positive input end of the first operational amplifier OP1, and the grid electrode and the source electrode are grounded;
the second capacitor C2 is connected between the drain of the first NMOS transistor MN1 and the ground;
the positive end of the first reference current source IREF1 is connected with a power supply voltage, and the negative end of the first reference current source IREF1 is connected with the positive input end of the first operational amplifier OP1 after passing through the second resistor R2;
the gate of the second NMOS transistor MN2 is connected to the output terminal of the first operational amplifier OP1, the drain thereof is connected to the drain of the third NMOS transistor MN3 and to the power supply voltage, and the source thereof is connected to the source of the third NMOS transistor MN3, the inverting inputs of the second operational amplifier OP2 and the first operational amplifier OP1, and the first input of the on-state control circuit 3, and is grounded through the third resistor R3;
the positive input end of the second operational amplifier OP2 is connected to a second reference voltage VREF2, the output end of the second operational amplifier OP2 is connected to the gate of the third NMOS transistor MN3, and the second reference voltage VREF2 is generated by the reference voltage generating circuit 2.
Specifically, the reference voltage generating circuit 2 includes a third operational amplifier OP3, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6,
the positive input end of the third operational amplifier OP3 is connected to the reference voltage VBG, the negative input end thereof is connected to the drain of the first PMOS transistor MP1 and grounded through the fourth resistor R4, and the output end thereof is connected to the gates of the first PMOS transistor MP1, the second PMOS transistor MP2 and the third PMOS transistor MP 3;
the drain of the second PMOS transistor MP2 is connected to one end of the fifth resistor R5 and outputs the first reference voltage VREF1, and the source thereof is connected to the sources of the first PMOS transistor MP1 and the third PMOS transistor MP3 and to the power supply voltage;
the drain of the third PMOS transistor MP3 is connected to one end of the sixth resistor R6 and outputs the second reference voltage VREF 2; the other end of the fifth resistor R5 and the other end of the sixth resistor R6 are grounded.
Specifically, the bias voltage VB is a third reference voltage VREF3, the third reference voltage VREF3 is generated by the reference voltage generation circuit 2, the reference voltage generation circuit 2 further includes a fourth PMOS transistor MP4 and a seventh resistor R7, a gate of the fourth PMOS transistor MP4 is connected to the output of the third operational amplifier OP3, a source thereof is connected to the power supply voltage, a drain thereof is connected to one end of the seventh resistor R7 and outputs the third reference voltage VREF3, and the other end of the seventh resistor R7 is grounded.
Specifically, the minimum on-time control circuit 4 comprises a charge-discharge circuit, a fourth NMOS transistor MN4, a third capacitor C3, a second hysteresis comparator, a third hysteresis comparator, a first nand gate, a second nand gate, a first inverter and a counter,
the output end of the charge-discharge circuit is connected with the reverse input end of the second hysteresis comparator, the forward input end of the third hysteresis comparator and the drain electrode of the fourth NMOS tube MN4, and is grounded after passing through a third capacitor C3, and the charge-discharge circuit is used for controlling the charge and discharge of the third capacitor C3;
the positive input end of the second hysteresis comparator is used as the input end of the minimum on-time control circuit 4, the output end of the second hysteresis comparator is connected with the first input end of the second nand gate, the negative input end of the third hysteresis comparator is connected with a fourth reference voltage VREF0, the output end of the third hysteresis comparator is connected with the first input end of the first nand gate, and the fourth reference voltage VREF0 is generated by the reference voltage generation circuit 2;
the second input end of the first nand gate is connected with the second input end of the second nand gate and is connected with an external enable signal ENA, the third input end of the first nand gate is connected with the output end of the second nand gate and the input end of the first inverter, the output end of the first nand gate is connected with the third input end of the second nand gate and the input end of the counter, and the output end of the counter is used as the output end of the minimum on-time control circuit 4 and is connected with the grid electrode of a fourth NMOS transistor MN 4; the source electrode of the fourth NMOS transistor MN4 is grounded; the output end of the first inverter is connected with the control end of the charge and discharge circuit;
the reference voltage generating circuit 2 further includes a fifth PMOS transistor MP5 and an eighth resistor R8, a gate of the fifth PMOS transistor MP5 is connected to the output terminal of the third operational amplifier OP3, a source thereof is connected to the power voltage, a drain thereof is connected to one end of the eighth resistor R8 and outputs the fourth reference voltage VREF0, and the other end of the eighth resistor R8 is grounded.
Specifically, the charge and discharge circuit comprises a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8 and a ninth PMOS transistor MP9,
the gate of the ninth PMOS transistor MP9 is connected to the output terminal of the third operational amplifier OP3 in the reference voltage generating circuit 2, the drain thereof is connected to the gates of the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7 and the drain of the sixth NMOS transistor MN6, and the source thereof is connected to the sources of the sixth PMOS transistor MP6, the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 and is connected to the supply voltage;
the drain electrode of the seventh NMOS transistor MN7 is connected to the drain electrodes of the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 and the gate electrodes of the sixth PMOS transistor MP6 and the eighth PMOS transistor MP8, and the source electrode thereof is connected to the source electrodes of the sixth NMOS transistor MN6 and the fifth NMOS transistor MN5 and grounded;
the grid electrode of the seventh PMOS pipe MP7 is used as the control end of the charge-discharge circuit; the drain of the eighth PMOS transistor MP8 is connected to the drain of the fifth NMOS transistor MN5 and serves as the output terminal of the charge and discharge circuit.
Specifically, the charge and discharge circuit includes an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a fifteenth NMOS transistor MN15, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fifteenth PMOS transistor MP15, a ninth resistor R9, and a second reference current source IREF2,
the positive end of the second reference current source IREF2 is connected with the power supply voltage, and the negative end of the second reference current source IREF2 is connected with one end of a ninth resistor R9, the eighth NMOS transistor MN8, the ninth NMOS transistor MN9, the twelfth NMOS transistor MN12 and the gate of a thirteenth NMOS transistor MN 13;
the grid electrode of the tenth NMOS transistor MN10 is connected to the grid electrodes of the eleventh NMOS transistor MN11, the fourteenth NMOS transistor MN14 and the fifteenth NMOS transistor MN15, the drain electrode of the eighth NMOS transistor MN8 and the other end of the ninth resistor R9, the drain electrode thereof is connected to the source electrode of the eighth NMOS transistor MN8, and the source electrode thereof is connected to the source electrodes of the eleventh NMOS transistor MN11, the fourteenth NMOS transistor MN14 and the fifteenth NMOS transistor MN15 and grounded;
the source electrode of the ninth NMOS transistor MN9 is connected with the drain electrode of the eleventh NMOS transistor MN11, and the drain electrode of the ninth NMOS transistor MN9 is connected with the gate electrodes of the twelfth PMOS transistor MP12, the thirteenth PMOS transistor MP13, the fourteenth PMOS transistor MP14 and the drain electrode of the fourteenth PMOS transistor MP 14;
the source electrode of the twelfth NMOS transistor MN12 is connected with the drain electrode of the fourteenth NMOS transistor MN14, and the drain electrode thereof is connected with the drain electrodes of the thirteenth PMOS transistor MP13 and the tenth PMOS transistor MP10 and the gate electrodes of the eleventh PMOS transistor MP11 and the fifteenth PMOS transistor MP 15;
the source electrode of the thirteenth NMOS transistor MN13 is connected with the drain electrode of the fifteenth NMOS transistor MN15, and the drain electrode of the thirteenth NMOS transistor MN13 is connected with the drain electrode of the twelfth PMOS transistor MP12 and serves as the output end of the charge and discharge circuit;
the drain electrode of the fifteenth PMOS tube MP15 is connected with the source electrode of the thirteenth PMOS tube MP13, and the source electrode of the fifteenth PMOS tube MP15 is connected with the source electrodes of the tenth PMOS tube MP10, the eleventh PMOS tube MP11 and the fourteenth PMOS tube MP14 and is connected with the power supply voltage;
the gate of the tenth PMOS transistor MP10 is used as the control terminal of the charge and discharge circuit, and the drain of the eleventh PMOS transistor MP11 is connected to the source of the twelfth PMOS transistor MP 12.
Specifically, when the conduction time does not need to be adjusted, the minimum conduction time control end MOT is suspended; when the conduction time needs to be adjusted to be small, the minimum conduction time control end MOT is grounded; and when the conduction time needs to be adjusted to be increased, the minimum conduction time control end MOT is connected with the external resistance RS.
The invention has the beneficial effects that: the invention can accurately control the on-time of the output voltage, thereby preventing the switch tube from being turned on or off by mistake and ensuring the normal work of the circuit; a counter is added, so that the requirement of a circuit on time is met; and the influence of the process deviation of the resistor on the conduction time is solved, and the reliability is improved.
Drawings
Fig. 1 is a schematic structural diagram of an adjustment circuit for controlling an on-time according to a first embodiment.
Fig. 2 is a block diagram of an adjusting circuit for controlling the on-time according to a second embodiment of the present invention.
Fig. 3 is a schematic structural diagram of an adjusting circuit for controlling the on-time according to a second embodiment of the present invention.
Fig. 4 is a schematic diagram of an on-time output of an adjusting circuit for controlling an on-time according to a second embodiment of the present invention.
Detailed Description
The technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.
According to the adjusting circuit for controlling the conduction time, the signal output by the output end of the adjusting circuit is connected with the grid electrode of the switching tube after passing through the driving circuit, the conduction and the disconnection of the switching tube in the switching power supply circuit can be accurately controlled, and the reference voltage is not dependent on resistance change by the designed circuit, so that the influence of the process deviation of the resistance on the conduction time is solved. The invention provides an adjusting circuit for controlling conduction time, which comprises a voltage sampling circuit 1, a reference voltage generating circuit 2, a conduction control circuit 3 and a minimum conduction time control circuit 4, wherein the voltage sampling circuit 1 comprises a sampling resistor R0, one end of the sampling resistor R0 is used as a minimum conduction time control end MOT, and the other end of the sampling resistor R0 is connected with the output end of the voltage sampling circuit 1; the conduction control circuit 3 comprises a transmission gate, a first capacitor C1, a first resistor R1 and a first hysteresis comparator, wherein a first input end of the transmission gate is connected with a first reference voltage VREF1, a second input end of the transmission gate is used as a first input end of the conduction control circuit 3, and an output end of the transmission gate is connected with one end of a first resistor R1; one end of the first capacitor C1 is connected to the other end of the first resistor R1 and serves as the output end of the conduction control circuit 3, and the other end thereof is grounded; the first resistor R1 and the first capacitor C1 form a filter for filtering the signal output by the transmission gate, generating an output signal VTH _ H of the turn-on control circuit and inputting the output signal VTH _ H into the minimum turn-on time control circuit 4; the reverse input end of the first hysteresis comparator, which is used as the second input end of the conduction control circuit, is connected with the output end of the voltage sampling circuit 1, the positive input end of the first hysteresis comparator is connected with the bias voltage VB, and the output end of the first hysteresis comparator is connected with the control end of the transmission gate; the input end of the minimum on-time control circuit 4 is connected with the output end of the on-time control circuit 3, and the output end of the minimum on-time control circuit is used as the output end of the adjusting circuit; the reference voltage generation circuit 2 is configured to generate a reference voltage, which includes a first reference voltage VREF 1.
When the conduction time does not need to be adjusted, the minimum conduction time control end MOT is suspended; when the conduction time needs to be adjusted to be small, the minimum conduction time control end MOT is grounded; and when the conduction time needs to be adjusted to be increased, the minimum conduction time control end MOT is connected with the external resistance RS.
In the first embodiment, the first input terminal of the conduction control circuit 3 is directly connected to the second reference voltage VREF2 and the output terminal of the voltage sampling circuit 1, as shown in fig. 1. In the second embodiment, the voltage sampling circuit 1 is improved, so that the sampling voltage of the minimum on-time control terminal MOT is not directly input to the transmission gate, but is processed by the voltage sampling circuit and then connected to the first input terminal of the on-time control circuit 3, thereby avoiding an error caused by the influence of the off-chip resistor on the process, making the on-time more accurate, and increasing the reliability. As shown in fig. 3, the voltage sampling circuit 1 according to the second embodiment further includes a second capacitor C2, a second resistor R2, a third resistor R3, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a first operational amplifier OP1, a second operational amplifier OP2, and a first reference current source IREF1, wherein a drain of the first NMOS transistor MN1 is connected to the output terminal of the voltage sampling circuit 1 and the positive input terminal of the first operational amplifier OP1, and a gate and a source thereof are grounded; the second capacitor C2 is connected between the drain of the first NMOS transistor MN1 and the ground; the positive end of the first reference current source IREF1 is connected with a power supply voltage, and the negative end of the first reference current source IREF1 is connected with the positive input end of the first operational amplifier OP1 after passing through the second resistor R2; the gate of the second NMOS transistor MN2 is connected to the output terminal of the first operational amplifier OP1, the drain thereof is connected to the drain of the third NMOS transistor MN3 and to the power supply voltage, and the source thereof is connected to the source of the third NMOS transistor MN3, the inverting inputs of the second operational amplifier OP2 and the first operational amplifier OP1, and the first input of the on-state control circuit 3, and is grounded through the third resistor R3; the positive input end of the second operational amplifier OP2 is connected to a second reference voltage VREF2, the output end of the second operational amplifier OP2 is connected to the gate of the third NMOS transistor MN3, and the second reference voltage VREF2 is generated by the reference voltage generating circuit 2. The first NMOS transistor MN1 may also be a diode in some embodiments.
In the first embodiment, the bias voltage VB is externally given, as shown in fig. 1; in the second embodiment, the bias voltage VB is given to the third reference voltage VREF3 generated by the reference voltage generation circuit 2, as shown in fig. 3.
The minimum on-time control circuit 4 generates an adjusting signal for controlling the minimum on-time according to a signal output by the on-control circuit 3, and the adjusting signal comprises a charge-discharge circuit, a fourth NMOS transistor MN4, a third capacitor C3, a second hysteresis comparator, a third hysteresis comparator, a first nand gate, a second nand gate, a first inverter and a counter, wherein the charge-discharge circuit is of a cascode current mirror structure, an output end of the charge-discharge circuit is connected with an inverted input end of the second hysteresis comparator, a forward input end of the third hysteresis comparator and a drain electrode of the fourth NMOS transistor MN4 and is grounded through the third capacitor C3, and the charge-discharge circuit is used for controlling charging and discharging of the third capacitor C3; the positive input end of the second hysteresis comparator is used as the input end of the minimum on-time control circuit 4, the output end of the second hysteresis comparator is connected with the first input end of the second nand gate, the negative input end of the third hysteresis comparator is connected with a fourth reference voltage VREF0, the output end of the third hysteresis comparator is connected with the first input end of the first nand gate, and the fourth reference voltage VREF0 is generated by the reference voltage generation circuit 2; the second input end of the first nand gate is connected with the second input end of the second nand gate and is connected with an external enable signal ENA, the third input end of the first nand gate is connected with the output end of the second nand gate and the input end of the first inverter, the output end of the first nand gate is connected with the third input end of the second nand gate and the input end of the counter, the output end of the counter is used as the output end of the minimum on-time control circuit 4 to output an output signal MOT _ OUT of the adjusting circuit, the output signal MOT _ OUT of the adjusting circuit is fed back and connected with the grid of the fourth NMOS transistor MN4 on one hand, and is used for pulling down the voltage after the output becomes high, so that the hysteresis comparator stops working, and is used as a circuit output voltage signal to control a. The source electrode of the fourth NMOS transistor MN4 is grounded; the output end of the first phase inverter is connected with the control end of the charge and discharge circuit.
The first embodiment and the second embodiment provide two implementation forms of the minimum on-time control circuit 4, and the difference is the structure of the charge and discharge circuit, for example, the charge and discharge circuit in the first embodiment shown in fig. 1 includes a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, and a ninth PMOS transistor MP9, a gate of the ninth PMOS transistor MP9 is connected to an output terminal of the third operational amplifier OP3 in the reference voltage generating circuit 2, a drain thereof is connected to gates of the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, and the seventh NMOS transistor MN7, and a drain of the sixth NMOS transistor MN 3535 6, and a source thereof is connected to sources of the sixth PMOS transistor MP6, the seventh PMOS transistor MP7, and the eighth PMOS transistor MP8, and is connected to a source voltage; the drain electrode of the seventh NMOS transistor MN7 is connected to the drain electrodes of the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 and the gate electrodes of the sixth PMOS transistor MP6 and the eighth PMOS transistor MP8, and the source electrode thereof is connected to the source electrodes of the sixth NMOS transistor MN6 and the fifth NMOS transistor MN5 and grounded; the grid electrode of the seventh PMOS pipe MP7 is used as the control end of the charge-discharge circuit; the drain of the eighth PMOS transistor MP8 is connected to the drain of the fifth NMOS transistor MN5 and serves as the output terminal of the charge and discharge circuit.
As shown in fig. 3, the charge and discharge circuit in the second embodiment includes an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a fifteenth NMOS transistor MN15, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fifteenth PMOS transistor MP15, a ninth resistor R9, and a second reference current source IREF2, wherein a positive end of the second reference current source IREF2 is connected to a power supply voltage, and a negative end thereof is connected to one end of the ninth resistor R9, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a twelfth NMOS transistor MN12, and a thirteenth gate NMOS transistor MN 13; the grid electrode of the tenth NMOS transistor MN10 is connected to the grid electrodes of the eleventh NMOS transistor MN11, the fourteenth NMOS transistor MN14 and the fifteenth NMOS transistor MN15, the drain electrode of the eighth NMOS transistor MN8 and the other end of the ninth resistor R9, the drain electrode thereof is connected to the source electrode of the eighth NMOS transistor MN8, and the source electrode thereof is connected to the source electrodes of the eleventh NMOS transistor MN11, the fourteenth NMOS transistor MN14 and the fifteenth NMOS transistor MN15 and grounded; the source electrode of the ninth NMOS transistor MN9 is connected with the drain electrode of the eleventh NMOS transistor MN11, and the drain electrode of the ninth NMOS transistor MN9 is connected with the gate electrodes of the twelfth PMOS transistor MP12, the thirteenth PMOS transistor MP13, the fourteenth PMOS transistor MP14 and the drain electrode of the fourteenth PMOS transistor MP 14; the source electrode of the twelfth NMOS transistor MN12 is connected with the drain electrode of the fourteenth NMOS transistor MN14, and the drain electrode thereof is connected with the drain electrodes of the thirteenth PMOS transistor MP13 and the tenth PMOS transistor MP10 and the gate electrodes of the eleventh PMOS transistor MP11 and the fifteenth PMOS transistor MP 15; the source electrode of the thirteenth NMOS transistor MN13 is connected with the drain electrode of the fifteenth NMOS transistor MN15, and the drain electrode of the thirteenth NMOS transistor MN13 is connected with the drain electrode of the twelfth PMOS transistor MP12 and serves as the output end of the charge and discharge circuit; the drain electrode of the fifteenth PMOS tube MP15 is connected with the source electrode of the thirteenth PMOS tube MP13, and the source electrode of the fifteenth PMOS tube MP15 is connected with the source electrodes of the tenth PMOS tube MP10, the eleventh PMOS tube MP11 and the fourteenth PMOS tube MP14 and is connected with the power supply voltage; the gate of the tenth PMOS transistor MP10 is used as the control terminal of the charge and discharge circuit, and the drain of the eleventh PMOS transistor MP11 is connected to the source of the twelfth PMOS transistor MP 12.
The reference voltage generating circuit 2 is used for generating reference voltages and comprises a first reference voltage VREF1, a second reference voltage VREF2, a third reference voltage VREF3 and a fourth reference voltage VREF0, the reference voltage generating circuit 2 comprises a third operational amplifier OP3, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6, the positive input end of the third operational amplifier OP3 is connected with the reference voltage VBG, the negative input end of the third operational amplifier is connected with the drain electrode of the first PMOS transistor MP1 and grounded through the fourth resistor R4, and the output end of the third operational amplifier is connected with the gate electrodes of the first PMOS transistor MP1, the second PMOS transistor MP2 and the third PMOS transistor MP 3; the drain of the second PMOS transistor MP2 is connected to one end of the fifth resistor R5 and outputs the first reference voltage VREF1, and the source thereof is connected to the sources of the first PMOS transistor MP1 and the third PMOS transistor MP3 and to the power supply voltage; the drain of the third PMOS transistor MP3 is connected to one end of the sixth resistor R6 and outputs the second reference voltage VREF 2; the other end of the fifth resistor R5 and the other end of the sixth resistor R6 are grounded. The reference voltage generating circuit 2 may be designed according to a required reference voltage, and if a third reference voltage is required to be generated, the reference voltage generating circuit 2 further includes a fourth PMOS transistor MP4 and a seventh resistor R7, a gate of the fourth PMOS transistor MP4 is connected to the output of the third operational amplifier OP3, a source thereof is connected to the power voltage, a drain thereof is connected to one end of the seventh resistor R7 and outputs the third reference voltage VREF3, and the other end of the seventh resistor R7 is grounded. When the fourth reference voltage VREF0 needs to be generated, the reference voltage generating circuit 2 further includes a fifth PMOS transistor MP5 and an eighth resistor R8, a gate of the fifth PMOS transistor MP5 is connected to the output terminal of the third operational amplifier OP3, a source thereof is connected to the power voltage, a drain thereof is connected to one end of the eighth resistor R8 and outputs the fourth reference voltage VREF0, and the other end of the eighth resistor R8 is grounded.
For the first embodiment of the present invention, to more vividly describe the working principle of the present embodiment, different voltage values are set for the fourth reference voltage VREF0, the first reference voltage VREF1, the second reference voltage VREF2 and the bias voltage VB, which can be changed as required in a specific circuit.
When the turn-on time does not need to be adjusted, the minimum turn-on time control terminal MOT suspends float, and at this time, the fourth reference voltage VREF0 is 0.3V, the first reference voltage VREF1 is 2V, and the second reference voltage is
Figure BDA0001632574770000081
The voltage value of the second input end of the transmission gate, namely the second bias voltage VREF2, is output by the transmission gate, so that the third capacitor C3 is continuously charged and discharged back and forth between 0.3V and 0.75V, after passing through an SR trigger composed of a hysteresis comparator and an nand gate in a minimum on-time output circuit, an oscillation signal with fixed frequency is generated, and after the counter module counts the full time, a high level is output, so that a voltage control signal MOT _ OUT with fixed on-time is generated.
When the required on-time is small, the minimum on-time control terminal MOT is grounded AGND, and the serially connected sampling resistor R0 is smaller than the sixth resistor R6, so that the voltage is approximate to the sixth resistorR6 is shorted, and the second reference voltage is applied
Figure BDA0001632574770000082
About 0.4V, the fourth reference voltage VREF0 is 0.3V, the first reference voltage VREF1 is 2V, and the bias voltage VB is 2.5V, since the bias voltage VB is greater than the second reference voltage VREF2, the transmission gate outputs the voltage value of the second input terminal and the second reference voltage VREF2, similarly, the third capacitor C3 is charged and discharged at 0.3V-0.4V, so that the frequency of the generated oscillation signal becomes high, the counter can more quickly count the full output high level, and the voltage control signal MOT _ OUT becomes higher earlier.
When the conduction time is required to be increased, the resistance RS outside the MOT contact pin of the minimum conduction time control end is very large, the sampling resistance R0 is very small and negligible, and the second reference voltage is at the moment
Figure BDA0001632574770000091
The voltage of the transmission gate is about the power supply voltage AVDD, the fourth reference voltage VREF0 is 0.3V, the first reference voltage VREF1 is 2V, and the bias voltage VB is 2.5V, and since the bias voltage VB is smaller than V1, the transmission gate outputs the voltage value of the first input end and the first reference voltage VREF1, at this time, the third capacitor C3 is charged and discharged at 0.3V-2V, so that the frequency of the generated oscillation signal becomes low, the counter needs to fully output a high level for a longer time, and the voltage control signal MOT _ OUT becomes high later.
Since the external off-chip resistor and the internal resistor are different from each other due to process variations, when the minimum on-time control terminal MOT is connected to the off-chip resistor RS, the voltage variation is increased, thereby affecting the stability, so that the voltage sampling circuit is improved in the second embodiment, and the generated second reference voltage VREF2 is not affected by the process variations of the off-chip resistor. The working process of the second embodiment is as follows:
when the on-time does not need to be adjusted, the minimum on-time control terminal MOT floats float, in this embodiment, the fourth reference voltage VREF0 is set to be 0.3V, the first reference voltage VREF1 is set to be 0.75V, the second reference voltage VREF2 is set to be 0.4V, the third reference voltage VREF3 is set to be 2V, although the resistance is subject to process deviation of 20%, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7 and the eighth resistor R8 are all internal resistors, so that the change is mutually cancelled to ensure that the voltage of the fourth reference voltage VREF0 is constant, at this time, the output MOT _ INT voltage of the minimum on-time control circuit 4 is the power supply voltage AVDD, at this time, the output signal ct output by the first hysteretic comparator to the transmission gate control terminal is 0, the transmission gate outputs the first reference voltage VREF1, which makes the first capacitor C1 continuously go between 0.3V and 0.75V, and the nand gate trigger after the minimum on-time and the pass through the hysteresis comparator in the minimum on-time control circuit 4, therefore, an oscillating signal with fixed frequency is generated, and after the counter module counts the full time, a high level is output, so that a voltage control signal MOT _ OUT with fixed conduction time is generated.
When the required on-time is small, the minimum on-time control terminal MOT is grounded AGND, the voltage of the first input terminal REF _ MOT of the on-time control circuit 3 is the second reference voltage VREF2, the voltage of the output terminal MOT _ INT of the minimum on-time control circuit 4 is the low voltage AGND, the output signal ct output by the first hysteresis comparator to the transmission gate control terminal is 1, the voltage of the first input terminal REF _ MOT of the transmission gate output on-time control circuit 3 is 0.4V, and the first capacitor C1 is charged and discharged at 0.3V-0.4V, so that the frequency of the generated oscillation signal becomes high, the counter can quickly count full output high level, and the voltage control signal MOT _ OUT becomes high earlier.
When the required conduction time is increased, the resistance RS outside the minimum conduction time control end MOT contact piece is large, the sampling resistance R0 is small and negligible due to the fact that the resistance RS outside the chip is large, the voltage of the output end MOT _ INT of the voltage sampling circuit 1 is 2V at the moment, the voltage of the first input end REF _ MOT of the conduction control circuit 3 is guaranteed to be 2 through the first operational amplifier OP1, the signal ct is 1 at the moment, the transmission gate outputs the voltage of the first input end REF _ MOT of the conduction control circuit 3, the first capacitor C1 can be charged and discharged at 0.3V-2V at the moment, therefore, the frequency of generated oscillation signals is lowered, the counter needs to count for a longer time to fully output a high level, and the voltage control signal MOT _ OUT is changed later.
In summary, the reference voltage generating circuit 2 in the second embodiment generates the required reference voltage according to the applied reference voltage VBG, and includes the first reference voltage VREF1, the second reference voltage VREF2, the third reference voltage VREF3 and the fourth reference voltage VREF0, the first reference voltage VREF1 and the third reference voltage VREF3 are inputted to the turn-on control circuit 3, the second reference voltage VREF2 is inputted to the voltage sampling circuit 1, and the fourth reference voltage VREF0 is inputted to the minimum turn-on time output circuit 4; in the voltage sampling circuit 1, different signals are generated by controlling the minimum on-time control end MOT to be suspended or connected with a ground level or an off-chip resistor RS, and are respectively connected with a first input end REF _ MOT and a second input end MOT _ OUT of the on-time control circuit, so that a transmission gate in the on-time control circuit outputs different voltage values, and a signal VTH _ H is output after passing through a filter consisting of a first capacitor C1 and a first resistor R1; the minimum on-time output circuit 4 generates the voltage control signal MOT _ OUT of different on-times according to the feedback of the signal VTH _ H, the enable signal ENA, and its output signal.
Fig. 4 is a schematic diagram of an on-time output of an adjusting circuit for controlling an on-time according to a second embodiment. When the minimum on-time control terminal MOT is grounded AGND, the circuit outputs a high voltage at T1; when the minimum on-time control end MOT floats, the circuit outputs high voltage at T2; when the minimum on-time control terminal MOT is connected with the external resistor RS, the circuit outputs high voltage at T3. T1, T2, and T3 are the corresponding on-times of the minimum on-time control terminal MOT when they are connected differently. Conduction time
Figure BDA0001632574770000101
Wherein C is the size of the charge and discharge capacitor, V is the voltage drop across the capacitor, I is the charge and discharge current, and N is the counter digit.
The invention utilizes the conduction control module circuit to change the conduction time, and can accurately control the conduction time of the output voltage, thereby preventing the MOS tube from being switched on or off by mistake and ensuring the normal work of the circuit; a counter is added, so that the requirement of a circuit on time is met; and the influence of the process deviation of the resistor on the conduction time is solved, and the reliability is improved.
It is to be understood that the invention is not limited to the precise arrangements and components shown above. Various modifications and optimizations may be made to the order of the steps, details and operations of the methods and structures described above without departing from the scope of protection of the claims.

Claims (9)

1. An adjusting circuit for controlling the conduction time is characterized by comprising a voltage sampling circuit (1), a reference voltage generating circuit (2), a conduction control circuit (3) and a minimum conduction time control circuit (4),
the voltage sampling circuit (1) comprises a sampling resistor (R0), one end of the sampling resistor (R0) is used as a minimum on-time control end (MOT), and the other end of the sampling resistor (R0) is connected with the output end of the voltage sampling circuit (1);
the conduction control circuit (3) comprises a transmission gate, a first capacitor (C1), a first resistor (R1) and a first hysteresis comparator,
the first input end of the transmission gate is connected with a first reference voltage (VREF1), the second input end of the transmission gate is used as the first input end of the conduction control circuit (3), and the output end of the transmission gate is connected with one end of a first resistor (R1);
one end of a first capacitor (C1) is connected with the other end of the first resistor (R1) and is used as the output end of the conduction control circuit (3), and the other end of the first capacitor is grounded;
the reverse input end of the first hysteresis comparator is used as the second input end of the conduction control circuit and is connected with the output end of the voltage sampling circuit (1), the positive input end of the first hysteresis comparator is connected with a bias Voltage (VB), and the output end of the first hysteresis comparator is connected with the control end of the transmission gate;
the input end of the minimum on-time control circuit (4) is connected with the output end of the on-time control circuit (3), and the output end of the minimum on-time control circuit is used as the output end of the adjusting circuit;
the reference voltage generation circuit (2) is used for generating a reference voltage, and the reference voltage comprises a first reference voltage (VREF 1).
2. The on-time controlled adjustment circuit of claim 1, characterized in that the first input of the on-time control circuit (3) is connected to a second reference voltage (VREF2) and to the output of the voltage sampling circuit, the second reference voltage (VREF2) being generated by the reference voltage generation circuit (2).
3. The adjustment circuit for controlling conduction time according to claim 1, wherein the voltage sampling circuit (1) further comprises a second capacitor (C2), a second resistor (R2), a third resistor (R3), a first NMOS transistor (MN1), a second NMOS transistor (MN2), a third NMOS transistor (MN3), a first operational amplifier (OP1), a second operational amplifier (OP2), and a first reference current source (IREF1),
the drain electrode of the first NMOS tube (MN1) is connected with the output end of the voltage sampling circuit (1) and the positive input end of the first operational amplifier (OP1), and the grid electrode and the source electrode of the first NMOS tube are grounded;
the second capacitor (C2) is connected between the drain of the first NMOS transistor (MN1) and the ground;
the positive end of the first reference current source (IREF1) is connected with a power supply voltage, and the negative end of the first reference current source is connected with the positive input end of the first operational amplifier (OP1) after passing through the second resistor (R2);
the grid electrode of the second NMOS tube (MN2) is connected with the output end of the first operational amplifier (OP1), the drain electrode of the second NMOS tube (MN2) is connected with the drain electrode of the third NMOS tube (MN3) and is connected with the power supply voltage, and the source electrode of the second NMOS tube (MN3) is connected with the source electrode of the third NMOS tube (MN3), the reverse input ends of the second operational amplifier (OP2) and the first operational amplifier (OP1) and the first input end of the conduction control circuit (3) and is grounded after passing through the third resistor (R3);
the positive input end of the second operational amplifier (OP2) is connected with a second reference voltage (VREF2), the output end of the second operational amplifier is connected with the grid electrode of the third NMOS tube (MN3), and the second reference voltage (VREF2) is generated by the reference voltage generating circuit (2).
4. The on-time control adjustment circuit according to claim 2 or 3, wherein the reference voltage generation circuit (2) comprises a third operational amplifier (OP3), a first PMOS transistor (MP1), a second PMOS transistor (MP2), a third PMOS transistor (MP3), a fourth resistor (R4), a fifth resistor (R5), and a sixth resistor (R6),
the positive input end of the third operational amplifier (OP3) is connected with the reference Voltage (VBG), the reverse input end of the third operational amplifier is connected with the drain electrode of the first PMOS tube (MP1) and is grounded after passing through the fourth resistor (R4), and the output end of the third operational amplifier is connected with the grid electrodes of the first PMOS tube (MP1), the second PMOS tube (MP2) and the third PMOS tube (MP 3);
the drain electrode of the second PMOS tube (MP2) is connected with one end of a fifth resistor (R5) and outputs the first reference voltage (VREF1), and the source electrode of the second PMOS tube is connected with the source electrodes of the first PMOS tube (MP1) and the third PMOS tube (MP3) and is connected with the power supply voltage;
the drain electrode of the third PMOS tube (MP3) is connected with one end of a sixth resistor (R6) and outputs the second reference voltage (VREF 2); the other end of the fifth resistor (R5) and the other end of the sixth resistor (R6) are grounded.
5. The on-time control adjustment circuit of claim 4, wherein the bias Voltage (VB) is a third reference voltage (VREF3), the third reference voltage (VREF3) is generated by the reference voltage generation circuit (2), the reference voltage generation circuit (2) further comprises a fourth PMOS transistor (MP4) and a seventh resistor (R7), a gate of the fourth PMOS transistor (MP4) is connected to the output of the third operational amplifier (OP3), a source of the fourth PMOS transistor is connected to the power voltage, a drain of the fourth PMOS transistor is connected to one end of the seventh resistor (R7) and outputs the third reference voltage (VREF3), and the other end of the seventh resistor (R7) is grounded.
6. The on-time control adjustment circuit of claim 4, wherein the minimum on-time control circuit (4) comprises a charge/discharge circuit, a fourth NMOS transistor (MN4), a third capacitor (C3), a second hysteresis comparator, a third hysteresis comparator, a first NAND gate, a second NAND gate, a first inverter, and a counter,
the output end of the charge-discharge circuit is connected with the reverse input end of the second hysteresis comparator, the forward input end of the third hysteresis comparator and the drain electrode of the fourth NMOS tube (MN4), and is grounded after passing through a third capacitor (C3), and the charge-discharge circuit is used for controlling the charge and discharge of the third capacitor (C3);
the positive input end of the second hysteresis comparator is used as the input end of the minimum on-time control circuit (4), the output end of the second hysteresis comparator is connected with the first input end of the second NAND gate, the negative input end of the third hysteresis comparator is connected with a fourth reference voltage (VREF0), the output end of the third hysteresis comparator is connected with the first input end of the first NAND gate, and the fourth reference voltage (VREF0) is generated by the reference voltage generating circuit (2);
the second input end of the first NAND gate is connected with the second input end of the second NAND gate and is connected with an external enable signal (ENA), the third input end of the first NAND gate is connected with the output end of the second NAND gate and the input end of the first phase inverter, the output end of the first NAND gate is connected with the third input end of the second NAND gate and the input end of the counter, and the output end of the counter is used as the output end of the minimum on-time control circuit (4) and is connected with the grid electrode of a fourth NMOS tube (MN 4); the source electrode of the fourth NMOS tube (MN4) is grounded; the output end of the first inverter is connected with the control end of the charge and discharge circuit;
the reference voltage generating circuit (2) further comprises a fifth PMOS (P-channel metal oxide semiconductor) tube (MP5) and an eighth resistor (R8), wherein the grid electrode of the fifth PMOS tube (MP5) is connected with the output end of the third operational amplifier (OP3), the source electrode of the fifth PMOS tube is connected with the power supply voltage, the drain electrode of the fifth PMOS tube is connected with one end of the eighth resistor (R8) and outputs the fourth reference voltage (VREF0), and the other end of the eighth resistor (R8) is grounded.
7. The on-time control adjustment circuit of claim 6, wherein the charge/discharge circuit comprises a fifth NMOS transistor (MN5), a sixth NMOS transistor (MN6), a seventh NMOS transistor (MN7), a sixth PMOS transistor (MP6), a seventh PMOS transistor (MP7), an eighth PMOS transistor (MP8), and a ninth PMOS transistor (MP9),
the grid electrode of a ninth PMOS tube (MP9) is connected with the output end of a third operational amplifier (OP3) in the reference voltage generating circuit (2), the drain electrode of the ninth PMOS tube is connected with the grid electrodes of a fifth NMOS tube (MN5), a sixth NMOS tube (MN6) and a seventh NMOS tube (MN7) and the drain electrode of a sixth NMOS tube (MN6), and the source electrode of the ninth PMOS tube is connected with the source electrodes of a sixth PMOS tube (MP6), a seventh PMOS tube (MP7) and an eighth PMOS tube (MP8) and is connected with power supply voltage;
the drain electrode of the seventh NMOS transistor (MN7) is connected with the drain electrodes of the sixth PMOS transistor (MP6) and the seventh PMOS transistor (MP7) and the grid electrodes of the sixth PMOS transistor (MP6) and the eighth PMOS transistor (MP8), and the source electrode of the seventh NMOS transistor (MN7) is connected with the source electrodes of the sixth NMOS transistor (MN6) and the fifth NMOS transistor (MN5) and is grounded;
the grid electrode of a seventh PMOS tube (MP7) is used as the control end of the charge-discharge circuit; the drain electrode of the eighth PMOS tube (MP8) is connected with the drain electrode of the fifth NMOS tube (MN5) and is used as the output end of the charge and discharge circuit.
8. The on-time control adjustment circuit of claim 6, wherein the charge/discharge circuit comprises an eighth NMOS transistor (MN8), a ninth NMOS transistor (MN9), a tenth NMOS transistor (MN10), an eleventh NMOS transistor (MN11), a twelfth NMOS transistor (MN12), a thirteenth NMOS transistor (MN13), a fourteenth NMOS transistor (MN14), a fifteenth NMOS transistor (MN15), a tenth PMOS transistor (MP10), an eleventh PMOS transistor (MP11), a twelfth PMOS transistor (MP12), a thirteenth PMOS transistor (MP13), a fourteenth PMOS transistor (MP14), a fifteenth PMOS transistor (MP15), a ninth resistor (R9), and a second reference current source (IREF2),
the positive end of the second reference current source (IREF2) is connected with the power supply voltage, and the negative end of the second reference current source is connected with one end of the ninth resistor (R9), the eighth NMOS transistor (MN8), the ninth NMOS transistor (MN9), the twelfth NMOS transistor (MN12) and the gate of the thirteenth NMOS transistor (MN 13);
the grid electrode of the tenth NMOS tube (MN10) is connected with the grid electrodes of the eleventh NMOS tube (MN11), the fourteenth NMOS tube (MN14) and the fifteenth NMOS tube (MN15), the drain electrode of the eighth NMOS tube (MN8) and the other end of the ninth resistor (R9), the drain electrode of the tenth NMOS tube is connected with the source electrode of the eighth NMOS tube (MN8), and the source electrode of the tenth NMOS tube is connected with the source electrodes of the eleventh NMOS tube (MN11), the fourteenth NMOS tube (MN14) and the fifteenth NMOS tube (MN15) and grounded;
the source electrode of the ninth NMOS transistor (MN9) is connected with the drain electrode of the eleventh NMOS transistor (MN11), and the drain electrode of the ninth NMOS transistor is connected with the grid electrodes of the twelfth PMOS transistor (MP12), the thirteenth PMOS transistor (MP13), the fourteenth PMOS transistor (MP14) and the drain electrode of the fourteenth PMOS transistor (MP 14);
the source electrode of the twelfth NMOS tube (MN12) is connected with the drain electrode of the fourteenth NMOS tube (MN14), and the drain electrode of the twelfth NMOS tube is connected with the drain electrodes of the thirteenth PMOS tube (MP13) and the tenth PMOS tube (MP10) and the grid electrodes of the eleventh PMOS tube (MP11) and the fifteenth PMOS tube (MP 15);
the source electrode of the thirteenth NMOS tube (MN13) is connected with the drain electrode of the fifteenth NMOS tube (MN15), and the drain electrode of the thirteenth NMOS tube is connected with the drain electrode of the twelfth PMOS tube (MP12) and serves as the output end of the charge-discharge circuit;
the drain electrode of the fifteenth PMOS tube (MP15) is connected with the source electrode of the thirteenth PMOS tube (MP13), and the source electrode of the fifteenth PMOS tube (MP15) is connected with the source electrodes of the tenth PMOS tube (MP10), the eleventh PMOS tube (MP11) and the fourteenth PMOS tube (MP14) and is connected with the power supply voltage;
the grid electrode of the tenth PMOS tube (MP10) is used as the control end of the charge-discharge circuit, and the drain electrode of the eleventh PMOS tube (MP11) is connected with the source electrode of the twelfth PMOS tube (MP 12).
9. The on-time control adjustment circuit according to claim 1, wherein the minimum on-time control terminal (MOT) is floating when no adjustment of the on-time is required; when the conducting time needs to be adjusted to be small, the minimum conducting time control terminal (MOT) is grounded; and when the conduction time needs to be adjusted to be increased, the minimum conduction time control end (MOT) is connected with the external Resistance (RS) of the sheet.
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