CN108390550A - A kind of adjustment circuit of control turn-on time - Google Patents
A kind of adjustment circuit of control turn-on time Download PDFInfo
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- CN108390550A CN108390550A CN201810348235.8A CN201810348235A CN108390550A CN 108390550 A CN108390550 A CN 108390550A CN 201810348235 A CN201810348235 A CN 201810348235A CN 108390550 A CN108390550 A CN 108390550A
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- nmos tube
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
Abstract
A kind of adjustment circuit of control turn-on time, belongs to electronic circuit technology field.Reference voltage generating circuit is used to generate the reference voltage needed, by controlling its hanging minimum turn-on time control terminal or connection ground level or off chip resistor in voltage sampling circuit, generate different signal connection turn-on time control circuits, so that transmission gate in turn-on control circuit is exported different voltage values, the output signal of turn-on control circuit is generated after the filter formed using the first capacitance and first resistor；Minimum turn-on time output circuit generates the voltage control signal of different turn-on times according to the feedback of the output signal of the output signal of turn-on control circuit, external enable signal and minimum turn-on time output circuit.The present invention can in accurately controlling switch power supply switching tube turn-on and turn-off, and solve influence of the process deviation to turn-on time of resistance.
Description
Technical field
The invention belongs to electronic circuit technology field more particularly to a kind of adjustment circuits of control turn-on time.
Background technology
In power switch control circuit, due to the influence of technique and extraneous factor, power switch tube source-drain voltage or
Electric current often will appear burr or concussion, this can cause opening by mistake for power switch tube to open or accidentally turn off, designed to cause
Unstable, the less reliable of system.In order to solve this problem, it is usually added into turn-on time adjustment circuit in driving IC, uses
To reduce burr and concussion.Traditional way is the grid electricity for using the set time to be connected or adjust drive output in circuit
Resistance, but since different driving IC has different device technology and model, so the required time is also just different, this just makes to adopt
There is significant limitation with the method for set time；Secondly because outer connecting resistance variation with temperature is bigger, and easily
The method for being influenced by technique, therefore adjusting gate resistance, which can make to obtain result and ideal value, relatively large deviation.
Invention content
For above-mentioned conducting of traditional set time and adjustment drive output gate resistance there are the problem of, the present invention proposes
A kind of adjustment circuit of control turn-on time, turn-on time are adjusted by the different connections of minimum turn-on time control terminal MOT
Whole, to meet the turn-on time demand of different application, and builtin voltage will not be by resistance process deviation influence, to ensure
Accurate, the reliability height of turn-on time.
The technical scheme is that：
A kind of adjustment circuit of control turn-on time, including voltage sampling circuit 1, reference voltage generating circuit 2, conducting control
Circuit 3 processed and minimum turn-on time control circuit 4,
The voltage sampling circuit 1 includes sampling resistor R0, and one end of sampling resistor R0 is controlled as minimum turn-on time
MOT, the other end is held to connect the output end of the voltage sampling circuit 1；
The turn-on control circuit 3 includes transmission gate, the first capacitance C1, first resistor R1 and the first hysteresis comparator,
The first input end of transmission gate connects the first reference voltage V REF1, and the second input terminal is controlled as the conducting
The first input end of circuit 3, output end connect one end of first resistor R1；
One end of first capacitance C1 connects the other end of first resistor R1 and as the output of the turn-on control circuit 3
End, other end ground connection；
The reverse input end of first hysteresis comparator connects the electricity as the second input terminal of the turn-on control circuit
The output end of sample circuit 1, positive input is pressed to connect bias voltage VB, output end connects the control terminal of transmission gate；
The input terminal of the minimum turn-on time control circuit 4 connects the output end of the turn-on control circuit 3, output
Hold the output end as the adjustment circuit；
The reference voltage generating circuit 2 includes the first reference voltage for generating reference voltage, the reference voltage
VREF1。
Specifically, the first input end of the turn-on control circuit 3 connects the second reference voltage V REF2 and the voltage is adopted
The output end of sample circuit, the second reference voltage V REF2 are generated by the reference voltage generating circuit 2.
Specifically, the voltage sampling circuit 1 further includes the second capacitance C2, second resistance R2,3rd resistor R3, first
NMOS tube MN1, the second NMOS tube MN2, third NMOS tube MN3, the first operational amplifier OP1, second operational amplifier OP2 and
One reference current source IREF1,
The drain electrode of first NMOS tube MN1 connects the output end and the first operational amplifier OP1 of the voltage sampling circuit 1
Positive input, grid and source electrode ground connection；
Second capacitance C2 is connected between the drain electrode and ground of the first NMOS tube MN1；
The forward end of first reference current source IREF1 connects supply voltage, and negative end after second resistance R2 by connecting
The positive input of first operational amplifier OP1；
The grid of second NMOS tube MN2 connects the output end of the first operational amplifier OP1, drain electrode connection third NMOS tube
The drain electrode of MN3 simultaneously connects supply voltage, and source electrode connects source electrode, the second operational amplifier OP2 and first of third NMOS tube MN3
The first input end of the reverse input end of operational amplifier OP1 and the turn-on control circuit 3 simultaneously passes through the 3rd resistor
It is grounded after R3；
The positive input of second operational amplifier OP2 connects the second reference voltage V REF2, and output end connects third
The grid of NMOS tube MN3, the second reference voltage V REF2 are generated by the reference voltage generating circuit 2.
Specifically, the reference voltage generating circuit 2 includes third operational amplifier OP3, the first PMOS tube MP1, second
PMOS tube MP2, third PMOS tube MP3, the 4th resistance R4, the 5th resistance R5 and the 6th resistance R6,
The positive input of third operational amplifier OP3 connects reference voltage VBG, and reverse input end connects the first PMOS
The drain electrode of pipe MP1 and by being grounded after the 4th resistance R4, output end connect the first PMOS tube MP1, the second PMOS tube MP2 and the
The grid of three PMOS tube MP3；
One end of the 5th resistance R5 of drain electrode connection of second PMOS tube MP2 simultaneously exports the first reference voltage V REF1,
The source electrode of source electrode connection the first PMOS tube MP1 and third PMOS tube MP3 simultaneously connects supply voltage；
One end of the 6th resistance R6 of drain electrode connection of third PMOS tube MP3 simultaneously exports the second reference voltage V REF2；The
The other end of five resistance R5 and the other end ground connection of the 6th resistance R6.
Specifically, the bias voltage VB is third reference voltage V REF3, the third reference voltage V REF3 is by described
Reference voltage generating circuit 2 generates, and the reference voltage generating circuit 2 further includes the 4th PMOS tube MP4 and the 7th resistance R7, the
The output of the grid connection third operational amplifier OP3 of four PMOS tube MP4, source electrode connects supply voltage, drain electrode connection
One end of 7th resistance R7 simultaneously exports the third reference voltage V REF3, the other end ground connection of the 7th resistance R7.
Specifically, minimum turn-on time control circuit 4 include charge-discharge circuit, the 4th NMOS tube MN4, third capacitance C3,
Second hysteresis comparator, third hysteresis comparator, the first NAND gate, the second NAND gate, the first phase inverter and counter,
The output end of charge-discharge circuit connects the forward direction of the reverse input end of the second hysteresis comparator, third hysteresis comparator
The drain electrode of input terminal and the 4th NMOS tube MN4 and by being grounded after third capacitance C3, the charge-discharge circuit are described for controlling
The charging and discharging of third capacitance C3；
Input terminal of the positive input of second hysteresis comparator as the minimum turn-on time control circuit 4, it is defeated
Outlet connects the first input end of the second NAND gate, and the reverse input end of third hysteresis comparator connects the 4th reference voltage
VREF0, output end connect the first input end of the first NAND gate, and the 4th reference voltage V REF0 is by the reference voltage
Generation circuit 2 generates；
Second input terminal of the first NAND gate connects the second input terminal of the second NAND gate and connects external enable signal
ENA, third input terminal connect the second NAND gate output end and the first phase inverter input terminal, output end connection second with
The third input terminal of NOT gate and the input terminal of counter, the output end of counter is as the minimum turn-on time control circuit 4
Output end and connect the 4th NMOS tube MN4 grid；The source electrode of 4th NMOS tube MN4 is grounded；The output end of first phase inverter
Connect the control terminal of the charge-discharge circuit；
The reference voltage generating circuit 2 further includes the 5th PMOS tube MP5 and the 8th resistance R8, the 5th PMOS tube MP5's
Grid connects the output end of the third operational amplifier OP3, and source electrode connects supply voltage, the 8th resistance R8 of drain electrode connection
One end and export the 4th reference voltage V REF0, the other end of the 8th resistance R8 ground connection.
Specifically, the charge-discharge circuit includes the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the
Six PMOS tube MP6, the 7th PMOS tube MP7, the 8th PMOS tube MP8 and the 9th PMOS tube MP9,
The grid of 9th PMOS tube MP9 connects the output of third operational amplifier OP3 in the reference voltage generating circuit 2
End, drain electrode connect the grid and the 6th NMOS tube MN6 of the 5th NMOS tube MN5, the 6th NMOS tube MN6 and the 7th NMOS tube MN7
Drain electrode, source electrode connect the 6th PMOS tube MP6, the 7th PMOS tube MP7 and the 8th PMOS tube MP8 source electrode and connect power supply electricity
Pressure；
Drain electrode and the 6th PMOS of drain electrode connection the 6th PMOS tube MP6 and the 7th PMOS tube MP7 of 7th NMOS tube MN7
The grid of pipe MP6 and the 8th PMOS tube MP8, the source electrode of source electrode connection the 6th NMOS tube MN6 and the 5th NMOS tube MN5 simultaneously connect
Ground；
Control terminal of the grid of 7th PMOS tube MP7 as the charge-discharge circuit；The drain electrode of 8th PMOS tube MP8 connects
The drain electrode of 5th NMOS tube MN5 and as the output end of the charge-discharge circuit.
Specifically, the charge-discharge circuit include the 8th NMOS tube MN8, the 9th NMOS tube MN9, the tenth NMOS tube MN10,
11st NMOS tube MN11, the 12nd NMOS tube MN12, the 13rd NMOS tube MN13, the 14th NMOS tube MN14, the 15th
NMOS tube MN15, the tenth PMOS tube MP10, the 11st PMOS tube MP11, the 12nd PMOS tube MP12, the 13rd PMOS tube MP13,
14th PMOS tube MP14, the 15th PMOS tube MP15, the 9th resistance R9 and the second reference current source IREF2,
The forward end connection supply voltage of second reference current source IREF2, one end of the 9th resistance R9 of negative end connection,
The grid of 8th NMOS tube MN8, the 9th NMOS tube MN9, the 12nd NMOS tube MN12 and the 13rd NMOS tube MN13；
The grid of tenth NMOS tube MN10 connects the 11st NMOS tube MN11, the 14th NMOS tube MN14 and the 15th NMOS
The grid of pipe MN15 and the drain electrode of the 8th NMOS tube MN8 and the other end of the 9th resistance R9, drain electrode the 8th NMOS tube of connection
The source electrode of MN8, source electrode connect the source electrode of the 11st NMOS tube MN11, the 14th NMOS tube MN14 and the 15th NMOS tube MN15
And it is grounded；
The source electrode of 9th NMOS tube MN9 connects the drain electrode of the 11st NMOS tube MN11, drain electrode the 12nd PMOS tube of connection
The drain electrode of the grid and the 14th PMOS tube MP14 of MP12, the 13rd PMOS tube MP13 and the 14th PMOS tube MP14；
The source electrode of 12nd NMOS tube MN12 connects the drain electrode of the 14th NMOS tube MN14, the 13rd PMOS of drain electrode connection
The drain electrode of pipe MP13 and the tenth PMOS tube MP10 and the grid of the 11st PMOS tube MP11 and the 15th PMOS tube MP15；
The source electrode of 13rd NMOS tube MN13 connects the drain electrode of the 15th NMOS tube MN15, the 12nd PMOS of drain electrode connection
The drain electrode of pipe MP12 and as the output end of the charge-discharge circuit；
The source electrode of the 13rd PMOS tube MP13 of drain electrode connection of 15th PMOS tube MP15, source electrode connect the tenth PMOS tube
MP10, the 11st PMOS tube MP11 and the 14th PMOS tube MP14 source electrode and connect supply voltage；
Control terminal of the grid of tenth PMOS tube MP10 as the charge-discharge circuit, the drain electrode of the 11st PMOS tube MP11
Connect the source electrode of the 12nd PMOS tube MP12.
Specifically, when that need not adjust turn-on time, the minimum turn-on time control terminal MOT is hanging；When needing to adjust
Whole turn-on time becomes hour, the minimum turn-on time control terminal MOT ground connection；It is described when needing adjustment turn-on time to become larger
Minimum turn-on time control terminal MOT connection off chip resistors RS.
Beneficial effects of the present invention are：The present invention can accurately control the turn-on time of output voltage, to prevent switching tube
It is accidentally switched on or off, circuit is made to work normally；Counter is increased, requirement of the circuit to the time is met；And solves electricity
Influence of the process deviation of resistance to turn-on time, improves reliability.
Description of the drawings
Fig. 1 is a kind of structural schematic diagram of the adjustment circuit of control turn-on time in embodiment one.
Fig. 2 is a kind of structure diagram of the adjustment circuit of control turn-on time in the embodiment of the present invention two.
Fig. 3 is a kind of structural schematic diagram of the adjustment circuit of control turn-on time in the embodiment of the present invention two.
Fig. 4 is a kind of turn-on time output signal of the adjustment circuit of control turn-on time in the embodiment of the present invention two
Figure.
Specific implementation mode
In the following with reference to the drawings and specific embodiments, detailed description of the present invention technical solution.
A kind of adjustment circuit of control turn-on time provided by the invention, the signal of output end output is through overdrive circuit
The grid of connecting valve pipe afterwards, can in accurately controlling switch power supply circuit switching tube turn-on and turn-off, and designed electricity
Road makes reference voltage not depend on resistance variations, to solve influence of the process deviation of resistance to turn-on time.The present invention carries
A kind of adjustment circuit of the control turn-on time supplied includes voltage sampling circuit 1, reference voltage generating circuit 2, conducting control electricity
Road 3 and minimum turn-on time control circuit 4, the voltage sampling circuit 1 include sampling resistor R0, and one end of sampling resistor R0 is made
For minimum turn-on time control terminal MOT, the other end connects the output end of the voltage sampling circuit 1；The turn-on control circuit 3
Including transmission gate, the first capacitance C1, first resistor R1 and the first hysteresis comparator, the first input end of transmission gate connects the first base
Quasi- voltage VREF1, first input end of second input terminal as the turn-on control circuit 3, the first electricity of output end connection
Hinder one end of R1；One end of first capacitance C1 connects the other end of first resistor R1 and as the defeated of the turn-on control circuit 3
Outlet, other end ground connection；First resistor R1 and the first capacitance C1 composition filters produce after filtering the signal that transmission gate exports
The output signal VTH_H of raw turn-on control circuit is input in minimum turn-on time control circuit 4；First hysteresis comparator it is anti-
The output end of the voltage sampling circuit 1 is connected as the second input terminal of the turn-on control circuit to input terminal, it is positive
Input terminal connects bias voltage VB, and output end connects the control terminal of transmission gate；The minimum turn-on time control circuit 4 it is defeated
Enter the output end that end connects the turn-on control circuit 3, output end of the output end as the adjustment circuit；The benchmark electricity
Pressure generation circuit 2 includes the first reference voltage V REF1 for generating reference voltage, the reference voltage.
When that need not adjust turn-on time, the minimum turn-on time control terminal MOT is hanging；When needing to adjust conducting
Between become hour, the minimum turn-on time control terminal MOT ground connection；When needing adjustment turn-on time to become larger, the minimum conducting
Time control end MOT connection off chip resistors RS.
In embodiment one, the first input end of turn-on control circuit 3 is directly connected to the second reference voltage V REF2 and voltage
The output end of sample circuit 1, as shown in Figure 1.In embodiment two, voltage sampling circuit 1 is improved, makes minimum turn-on time control
The sampled voltage of end MOT processed is not directly inputted in transmission gate, first passes through to reconnect after voltage sampling circuit is handled and lead
The first input end of logical control circuit 3 makes turn-on time more so as to avoid the error for being influenced to bring by technique by off chip resistor
Add accurate, increase reliability.As shown in figure 3, the voltage sampling circuit 1 that embodiment two provides further includes the second capacitance C2, second
Resistance R2,3rd resistor R3, the first NMOS tube MN1, the second NMOS tube MN2, third NMOS tube MN3, the first operational amplifier
The drain electrode of OP1, second operational amplifier OP2 and the first reference current source IREF1, the first NMOS tube MN1 connect the voltage and adopt
The positive input of the output end of sample circuit 1 and the first operational amplifier OP1, grid and source electrode ground connection；Second capacitance C2 connects
Between the drain electrode and ground of the first NMOS tube MN1；The forward end of first reference current source IREF1 connects supply voltage, negative sense
Hold the positive input by connecting the first operational amplifier OP1 after second resistance R2；The grid connection the of second NMOS tube MN2
The output end of one operational amplifier OP1, the drain electrode of drain electrode connection third NMOS tube MN3 simultaneously connect supply voltage, and source electrode connects
Meet the source electrode of third NMOS tube MN3, the reverse input end of second operational amplifier OP2 and the first operational amplifier OP1 and institute
State the first input end of turn-on control circuit 3 and by being grounded after the 3rd resistor R3；The forward direction of second operational amplifier OP2
Input terminal connects the second reference voltage V REF2, and output end connects the grid of third NMOS tube MN3, second reference voltage
VREF2 is generated by the reference voltage generating circuit 2.The first NMOS tube MN1 can also be diode in some embodiments.
In embodiment one, bias voltage VB is that outside is given, as shown in Figure 1；In embodiment two, bias voltage VB is
The third reference voltage V REF3 that reference voltage generating circuit 2 generates is given, as shown in Figure 3.
Minimum turn-on time control circuit 4 generates the minimum turn-on time of control according to the signal that turn-on control circuit 3 exports
Adjustment signal, including charge-discharge circuit, the 4th NMOS tube MN4, third capacitance C3, the second hysteresis comparator, third sluggishness ratio
Compared with device, the first NAND gate, the second NAND gate, the first phase inverter and counter, charge-discharge circuit is common-source common-gate current mirror structure,
The output end of charge-discharge circuit connect the reverse input end of the second hysteresis comparator, third hysteresis comparator positive input and
The drain electrode of 4th NMOS tube MN4 and by being grounded after third capacitance C3, the charge-discharge circuit is for controlling the third capacitance
The charging and discharging of C3；Input of the positive input of second hysteresis comparator as the minimum turn-on time control circuit 4
End, output end connect the first input end of the second NAND gate, and the reverse input end of third hysteresis comparator connects the 4th benchmark
Voltage VREF0, output end connect the first input end of the first NAND gate, and the 4th reference voltage V REF0 is by the benchmark
Voltage generation circuit 2 generates；Second input terminal of the first NAND gate connects the second input terminal of the second NAND gate and connects outside
Enable signal ENA, third input terminal connect the input terminal of the output end and the first phase inverter of the second NAND gate, and output end connects
The third input terminal of the second NAND gate and the input terminal of counter are connect, the output end of counter is as the minimum turn-on time control
The output signal MOT_OUT of the output end output regulation circuit of circuit 4 processed, the output signal MOT_OUT of adjustment circuit is on the one hand
The grid for feeding back and connecting the 4th NMOS tube MN4 gets higher post-tensioning low-voltage for working as output, hysteresis comparator is made to be stopped,
On the other hand subsequent driving circuit is controlled as circuit output voltage signal, to control the on or off of power switch.
The source electrode of 4th NMOS tube MN4 is grounded；The output end of first phase inverter connects the control terminal of the charge-discharge circuit.
Embodiment one and embodiment two give two kinds of ways of realization of minimum turn-on time control circuit 4, difference lies in
The structure of charge-discharge circuit, the charge-discharge circuit in embodiment one as shown in Figure 1 include the 5th NMOS tube MN5, the 6th NMOS tube
MN6, the 7th NMOS tube MN7, the 6th PMOS tube MP6, the 7th PMOS tube MP7, the 8th PMOS tube MP8 and the 9th PMOS tube MP9, the
The grid of nine PMOS tube MP9 connects the output end of third operational amplifier OP3 in the reference voltage generating circuit 2, drain electrode
The drain electrode of the grid and the 6th NMOS tube MN6 of the 5th NMOS tube MN5, the 6th NMOS tube MN6 and the 7th NMOS tube MN7 is connected,
Source electrode connects the source electrode of the 6th PMOS tube MP6, the 7th PMOS tube MP7 and the 8th PMOS tube MP8 and connects supply voltage；7th
Drain electrode and the 6th PMOS tube MP6 and the 8th of drain electrode connection the 6th PMOS tube MP6 and the 7th PMOS tube MP7 of NMOS tube MN7
The grid of PMOS tube MP8, source electrode connect source electrode and the ground connection of the 6th NMOS tube MN6 and the 5th NMOS tube MN5；7th PMOS tube
Control terminal of the grid of MP7 as the charge-discharge circuit；The leakage of the 5th NMOS tube MN5 of drain electrode connection of 8th PMOS tube MP8
Pole and as the output end of the charge-discharge circuit.
As shown in figure 3, the charge-discharge circuit in embodiment two includes the 8th NMOS tube MN8, the 9th NMOS tube MN9, the tenth
NMOS tube MN10, the 11st NMOS tube MN11, the 12nd NMOS tube MN12, the 13rd NMOS tube MN13, the 14th NMOS tube
MN14, the 15th NMOS tube MN15, the tenth PMOS tube MP10, the 11st PMOS tube MP11, the 12nd PMOS tube MP12, the 13rd
PMOS tube MP13, the 14th PMOS tube MP14, the 15th PMOS tube MP15, the 9th resistance R9 and the second reference current source IREF2,
The forward end of second reference current source IREF2 connects supply voltage, and negative end connects one end of the 9th resistance R9, the 8th NMOS
The grid of pipe MN8, the 9th NMOS tube MN9, the 12nd NMOS tube MN12 and the 13rd NMOS tube MN13；Tenth NMOS tube MN10's
Grid connects the grid and the 8th NMOS of the 11st NMOS tube MN11, the 14th NMOS tube MN14 and the 15th NMOS tube MN15
The drain electrode of pipe MN8 and the other end of the 9th resistance R9, the source electrode of the 8th NMOS tube MN8 of drain electrode connection, source electrode connection the tenth
Source electrode and the ground connection of one NMOS tube MN11, the 14th NMOS tube MN14 and the 15th NMOS tube MN15；The source of 9th NMOS tube MN9
Pole connects the drain electrode of the 11st NMOS tube MN11, the 12nd PMOS tube MP12 of drain electrode connection, the 13rd PMOS tube MP13 and the
The drain electrode of the grid and the 14th PMOS tube MP14 of 14 PMOS tube MP14；The source electrode connection the tenth of 12nd NMOS tube MN12
The drain electrode of four NMOS tube MN14, the drain electrode and the 11st of the 13rd PMOS tube MP13 and the tenth PMOS tube MP10 of drain electrode connection
The grid of PMOS tube MP11 and the 15th PMOS tube MP15；The source electrode of 13rd NMOS tube MN13 connects the 15th NMOS tube MN15
Drain electrode, drain electrode connection the 12nd PMOS tube MP12 drain electrode and as the output end of the charge-discharge circuit；15th
The source electrode of the 13rd PMOS tube MP13 of drain electrode connection of PMOS tube MP15, source electrode connect the tenth PMOS tube MP10, the 11st
The source electrode of PMOS tube MP11 and the 14th PMOS tube MP14 simultaneously connect supply voltage；Described in the grid of tenth PMOS tube MP10 is used as
The control terminal of charge-discharge circuit, the source electrode of the 12nd PMOS tube MP12 of drain electrode connection of the 11st PMOS tube MP11.
Reference voltage generating circuit 2 is for generating reference voltage, including the first reference voltage V REF1, the second reference voltage
VREF2, third reference voltage V REF3 and the 4th reference voltage V REF0, reference voltage generating circuit 2 include third operation amplifier
Device OP3, the first PMOS tube MP1, the second PMOS tube MP2, third PMOS tube MP3, the 4th resistance R4, the electricity of the 5th resistance R5 and the 6th
R6 is hindered, the positive input of third operational amplifier OP3 connects reference voltage VBG, and reverse input end connects the first PMOS tube
The drain electrode of MP1 and by being grounded after the 4th resistance R4, output end connect the first PMOS tube MP1, the second PMOS tube MP2 and third
The grid of PMOS tube MP3；One end of the 5th resistance R5 of drain electrode connection of second PMOS tube MP2 simultaneously exports first reference voltage
VREF1, the source electrode of source electrode connection the first PMOS tube MP1 and third PMOS tube MP3 simultaneously connect supply voltage；Third PMOS tube
One end of the 6th resistance R6 of drain electrode connection of MP3 simultaneously exports the second reference voltage V REF2；The other end of 5th resistance R5 and
The other end of 6th resistance R6 is grounded.Reference voltage design basis voltage generation circuit 2 that can be as needed, such as needs generation
Reference voltage generating circuit 2 further includes the 4th PMOS tube MP4 and the 7th resistance R7 when three reference voltages, the 4th PMOS tube MP4's
Grid connects the output of third operational amplifier OP3, and source electrode connects supply voltage, and drain electrode connects the one of the 7th resistance R7
Hold and export the third reference voltage V REF3, the other end ground connection of the 7th resistance R7.When need generate the 4th reference voltage
When VREF0, reference voltage generating circuit 2 further includes the 5th PMOS tube MP5 and the 8th resistance R8, the grid of the 5th PMOS tube MP5
The output end of the third operational amplifier OP3 is connected, source electrode connects supply voltage, and drain electrode connects the one of the 8th resistance R8
Hold and export the 4th reference voltage V REF0, the other end ground connection of the 8th resistance R8.
For the first embodiment of the invention the 4th reference voltage is given for more pictute the present embodiment operation principle
Different voltages value is arranged in VREF0, the first reference voltage V REF1, the second reference voltage V REF2 and bias voltage VB, in specific electricity
Lu Zhongke is changed according to demand.
When that need not adjust turn-on time, the hanging float of minimum turn-on time control terminal MOT, the 4th benchmark is electric at this time
Pressure VREF0 is 0.3V, the first reference voltage V REF1 is 2V, the second reference voltageFor 0.75V, biased electrical
Pressure VB is 2.5V, although resistance can be by process deviation 20%, the 4th resistance R4 and the 6th resistance R6 are internal resistance, so
Variation, which can cancel out each other, ensures that the second reference voltage V REF2 is unaffected, and the second reference voltage V REF2 is less than bias voltage at this time
VB, so transmission gate exports voltage value i.e. the second bias voltage VREF2 of its second input terminal, this can make third capacitance C3 exist
Continuous charge and discharge back and forth between 0.3V-0.75V, by minimum turn-on time output circuit by hysteresis comparator and NAND gate group
At set-reset flip-floop after, to generate the oscillator signal of a fixed frequency, after counter module meter expire the time, output is high electric
It is flat, to generate the voltage control signal MOT_OUT of fixed turn-on time.
When needing turn-on time to become small, minimum turn-on time control terminal MOT is grounded AGND, due to the sampling resistor of concatenation
R0 compares the 6th resistance R6 very littles, so the 6th resistance R6 of approximation is shorted, the second reference voltage at this timeAbout
0.4V, the 4th reference voltage V REF0 are 0.3V, the first reference voltage V REF1 is 2V, bias voltage VB is 2.5V, due to biasing
Voltage VB is more than the second reference voltage V REF2, so transmission gate exports the voltage value and the second reference voltage of its second input terminal
VREF2, similarly third capacitance C3 can be in 0.3V-0.4V charge and discharge, to make the oscillation signal frequency of generation get higher, counter meeting
Meter completely exports high level faster, and voltage control signal MOT_OUT is made to get higher earlier.
When needing turn-on time to become larger, minimum turn-on time control terminal MOT contact pin external resistance RS is adopted since RS is very big
Sample resistance R0 very littles are negligible, at this time the second reference voltageAbout supply voltage AVDD, the
Four reference voltage V REF0 are 0.3V, the first reference voltage V REF1 is 2V, bias voltage VB is 2.5V, since bias voltage VB is small
In V1, so transmission gate exports the voltage value and the first reference voltage V REF1 of its first input end, third capacitance C3 can be at this time
0.3V-2V charge and discharge, to make the oscillation signal frequency of generation be lower, the meter that counter takes longer for completely exports high electricity
It is flat, so that voltage control signal MOT_OUT is got higher later.
Since external off chip resistor is different by process deviation from internal resistance, so when minimum turn-on time control terminal
When MOT contact pin external resistance RS, generates voltage change and increase, to influence stability, improved so being added in embodiment two
Voltage sampling circuit makes generated second reference voltage V REF2 not influenced by off chip resistor process deviation.Embodiment two
The course of work is：
When that need not adjust turn-on time, minimum turn-on time control terminal MOT hanging float are arranged in the present embodiment
4th reference voltage V REF0 is 0.3V, the first reference voltage V REF1 is 0.75V, the second reference voltage V REF2 is 0.4V, third
Reference voltage V REF3 is 2V, although resistance can be by process deviation 20%, the 4th resistance R4, the 5th resistance R5, the 6th resistance
R6, the 7th resistance R7 and the 8th resistance R8 are internal resistance, so variation, which can cancel out each other, ensures the 4th reference voltage V REF0
Voltage constant, the output end MOT_INT voltage swings of minimum turn-on time control circuit 4 are supply voltage AVDD at this time, at this time
It is 0 that first hysteresis comparator, which is exported to the output signal ct of transmission gate control terminal, and transmission gate exports the first reference voltage V REF1,
This can make the first capacitance C1 continuous charge and discharge back and forth between 0.3V-0.75V, by minimum turn-on time control circuit 4
After hysteresis comparator and the set-reset flip-floop being made of NAND gate, to generate the oscillator signal of a fixed frequency, work as counter
After module meter expires the time, high level is exported, to generate the voltage control signal MOT_OUT of fixed turn-on time.
When needing turn-on time to become small, minimum turn-on time control terminal MOT is grounded AGND, at this time turn-on control circuit 3
First input end REF_MOT voltage swings be the second reference voltage V REF2, minimum turn-on time control circuit 4 is defeated at this time
Outlet MOT_INT voltage swings are low-voltage AGND, and the first hysteresis comparator is exported to the output letter of transmission gate control terminal at this time
Number ct is 1, and the first input end REF_MOT voltages that transmission gate exports turn-on control circuit 3 are 0.4V, and the first capacitance C1 can be
0.3V-0.4V charge and discharge, to make the oscillation signal frequency of generation get higher, counter can be counted and completely export high level faster, make
Voltage control signal MOT_OUT is got higher earlier.
When needing turn-on time to become larger, minimum turn-on time control terminal MOT contact pin external resistance RS, due to off chip resistor RS
Very big, sampling resistor R0 very littles are negligible, and the output end MOT_INT voltage swings of voltage sampling circuit 1 are 2V at this time, are led to
It is 2 to cross the first operational amplifier OP1 and ensure that 3 first input end REF_MOT voltages of turn-on control circuit also, and ct signals are at this time
1, transmission gate exports the first input end REF_MOT voltages of turn-on control circuit 3, and the first capacitance C1 can be filled in 0.3V-2V at this time
Electric discharge, to make the oscillation signal frequency of generation be lower, the meter that counter takes longer for completely exports high level, makes voltage control
Signal MOT_OUT processed is got higher later.
In conclusion reference voltage generating circuit 2 generates the base needed according to additional reference voltage V BG in embodiment two
Quasi- voltage, including the first reference voltage V REF1, the second reference voltage V REF2, third reference voltage V REF3 and the 4th benchmark electricity
Pressure VREF0, the first reference voltage V REF1 and third reference voltage V REF3 are input in turn-on control circuit 3, the second benchmark electricity
Pressure VREF2 is input in voltage sampling circuit 1, and the 4th reference voltage V REF0 is input in minimum turn-on time output circuit 4；
By controlling minimum turn-on time control terminal MOT hanging or connection ground level or off chip resistor RS, production in voltage sampling circuit 1
Raw different signal is separately connected the first input end REF_MOT and the second input terminal MOT_OUT of turn-on time control circuit, makes
Transmission gate exports different voltage values in turn-on control circuit, using the filter of the first capacitance C1 and first resistor R1 compositions
Output signal VTH_H afterwards；Minimum turn-on time output circuit 4 is according to signal VTH_H, enable signal ENA and its output signal
Feedback generates the voltage control signal MOT_OUT of different turn-on times.
Fig. 4 is that a kind of turn-on time of the adjustment circuit of control turn-on time in embodiment two exports schematic diagram.When most
When small turn-on time control terminal MOT ground connection AGND, circuit output HIGH voltage in T1；When minimum turn-on time control terminal MOT is outstanding
When empty float, circuit output HIGH voltage in T2；As minimum turn-on time control terminal MOT contact pin external resistance RS, circuit is in T3
When output HIGH voltage.T1, T2 and T3 corresponding turn-on time when being minimum turn-on time control terminal MOT difference connections.It leads
The logical timeWherein C is the size of charge and discharge capacitance, and V is the pressure drop of capacitance both ends, and I is charging and discharging currents size, N
For number of counter bits.
The present invention changes turn-on time using conducting control module circuit, when can accurately control the conducting of output voltage
Between, to prevent metal-oxide-semiconductor to be accidentally switched on or off, circuit is made to work normally；Counter is increased, circuit is met and the time is wanted
It asks；And influence of the process deviation to turn-on time for solving resistance, improves reliability.
It is understood that the present invention is not limited to the accurate configuration being illustrated above and components.Claims are not being departed from
Protection domain on the basis of, can be to method as described above and structure the step of sequence, details and operation make various modifications and
Optimization.
Claims (9)
1. a kind of adjustment circuit of control turn-on time, which is characterized in that generated including voltage sampling circuit (1), reference voltage
Circuit (2), turn-on control circuit (3) and minimum turn-on time control circuit (4),
The voltage sampling circuit (1) includes sampling resistor (R0), and one end of sampling resistor (R0) is as minimum turn-on time control
End (MOT) processed, the other end connect the output end of the voltage sampling circuit (1)；
The turn-on control circuit (3) includes transmission gate, the first capacitance (C1), first resistor (R1) and the first hysteresis comparator,
The first input end of transmission gate connects the first reference voltage (VREF1), and the second input terminal controls electricity as the conducting
The first input end on road (3), output end connect one end of first resistor (R1)；
One end of first capacitance (C1) connects the other end of first resistor (R1) and as the output of the turn-on control circuit (3)
End, other end ground connection；
The reverse input end of first hysteresis comparator connects the voltage as the second input terminal of the turn-on control circuit and adopts
The output end of sample circuit (1), positive input connect bias voltage (VB), and output end connects the control terminal of transmission gate；
The input terminal of the minimum turn-on time control circuit (4) connects the output end of the turn-on control circuit (3), output
Hold the output end as the adjustment circuit；
The reference voltage generating circuit (2) includes the first reference voltage for generating reference voltage, the reference voltage
(VREF1)。
2. the adjustment circuit of control turn-on time according to claim 1, which is characterized in that the turn-on control circuit
(3) first input end connects the output end of the second reference voltage (VREF2) and the voltage sampling circuit, second benchmark
Voltage (VREF2) is generated by the reference voltage generating circuit (2).
3. the adjustment circuit of control turn-on time according to claim 1, which is characterized in that the voltage sampling circuit
(1) further include the second capacitance (C2), second resistance (R2), 3rd resistor (R3), the first NMOS tube (MN1), the second NMOS tube
(MN2), third NMOS tube (MN3), the first operational amplifier (OP1), second operational amplifier (OP2) and the first reference current source
(IREF1),
The drain electrode of first NMOS tube (MN1) connects the output end and the first operational amplifier (OP1) of the voltage sampling circuit (1)
Positive input, grid and source electrode ground connection；
Second capacitance (C2) is connected between the drain electrode and ground of the first NMOS tube (MN1)；
The forward end of first reference current source (IREF1) connects supply voltage, and negative end is connected afterwards by second resistance (R2)
The positive input of first operational amplifier (OP1)；
The grid of second NMOS tube (MN2) connects the output end of the first operational amplifier (OP1), drain electrode connection third NMOS tube
(MN3) drain electrode simultaneously connects supply voltage, and source electrode connects the source electrode of third NMOS tube (MN3), second operational amplifier (OP2)
With the reverse input end of the first operational amplifier (OP1) and the first input end of the turn-on control circuit (3) and pass through institute
3rd resistor (R3) is stated to be grounded afterwards；
The positive input of second operational amplifier (OP2) connects the second reference voltage (VREF2), and output end connects third
The grid of NMOS tube (MN3), second reference voltage (VREF2) are generated by the reference voltage generating circuit (2).
4. the adjustment circuit of control turn-on time according to claim 2 or 3, which is characterized in that the reference voltage production
Raw circuit (2) includes third operational amplifier (OP3), the first PMOS tube (MP1), the second PMOS tube (MP2), third PMOS tube
(MP3), the 4th resistance (R4), the 5th resistance (R5) and the 6th resistance (R6),
The positive input connection reference voltage (VBG) of third operational amplifier (OP3), reverse input end connect the first PMOS
It manages the drain electrode of (MP1) and is grounded afterwards by the 4th resistance (R4), output end connects the first PMOS tube (MP1), the second PMOS tube
(MP2) and the grid of third PMOS tube (MP3)；
The drain electrode of second PMOS tube (MP2) connects one end of the 5th resistance (R5) and exports first reference voltage (VREF1),
Its source electrode connects the source electrode of the first PMOS tube (MP1) and third PMOS tube (MP3) and connects supply voltage；
The drain electrode of third PMOS tube (MP3) connects one end of the 6th resistance (R6) and exports second reference voltage (VREF2)；
The other end of 5th resistance (R5) and the other end ground connection of the 6th resistance (R6).
5. the adjustment circuit of control turn-on time according to claim 4, which is characterized in that the bias voltage (VB) is
Third reference voltage (VREF3), the third reference voltage (VREF3) is generated by the reference voltage generating circuit (2), described
Reference voltage generating circuit (2) further includes the 4th PMOS tube (MP4) and the 7th resistance (R7), the grid of the 4th PMOS tube (MP4)
The output of third operational amplifier (OP3) is connected, source electrode connects supply voltage, and drain electrode connects the one of the 7th resistance (R7)
Hold and export the third reference voltage (VREF3), the other end ground connection of the 7th resistance (R7).
6. the adjustment circuit of control turn-on time according to claim 1, which is characterized in that minimum turn-on time control electricity
Road (4) includes that charge-discharge circuit, the 4th NMOS tube (MN4), third capacitance (C3), the second hysteresis comparator, third sluggishness compare
Device, the first NAND gate, the second NAND gate, the first phase inverter and counter,
The output end of charge-discharge circuit connects the positive input of the reverse input end of the second hysteresis comparator, third hysteresis comparator
The drain electrode of end and the 4th NMOS tube (MN4) is simultaneously grounded by third capacitance (C3) afterwards, and the charge-discharge circuit is described for controlling
The charging and discharging of third capacitance (C3)；
Input terminal of the positive input of second hysteresis comparator as the minimum turn-on time control circuit (4), output
The first input end of the second NAND gate of end connection, the reverse input end of third hysteresis comparator connect the 4th reference voltage
(VREF0), output end connects the first input end of the first NAND gate, and the 4th reference voltage (VREF0) is by the benchmark
Voltage generation circuit (2) generates；
Second input terminal of the first NAND gate connects the second input terminal of the second NAND gate and connects external enable signal (ENA),
Its third input terminal connects the input terminal of the output end and the first phase inverter of the second NAND gate, and output end connects the second NAND gate
Third input terminal and counter input terminal, the output end of counter is as the minimum turn-on time control circuit (4)
Output end and the grid for connecting the 4th NMOS tube (MN4)；The source electrode of 4th NMOS tube (MN4) is grounded；The output of first phase inverter
End connects the control terminal of the charge-discharge circuit；
The reference voltage generating circuit (2) further includes the 5th PMOS tube (MP5) and the 8th resistance (R8), the 5th PMOS tube
(MP5) grid connects the output end of the third operational amplifier (OP3), and source electrode connects supply voltage, drain electrode connection
One end of 8th resistance (R8) simultaneously exports the 4th reference voltage (VREF0), the other end ground connection of the 8th resistance (R8).
7. the adjustment circuit of control turn-on time according to claim 6, which is characterized in that the charge-discharge circuit includes
5th NMOS tube (MN5), the 6th NMOS tube (MN6), the 7th NMOS tube (MN7), the 6th PMOS tube (MP6), the 7th PMOS tube
(MP7), the 8th PMOS tube (MP8) and the 9th PMOS tube (MP9),
Third operational amplifier (OP3) is defeated in the grid connection reference voltage generating circuit (2) of 9th PMOS tube (MP9)
Outlet, drain electrode connect the grid and the 6th of the 5th NMOS tube (MN5), the 6th NMOS tube (MN6) and the 7th NMOS tube (MN7)
The drain electrode of NMOS tube (MN6), source electrode connect the 6th PMOS tube (MP6), the 7th PMOS tube (MP7) and the 8th PMOS tube (MP8)
Source electrode and connect supply voltage；
The drain electrode of 7th NMOS tube (MN7) connects the drain electrode and the 6th of the 6th PMOS tube (MP6) and the 7th PMOS tube (MP7)
The grid of PMOS tube (MP6) and the 8th PMOS tube (MP8), source electrode connect the 6th NMOS tube (MN6) and the 5th NMOS tube (MN5)
Source electrode and ground connection；
Control terminal of the grid of 7th PMOS tube (MP7) as the charge-discharge circuit；The drain electrode of 8th PMOS tube (MP8) connects
The drain electrode of 5th NMOS tube (MN5) and as the output end of the charge-discharge circuit.
8. the adjustment circuit of control turn-on time according to claim 6, which is characterized in that the charge-discharge circuit includes
8th NMOS tube (MN8), the 9th NMOS tube (MN9), the tenth NMOS tube (MN10), the 11st NMOS tube (MN11), the 12nd
NMOS tube (MN12), the 13rd NMOS tube (MN13), the 14th NMOS tube (MN14), the 15th NMOS tube (MN15), the tenth
PMOS tube (MP10), the 11st PMOS tube (MP11), the 12nd PMOS tube (MP12), the 13rd PMOS tube (MP13), the 14th
PMOS tube (MP14), the 15th PMOS tube (MP15), the 9th resistance (R9) and the second reference current source (IREF2),
The forward end connection supply voltage of second reference current source (IREF2), one end of negative end the 9th resistance (R9) of connection,
The grid of 8th NMOS tube (MN8), the 9th NMOS tube (MN9), the 12nd NMOS tube (MN12) and the 13rd NMOS tube (MN13)；
The grid of tenth NMOS tube (MN10) connects the 11st NMOS tube (MN11), the 14th NMOS tube (MN14) and the 15th
The other end of the drain electrode and the 9th resistance (R9) of the grid of NMOS tube (MN15) and the 8th NMOS tube (MN8), drain electrode connection
The source electrode of 8th NMOS tube (MN8), source electrode connect the 11st NMOS tube (MN11), the 14th NMOS tube (MN14) and the 15th
The source electrode of NMOS tube (MN15) and ground connection；
The source electrode of 9th NMOS tube (MN9) connects the drain electrode of the 11st NMOS tube (MN11), drain electrode the 12nd PMOS tube of connection
(MP12), the 13rd PMOS tube (MP13) and the grid of the 14th PMOS tube (MP14) and the leakage of the 14th PMOS tube (MP14)
Pole；
The source electrode of 12nd NMOS tube (MN12) connects the drain electrode of the 14th NMOS tube (MN14), the 13rd PMOS of drain electrode connection
Manage drain electrode and the 11st PMOS tube (MP11) and the 15th PMOS tube (MP15) of (MP13) and the tenth PMOS tube (MP10)
Grid；
The source electrode of 13rd NMOS tube (MN13) connects the drain electrode of the 15th NMOS tube (MN15), the 12nd PMOS of drain electrode connection
Manage the drain electrode of (MP12) and as the output end of the charge-discharge circuit；
The drain electrode of 15th PMOS tube (MP15) connects the source electrode of the 13rd PMOS tube (MP13), and source electrode connects the tenth PMOS tube
(MP10), the source electrode of the 11st PMOS tube (MP11) and the 14th PMOS tube (MP14) and supply voltage is connected；
Control terminal of the grid of tenth PMOS tube (MP10) as the charge-discharge circuit, the drain electrode of the 11st PMOS tube (MP11)
Connect the source electrode of the 12nd PMOS tube (MP12).
9. the adjustment circuit of control turn-on time according to claim 1, which is characterized in that when conducting need not be adjusted
Between when, the minimum turn-on time control terminal (MOT) is hanging；When needing adjustment turn-on time to become small, when the minimum is connected
Between control terminal (MOT) be grounded；When needing adjustment turn-on time to become larger, described minimum turn-on time control terminal (MOT) connection sheet
External resistance (RS).
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810348235.8A CN108390550B (en) | 2018-04-18 | 2018-04-18 | Adjusting circuit for controlling conduction time |
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|---|---|---|---|
| CN201810348235.8A CN108390550B (en) | 2018-04-18 | 2018-04-18 | Adjusting circuit for controlling conduction time |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113381774A (en) * | 2020-03-09 | 2021-09-10 | 瑞昱半导体股份有限公司 | Transmitting circuit and working method thereof |
| CN113708638A (en) * | 2021-08-20 | 2021-11-26 | 深圳市必易微电子股份有限公司 | Synchronous rectification control circuit, control method and flyback switching power supply |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102498653A (en) * | 2009-07-22 | 2012-06-13 | 沃福森微电子股份有限公司 | Improvements in dc-dc converters |
| CN102868297A (en) * | 2012-09-20 | 2013-01-09 | 电子科技大学 | Deadline-fixed PFM (pulse frequency modulation) mode switching power supply controller |
| CN203466720U (en) * | 2013-09-02 | 2014-03-05 | 南京埃科孚电子科技有限公司 | Circuit reducing opening time in current control type switching regulating system |
-
2018
- 2018-04-18 CN CN201810348235.8A patent/CN108390550B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102498653A (en) * | 2009-07-22 | 2012-06-13 | 沃福森微电子股份有限公司 | Improvements in dc-dc converters |
| CN102868297A (en) * | 2012-09-20 | 2013-01-09 | 电子科技大学 | Deadline-fixed PFM (pulse frequency modulation) mode switching power supply controller |
| CN203466720U (en) * | 2013-09-02 | 2014-03-05 | 南京埃科孚电子科技有限公司 | Circuit reducing opening time in current control type switching regulating system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113381774A (en) * | 2020-03-09 | 2021-09-10 | 瑞昱半导体股份有限公司 | Transmitting circuit and working method thereof |
| CN113708638A (en) * | 2021-08-20 | 2021-11-26 | 深圳市必易微电子股份有限公司 | Synchronous rectification control circuit, control method and flyback switching power supply |
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