CN113381774B

CN113381774B - Transmitting circuit and working method thereof

Info

Publication number: CN113381774B
Application number: CN202010156360.6A
Authority: CN
Inventors: 宋亚轩
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2020-03-09
Filing date: 2020-03-09
Publication date: 2022-07-19
Anticipated expiration: 2040-03-09
Also published as: CN113381774A

Abstract

A transmitting circuit comprises a slew rate control circuit, a hysteresis circuit, a logic control circuit and an amplifying circuit. The slew rate control circuit is used for controlling the slew rate of the input signal so as to generate a first output signal. The hysteresis circuit is used for generating a first control signal according to the first output signal. The logic control circuit is used for generating a second control signal and a third control signal according to the input signal and the first control signal. The amplifying circuit is used for generating a second output signal according to the first output signal, the second control signal and the third control signal.

Description

Transmitting circuit and working method thereof

Technical Field

The embodiments described herein relate to a circuit technology, and more particularly, to a transmitter circuit and a method for operating the same.

Background

With the development of technology, applications requiring signal/data transmission functions are increasing. Any two electronic devices can perform signal/data transmission through interfaces of the same protocol or the same technology. For example, an electronic device can be connected to a Type-C interface of another electronic device through a Type-C interface for signal/data transmission.

Disclosure of Invention

Some embodiments of the invention relate to a transmit circuit. The transmitting circuit comprises a slew rate control circuit, a hysteresis circuit, a logic control circuit and an amplifying circuit. The slew rate control circuit is used for controlling the slew rate of the input signal to generate a first output signal. The hysteresis circuit is used for generating a first control signal according to the first output signal. The logic control circuit is used for generating a second control signal and a third control signal according to the input signal and the first control signal. The amplifying circuit is used for generating a second output signal according to the first output signal, the second control signal and the third control signal.

Some embodiments of the invention relate to a method of operation for a transmit circuit. The working method comprises the following steps: controlling the slew rate of the input signal through a slew rate control circuit to generate a first output signal; generating a first control signal according to the first output signal through a hysteresis circuit; generating a second control signal and a third control signal according to the input signal and the first control signal through a logic control circuit; and generating a second output signal by the amplifying circuit according to the first output signal, the second control signal and the third control signal.

In summary, the transmitting circuit of the invention has the advantage of low power consumption.

Drawings

In order to make the aforementioned and other objects, features, advantages and embodiments of the invention more comprehensible, the following description is given:

FIG. 1 is a schematic diagram of an electronic system depicted in accordance with some embodiments of the present invention;

FIG. 2 is a schematic diagram of the transmission circuit of FIG. 1 depicted in accordance with some embodiments of the present invention;

FIG. 3 is a schematic diagram of the amplification circuit of FIG. 2, depicted in accordance with some embodiments of the present invention;

FIG. 4 is a waveform diagram of a plurality of signals of FIGS. 2 and 3, depicted in accordance with some embodiments of the present invention; and

FIG. 5 is a flow diagram depicting a method of operation in accordance with some embodiments of the invention.

Detailed Description

The term "coupled" as used herein may also refer to "electrically coupled," and the term "connected" may also refer to "electrically connected. "coupled" and "connected" may also mean that two or more elements co-operate or interact with each other.

Refer to fig. 1. FIG. 1 is a schematic diagram of an electronic system 100 depicted in accordance with some embodiments of the present invention.

For the example of fig. 1, the electronic system 100 includes an electronic device D1, an electronic device D2, and a cable (cable) CAB. Electronic device D1 and electronic device D2 are each coupled to a cable CAB. In some embodiments, the electronic device D1 includes a transmitting circuit Tx and a capacitance C1. The electronic device D2 includes a receiving circuit Rx and a capacitor C2. The cable CAB includes an inductor L1, a capacitor C3, and a capacitor C4. The transmit circuit Tx of the electronic device D1 may be coupled to the cable CAB through pin (pin) P1, and the receive circuit Rx of the electronic device D2 may be coupled to the cable CAB through pin P2. In this way, the transmitting circuit Tx and the receiving circuit Rx can perform signal/data transmission through the cable CAB.

In some embodiments, electronic system 100 is implemented in Type-C technology. That is, the electronic device D1, the electronic device D2, the pin P1 and the pin P2 adopt the Type-C technology.

The configuration of the electronic system 100 described above is for illustrative purposes only, and various suitable configurations of the electronic system 100 are within the scope of the present invention.

Refer to fig. 2. Fig. 2 is a schematic diagram of the transmission circuit Tx of fig. 1 depicted in accordance with some embodiments of the present invention. In the example of fig. 2, the transmission circuit Tx includes a slew rate control circuit 210, a hysteresis circuit 220, a logic control circuit 230, and an amplifying circuit 240. The slew rate control circuit 210 is coupled to the hysteresis circuit 220 and the amplification circuit 240. The logic control circuit 230 is coupled to the hysteresis circuit 220 and the amplification circuit 240.

In operation, the slew rate control circuit 210 is configured to receive an input signal DIN. The slew rate control circuit 210 controls the slew rate of the input signal DIN to generate the output signal SRO. For the example of fig. 2, the input signal DIN is a square wave. The output signal SRO output from the slew rate control circuit 210 is a trapezoidal wave (the slew rate is reduced). That is, the voltage change width per unit time of the output signal SRO is small. The hysteresis circuit 220 is configured to receive the output signal SRO and generate a control signal OHYS according to the output signal SRO. The logic control circuit 230 is configured to receive an input signal DIN and a control signal OHYS. The logic control circuit 230 generates a control signal YP and a control signal YN according to the input signal DIN and the control signal OHYS. The amplifying circuit 240 receives the output signal SRO and the fed-back output signal OUT and is controlled by the control signal YP and the control signal YN to generate the output signal OUT. In some embodiments, the amplifying circuit 240 is a unity gain buffer (unity gain buffer). In this way, the amplifying circuit 240 can generate the output signal OUT according to the output signal SRO, and transmit the output signal OUT to the cable CAB and the receiving circuit Rx of fig. 1, so as to complete signal/data transmission.

For the example of FIG. 2, the hysteresis circuit 220 comprises comparators 2201-2202, NAND gate 2203-2205, NOR gate 2206 and inverter 2207. The

comparators

2201 and 2202 are used for receiving the output signal SRO. The comparator 2201 compares the output signal SRO with a threshold VH. The comparator 2202 compares the output signal SRO with the threshold VL. NAND gate 2203 and NOR gate 2206 are coupled to the outputs of comparators 2201-2202. Inverter 2207 is coupled to the output of nor gate 2206. Nand gate 2204 is coupled to the output of inverter 2207 and to the output of nand gate 2205. Nand gate 2205 is coupled to the output of nand gate 2203 and to the output of nand gate 2204. The

NAND gate

2204 and 2205 are used to output the control signal OHYS.

The configuration of the hysteresis circuit 220 described above is for exemplary purposes only, and various suitable configurations of the hysteresis circuit 220 are within the scope of the present invention.

In addition, for the example of fig. 2, the logic control circuit 230 includes an AND gate (AND gate)2301 AND an OR gate (OR gate) 2302. The and gate 2301 and the or gate 2302 are configured to receive the input signal DIN and the control signal OHYS, and respectively output the control signal YP and the control signal YN according to the input signal DIN and the control signal OHYS.

The configuration of the logic control circuit 230 described above is for illustrative purposes only, and various suitable configurations of the logic control circuit 230 are within the scope of the present invention.

Refer to fig. 3. Fig. 3 is a schematic diagram of the amplification circuit 240 of fig. 2, depicted in accordance with some embodiments of the present invention. Taking the example of fig. 3, the amplifying circuit 240 includes a gain stage 241, a control stage 242, and an output stage 243. The gain stage 241 is used to provide a unity gain. The control stage 242 controls the output stage 243 to output the output signal OUT according to the control signal YN and the control signal YP.

The gain stage 241 is configured to receive the output signal SRO from the slew rate control circuit 210 and the output signal OUT from the output stage 243. For the example of FIG. 3, gain stage 241 includes transistors MB, MH1-MH5, MH6A-MH6B, ML7, and ML8A-ML 8B. The transistor MB is used for receiving the power voltage VDDH and the bias voltage Vb to generate the constant current Ib. Equivalently, the transistor MB operates as a current source circuit IS. The transistors MH1-MH2 are used for receiving the constant current Ib and are respectively controlled by the output signal SRO and the output signal OUT. The transistors ML7 and ML8A-ML8B are used for receiving the power voltage VDDL. The transistors MH3-MH5 and MH6A-MH6B are used for receiving the ground voltage GND. Transistor MH6A and transistor ML8A are coupled to node N1. Transistor MH6B and transistor ML8B are coupled to node N2.

In some embodiments, supply voltage VDDH is higher than supply voltage VDDL. For example, the supply voltage VDDL may be 1.05-1.2 volts, while the supply voltage VDDH may be twice or three times the supply voltage VDDL. In addition, the supply voltage VDDH may be a supply voltage of an input/output device (I/O device).

The above configuration of the values of the power supply voltage VDDH and the power supply voltage VDDL is for illustrative purposes only, and various suitable values of the power supply voltage VDDH and the power supply voltage VDDL are within the scope of the invention.

In some related arts, the power voltage of the current source circuit IS the same as the power voltage received by some transistors (e.g., both are the power voltage VDDL). In this case, the headroom (head room) of the gain stage 241 is not large enough, so that the gain stage 241 cannot operate normally and cannot provide the correct gain. For example, if the transistor MB of the current source circuit IS and the transistor ML9 for generating the output signal OUT (input to the gate of the transistor MH 2) both receive the power voltage VDDL, the transistor MH2 will not work normally when the output signal OUT IS the power voltage VDDL, so that the gain stage 241 cannot provide correct gain. Based on the above, in other related arts, an additional enhancement stage circuit is provided to ensure that the gain stage 241 can operate normally. However, the additional enhancement stage circuit will increase the circuit area and cost.

In contrast to the related art, in the gain stage 241 of the present invention, the transistor MB of the current source circuit IS used for receiving the power voltage VDDH, and the power voltage VDDH IS higher than the power voltage VDDL. In this case, the headroom of the gain stage 241 is large enough so there is no problem as described above. Therefore, the gain stage 241 can normally operate to provide the correct unity gain without providing an additional enhancement stage circuit.

The configuration of the gain stage 241 described above is for illustrative purposes only, and various suitable configurations of the gain stage 241 are within the scope of the present invention.

The control stage 242 generates a gate signal GA and a gate signal GB according to the control signal YN and the control signal YP, respectively. For the example of fig. 3, the control stage 242 includes a transistor SWP and a transistor SWN. The transistor SWP is used for receiving a power voltage VDDL and is controlled by a control signal YN to generate a gate signal GA at a node N1. The transistor SWN is used for receiving a ground voltage GND and is controlled by a control signal YP to generate a gate signal GB at a node N2.

The output stage 243 is used for generating an output signal OUT according to the gate signal GA and the gate signal GB. For the example of fig. 3, the output stage 243 includes a transistor ML9 and a transistor ML 10. The transistor ML9 and the transistor ML10 are coupled to the node N3 to generate the output signal OUT at the node N3. Specifically, the transistor ML9 is used for receiving a power voltage VDDL and is coupled to the node N1 to be controlled by a gate signal GA. The transistor ML10 is used for receiving a ground voltage GND and is coupled to the node N2 to be controlled by a gate signal GB.

Reference is made to fig. 2, 3 and 4 together. Fig. 4 is a waveform diagram of the plurality of signals of fig. 2 and 3, depicted in accordance with some embodiments of the present invention. Fig. 4 depicts waveforms of the input signal DIN, the output signal SRO, the control signal OHYS, the control signal YP, and the control signal YN.

For the example of fig. 4, the input signal DIN is a square wave. The output signal SRO output from the slew rate control circuit 210 is a trapezoidal wave (the slew rate is reduced). The output signal SRO is defined by a voltage value V1, a voltage value V2, a voltage value V3, and a voltage value V4, which correspond to 0%, 10%, 90%, and 100% in sequence. In some embodiments, the control signal OHYS and the control signal YP may be preset to a low logic level. The control signal YN may be preset to a high logic level. Therefore, the transistors SWN and SWP of the control stage 242 are preset to be off.

Based on the operation of the hysteresis circuit 220, the control signal OHYS has a high logic level when the output signal SRO rises from the voltage value V3 to the voltage value V4, remains at the voltage value V4 for a period of time, and falls from the voltage value V4 to the voltage value V2 (i.e., the time interval T1 and the time interval T2). When the output signal SRO falls from the voltage value V2 to the voltage value V1, is maintained at the voltage value V1 for a certain period of time, and rises from the voltage value V1 to the voltage value V3 (i.e., the time interval T3 and the time interval T4), the control signal OHYS has a low logic level.

At the time interval T1, since the input signal DIN has a high logic level and the control signal OHYS has a high logic level, the control signal YP output by the and gate 2301 has a high logic level. In this case, the transistor SWN of fig. 3 is turned on. Since the transistor SWN is turned on, the gate signal GB at the node N2 is pulled to the ground voltage GND. Therefore, the transistor ML10 is completely turned off.

At the time interval T3, since the input signal DIN has a low logic level and the control signal OHYS has a low logic level, the control signal YN output by the or gate 2302 has a low logic level. In this case, the transistor SWP of fig. 3 is turned on. With transistor SWP turned on, the gate signal GA at node N1 is pulled to supply voltage VDDL. Therefore, the transistor ML9 is completely turned off.

In some related technologies, the transistors ML9 and ML10 may be turned on simultaneously in the time interval T1 or in the time interval T3, so that the dc current flows through the transistors ML9 and ML 10. Compared to the related arts, the transistors ML9 and ML10 of the present invention are controlled by different gate signals (gate signal GA/gate signal GB). In addition, the transistor ML10 of the present invention may be completely turned off at the time interval T1 and the transistor ML9 of the present invention may be completely turned off at the time interval T3. Therefore, the transistors ML10 and ML9 can be prevented from being turned on at the same time, so as to prevent the dc current from flowing through the transistors ML9 and ML10, thereby reducing the power consumption. Furthermore, since the power consumption of the transmitting circuit Tx occupies almost most of the power consumption of the whole chip, the power consumption of the whole chip can be greatly reduced by configuring the transmitting circuit Tx according to the present invention.

In addition, the transmitting circuit Tx of the present invention employs a feed-forward system, so that the risk of the output of the circuit being locked (lock) is avoided. Alternatively, the threshold VH or VL input to the

comparator

2201 or 2202 may be designed according to system requirements to ensure signal integrity and thus meet the specification (spec). For example, the related art standard of Type-C can be met.

The on or off levels of these signals are for exemplary purposes only and may be designed accordingly to correspond to the type of these components (e.g., transistors) in the circuit.

Refer to fig. 5. Fig. 5 is a flow chart depicting a method 500 of operation in accordance with some embodiments of the invention. The working method 500 includes operation S510, operation S520, operation S530, and operation S540. In some embodiments, the operation method 500 is applied to the transmission circuit Tx in fig. 2, but the invention is not limited thereto. For ease of understanding, the method of operation 500 will be discussed in conjunction with fig. 1-4.

In operation S510, the slew rate of the input signal DIN is controlled by the slew rate control circuit 210 to generate the output signal SRO. In some embodiments, the input signal DIN is a square wave. The slew rate control circuit 210 controls the slew rate of the input signal DIN to generate a desired signal (e.g., the output signal SRO) (trapezoidal wave).

In operation S520, a control signal OHYS is generated by the hysteresis circuit 220 according to the output signal SRO. The hysteresis circuit 220 may be implemented using various logic gates, and the present invention is not limited to the hysteresis circuit 220 depicted in FIG. 2.

In operation S530, the logic control circuit 230 generates the control signal YP and the control signal YN according to the input signal DIN and the control signal OHYS. Similarly, the logic control circuit 230 can be implemented by various logic gates, and the invention is not limited to the logic control circuit 230 depicted in FIG. 2.

In operation S540, the amplifying circuit 240 generates an output signal OUT according to the output signal SRO, the fed-back output signal OUT, the control signal YP, and the control signal YN. In some embodiments, the control signal YP is used to control the transistor SWN of the control stage 242 of the amplifier circuit 240, and the control signal YN is used to control the transistor SWP of the control stage 242 of the amplifier circuit 240, thereby controlling the gate signal GA and the gate signal GB. The gate signals GA and GA are used to control the transistors ML9 and ML10, so as to prevent the transistors ML9 and ML10 from being turned on simultaneously. Thus, the effect of reducing power consumption can be achieved.

Various functional elements and blocks have been disclosed herein. It will be apparent to one of ordinary skill in the art that functional blocks may be implemented by circuits (whether dedicated circuits or general-purpose circuits that operate under the control of one or more processors and coded instructions), which generally comprise transistors or other circuit elements for controlling the operation of the electrical circuits corresponding to the functions and operations described herein. As will be further appreciated, the specific structure and interconnections of circuit elements in general may be determined by a compiler, such as a Register Transfer Language (RTL) compiler. A register transfer language compiler operates on scripts (scripts) that are fairly similar to assembly language code (assembly language code) and compiles the scripts into a form for layout or fabrication of the final circuit. Indeed, register transfer languages are known for their role and purpose in facilitating the design process of electronic and digital systems.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Description of the reference numerals:

100 electronic system

210 slew rate control circuit

220 retarding circuit

2201,2202 comparator

2203,2204,2205 NAND gate

2206 NOR gate

2207 inverter

230 logic control circuit

2301 AND gate

2302 OR gate

240: amplifying circuit

241 gain stage

242 control stage

243 output stage

500 working method

D1, D2 electronic device

Tx: transmission circuit

Rx receiving circuit

CAB cable

P1, P2 pins

L1 inductor

C1, C2, C3 and C4

DIN input signal

SRO, OUT output signal

OHYS, YP, YN control signals

VH, VL: threshold

MB, MH1-MH5, MH6A-MH6B, ML7, ML8A-ML8B, ML9-ML10, SWP, SWN transistors

IS current source circuit

Ib constant current

Vb bias voltage

GA, GB gate signal

VDDH, VDDL power supply voltage

GND ground voltage

N1, N2, N3 nodes

V1, V2, V3, V4 voltage values

T1, T2, T3, T4 time interval

Operations S510, S520, S530, S540

Claims

1. A transmit circuit, comprising:

the slew rate control circuit is used for controlling the slew rate of an input signal so as to generate a first output signal;

a hysteresis circuit for generating a first control signal according to the first output signal; wherein the first control signal has a first logic level when the first output signal rises from a first voltage value to a second voltage value, is at the second voltage value, and falls from the second voltage value to a third voltage value;

a logic control circuit for generating a second control signal and a third control signal according to the input signal and the first control signal; wherein the second control signal has a first logic level when the input signal and the first control signal have the first logic level; when the input signal and the first control signal have a second logic level, the third control signal has the second logic level; and

the amplifying circuit is used for generating the second output signal according to the first output signal, the second control signal and the third control signal.

2. The transmit circuit of claim 1, wherein the first control signal has the second logic level when the first output signal falls from the third voltage value to a fourth voltage value, is at the fourth voltage value, and rises from the fourth voltage value to the first voltage value.

3. The transmit circuit of claim 1, wherein the amplification circuit comprises:

a gain stage to receive the first output signal and the second output signal;

a control stage for generating a first gate signal and a second gate signal according to the second control signal and the third control signal, respectively; and

the output stage is used for generating the second output signal according to the first grid signal and the second grid signal.

4. The transmit circuit of claim 3, wherein the control stage comprises:

a first transistor for receiving a first power voltage and controlled by the third control signal to generate the first gate signal; and

a second transistor for receiving a ground voltage and controlled by the second control signal to generate the second gate signal,

wherein the output stage comprises:

a third transistor for receiving the first power voltage and controlled by the first gate signal; and

a fourth transistor to receive the ground voltage and controlled by the second gate signal,

wherein the fourth transistor is coupled to the third transistor at a node and the second output signal is generated at the node.

5. The transmit circuit of claim 4, wherein the current source circuit of the gain stage is configured to receive a second supply voltage and a bias voltage to operate, wherein the second supply voltage is greater than the first supply voltage.

6. The transmit circuit of claim 1, wherein the transmit circuit is included in a Type-C device.

7. A method of operation for a transmit circuit, the method of operation comprising:

controlling the slew rate of the input signal through a slew rate control circuit to generate a first output signal;

generating a first control signal according to the first output signal through a hysteresis circuit;

generating a second control signal and a third control signal according to the input signal and the first control signal through a logic control circuit; and

and generating the second output signal by an amplifying circuit according to the first output signal, the second control signal and the third control signal.