CN218335982U - Clock generation circuit and DC-DC converter - Google Patents
Clock generation circuit and DC-DC converter Download PDFInfo
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- CN218335982U CN218335982U CN202221346008.XU CN202221346008U CN218335982U CN 218335982 U CN218335982 U CN 218335982U CN 202221346008 U CN202221346008 U CN 202221346008U CN 218335982 U CN218335982 U CN 218335982U
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Abstract
The utility model discloses a clock generation circuit and a DC-DC converter, wherein the clock generation circuit is used for generating a clock signal with fixed frequency; the clock generation circuit comprises a first zero temperature coefficient resistor; the first zero temperature coefficient resistor is used for temperature compensation; the zero-temperature coefficient resistor is arranged in the clock generating circuit, so that the oscillation frequency of the clock generating circuit is insensitive to temperature, the influence of temperature factors on a switch power supply circuit is effectively avoided, and the reliability of the clock generating circuit is improved.
Description
Technical Field
The utility model belongs to the technical field of integrated circuit switching power supply, in particular to clock generation circuit and DC-DC converter.
Background
With the development of the internet of things, wireless sensors and embedded equipment, higher requirements are put forward on a switching power supply converter inside the equipment, namely the switching power supply converter is required to reliably work under a fixed frequency; the high integration level is ensured, and the designed clock generation circuit module is not influenced by the process, the temperature and the power supply voltage so as to ensure the high reliability of the clock generation circuit module.
Currently, the oscillator integrated on the switching power converter chip includes a ring oscillator and an RC oscillator; compared with a ring oscillator, the RC oscillator can realize lower power consumption and higher precision in a limited area; the frequency stability of RC oscillators is susceptible to process, voltage, and temperature.
Therefore, for a switching power converter with a fixed operating frequency, it is necessary to design a highly reliable clock generation circuit, which has a stable operating frequency for a long time and has low sensitivity to a supply voltage and stability.
SUMMERY OF THE UTILITY MODEL
To the technical problem who exists among the prior art, the utility model provides a clock generation circuit and DC-DC converter to solve current clock generation circuit module and easily receive the temperature to influence, the lower technical problem of reliability.
In order to achieve the above purpose, the utility model adopts the technical scheme that:
the utility model provides a clock generating circuit, which is used for generating a clock signal with fixed frequency; the clock generation circuit comprises a first zero temperature coefficient resistor; and the first zero temperature coefficient resistor is used for temperature compensation.
Further, the clock generating circuit includes a first P-type MOS transistor MP1, a second P-type MOS transistor MP2, a third P-type MOS transistor MP3, a fourth P-type MOS transistor MP4, a fifth P-type MOS transistor MP5, a sixth P-type MOS transistor MP6, a seventh P-type MOS transistor MP7, a first N-type MOS transistor MN1, a second N-type MOS transistor MN2, a third N-type MOS transistor MN3, a fourth N-type MOS transistor MN4, a fifth N-type MOS transistor MN5, a sixth N-type MOS transistor MN6, a seventh N-type MOS transistor MN7, a first zero-temperature-coefficient resistor, a capacitor C1, a first inverter, and a second inverter;
one end of the first zero-temperature-coefficient resistor is connected with the drain electrode of the first N-type MOS tube MN1 and the grid electrode of the first N-type MOS tube MN 1; the other end of the first zero-temperature-coefficient resistor is connected with the drain electrode of the first P-type MOS transistor MP1 and the grid electrode of the first P-type MOS transistor MP 1; the drain electrode of the first N-type MOS tube MN1 is connected with the grid electrode of the first N-type MOS tube MN1, the grid electrode of the second N-type MOS tube MN2 and the grid electrode of the seventh N-type MOS tube MN 7; the grid electrode of the second N-type MOS tube MN2 and the grid electrode of the seventh N-type MOS tube MN7 are connected to the grid electrode of the first N-type MOS tube MN 1;
the drain electrode of the first P-type MOS transistor MP1 is connected with the grid electrode of the first P-type MOS transistor MP1, the grid electrode of the second P-type MOS transistor MP2 and the grid electrode of the sixth P-type MOS transistor MP 6; the grid electrode of the second P-type MOS transistor MP2 and the grid electrode of the sixth P-type MOS transistor MP6 are both connected to the grid electrode of the first P-type MOS transistor MP 1; the drain electrode of the second P-type MOS tube MP2 is connected with the source electrode of the third P-type MOS tube MP 3; the drain electrode of the second N-type MOS tube MN2 is connected with the source electrode of the third N-type MOS tube MN 3; the drain electrode of the third P-type MOS tube MP3 is connected with the drain electrode of the third N-type MOS tube MN 3; the grid electrode of the third P-type MOS tube MP3 is connected with the grid electrode of the third N-type MOS tube MN 3;
the grid electrode of the fourth P-type MOS transistor MP4 is connected with the grid electrode of the fifth N-type MOS transistor MN 5; one end of the capacitor C1 is connected with the drain electrode of the third P-type MOS tube MP3, the drain electrode of the third N-type MOS tube MN3, the grid electrode of the fourth P-type MOS tube MP4 and the grid electrode of the fifth N-type MOS tube MP5, and the other end of the capacitor C1 is connected to GND; the drain electrode of the fourth P-type MOS transistor MP4 is connected with the source electrode of the fifth P-type MOS transistor MP 5; the source electrode of the fourth N-type MOS tube MN4 is connected with the drain electrode of the fifth N-type MOS tube MN 5; the drain electrode of the fifth P-type MOS transistor MP5 is connected with the drain electrode of the fourth N-type MOS transistor MN 4; the grid electrode of the fifth P-type MOS transistor MP5 is connected with the grid electrode of the fourth N-type MOS transistor MN 4;
the grid electrode of the fifth P-type MOS tube MP5 is connected with the grid electrode of the third N-type MOS tube MN 3; the drain electrode of the sixth P-type MOS transistor MP6 is connected with the source electrode of the seventh P-type MOS transistor MP 7; the source electrode of the sixth N-type MOS transistor MN6 is connected with the drain electrode of the seventh N-type MOS transistor MN 7; the drain electrode of the sixth N-type MOS transistor MN6 is connected with the drain electrode of the seventh P-type MOS transistor MP 7; the grid electrode of the sixth N-type MOS transistor MN6 is connected with the grid electrode of the seventh P-type MOS transistor MP 7; the drain electrode of the seventh P-type MOS transistor MP7 is connected with the drain electrode of the fifth P-type MOS transistor MP 5; the drain electrode of the seventh P-type MOS tube MP7 is connected with the input end of the first phase inverter, the output end of the first phase inverter is connected with the grid electrode of the third N-type MOS tube MN3, the output end of the first phase inverter is connected with the input end of the second phase inverter, and the output end of the second phase inverter is connected with the grid electrode of the seventh P-type MOS tube MP 7.
Further, the first zero temperature coefficient resistor includes a first positive temperature coefficient resistor RP1 and a first negative temperature coefficient resistor RN1; one end of the first positive temperature coefficient resistor RP1 is connected with one end of the first negative temperature coefficient resistor RN1; the other end of the first positive temperature coefficient resistor RP1 is connected with the drain electrode of the first N-type MOS tube MN1 and the grid electrode of the first N-type MOS tube MN 1; the other end of the first negative temperature coefficient resistor RN1 is connected with the drain electrode of the first P-type MOS transistor MP1 and the grid electrode of the first P-type MOS transistor MP 1.
Further, the source electrode of the first P-type MOS transistor MP1, the source electrode of the second P-type MOS transistor MP2, the source electrode of the fourth P-type MOS transistor MP4, and the source electrode of the sixth P-type MOS transistor MP6 are all connected to VDD.
Further, the source electrode of the first N-type MOS transistor MN1, the source electrode of the second N-type MOS transistor MN2, the source electrode of the fifth N-type MOS transistor MN5, and the source electrode of the seventh N-type MOS transistor MN7 are all connected to GND.
Further, the ratio of the sizes of the first P-type MOS transistor MP1 and the second P-type MOS transistor MP2 is 1; the size ratio of the first N-type MOS transistor MN1 to the second N-type MOS transistor MN2 is 1.
The utility model also provides a clock generating circuit, which is used for generating the clock signal with the selectable duty ratio; the clock generation circuit comprises a second zero temperature coefficient resistor and a selection capacitor C2; the second zero temperature coefficient resistor is used for temperature compensation; and the selection capacitor C2 is used for controlling the duty ratio.
Further, the clock generating circuit includes an eighth P-type MOS transistor MP8, a ninth P-type MOS transistor MP9, a tenth P-type MOS transistor MP10, an eleventh P-type MOS transistor MP11, a twelfth P-type MOS transistor MP12, a thirteenth P-type MOS transistor MP13, a fourteenth P-type MOS transistor MP14, a fifteenth P-type MOS transistor MP15, an eighth N-type MOS transistor MN8, a ninth N-type MOS transistor MN9, a tenth N-type MOS transistor MN10, an eleventh N-type MOS transistor MN11, a twelfth N-type MOS transistor MN12, a thirteenth N-type MOS transistor MN13, a fourteenth N-type MOS transistor MN14, a second zero-temperature-coefficient resistor, a selection capacitor C2, a third inverter, and a fourth inverter;
one end of the second zero-temperature-coefficient resistor is connected with both the drain electrode of the fourteenth N-type MOS transistor MN14 and the gate electrode of the fourteenth N-type MOS transistor MN 14; the other end of the second zero temperature coefficient resistor is connected with the drain electrode of the fifteenth P-type MOS transistor MP15 and the grid electrode of the fifteenth P-type MOS transistor MP 15;
the grid electrode of the eighth P-type MOS transistor MP8, the grid electrode of the tenth P-type MOS transistor MP10 and the grid electrode of the thirteenth P-type MOS transistor MP13 are all connected to the grid electrode of the first five P-type MOS transistor MP 15; the drain electrode of the eighth P-type MOS transistor MP8 is connected with the source electrode of the ninth P-type MOS transistor MP 9; the drain electrode of the eighth N-type MOS transistor MN8 is connected with the drain electrode of the tenth P-type MOS transistor MP 10; the source electrode of the eighth N-type MOS transistor MN8 is connected with the drain electrode of the ninth P-type MOS transistor MP 9; the grid electrode of the eleventh P-type MOS tube MP11 is connected with the grid electrode of the eleventh N-type MOS tube MN 11; the drain electrode of the eighth N-type MOS transistor MN8 is connected with the drain electrode of the ninth N-type MOS transistor MN9 and the grid electrode of the ninth N-type MOS transistor MN 9;
one end of the selection capacitor C2 is connected with the drain electrode of the ninth P-type MOS transistor MP9 and the grid electrode of the eleventh P-type MOS transistor MP11, and the other end of the selection capacitor C2 is connected to GND; the drain electrode of the eleventh P-type MOS transistor MP11 is connected with the source electrode of the twelfth P-type MOS transistor MP 12; the source electrode of the tenth N-type MOS tube MN10 is connected with the drain electrode of the eleventh N-type MOS tube MN 11; the drain electrode of the twelfth P-type MOS tube MP12 is connected with the drain electrode of the tenth N-type MOS tube MN 10; the grid electrode of the twelfth P-type MOS tube MP12 is connected with the grid electrode of the tenth N-type MOS tube MN 10; the grid electrode of the tenth N-type MOS tube MN10 is connected with the grid electrode of the ninth P-type MOS tube MP 9;
the drain electrode of the thirteenth P-type MOS transistor MP13 is connected with the source electrode of the fourteenth P-type MOS transistor MP 14; the source electrode of the twelfth N-type MOS tube MN12 is connected with the drain electrode of the thirteenth N-type MOS tube MN 13; the drain electrode of the twelfth N-type MOS tube MN12 is connected with the drain electrode of the fourteenth P-type MOS tube MP 14; the grid electrode of the twelfth N-type MOS tube MN12 is connected with the grid electrode of the fourteenth P-type MOS tube MP 14; the drain electrode of the fourteenth P-type MOS transistor MP14 is connected with the drain electrode of the twelfth P-type MOS transistor MP 12; the drain of the fourteenth P-type MOS transistor MP14 is connected to the input of the third inverter, and the output of the third inverter is connected to the input of the fourth inverter.
Further, the second zero temperature coefficient resistor comprises a second positive temperature coefficient resistor RP2 and a second negative temperature coefficient resistor RN2; one end of the second positive temperature coefficient resistor RP2 is connected with one end of the second negative temperature coefficient resistor RN2; the other end of the second positive temperature coefficient resistor RP2 is connected with the drain electrode of the fourteenth N-type MOS tube MN14 and the grid electrode of the fourteenth N-type MOS tube MN 2; the other end of the second negative temperature coefficient resistor RN2 is connected to the drain of the fifteenth P-type MOS transistor MP15 and the gate of the fifteenth P-type MOS transistor MP 15.
The utility model also provides a DC-DC converter, which comprises the clock generation circuit; the DC-DC converter is a DC-DC converter with fixed working frequency.
Compared with the prior art, the beneficial effects of the utility model are that:
the utility model provides a clock generation circuit and DC-DC converter adopts and sets up zero temperature coefficient resistance in the clock generation circuit for the oscillation frequency of clock generation circuit shows for the insensitivity to the temperature, effectively avoids the influence of temperature factor to switch power supply circuit, has improved the reliability that the clock generation circuit reaches.
Furthermore, the zero temperature coefficient resistor adopts a combination mode of a positive temperature coefficient resistor and a negative temperature coefficient resistor, and the zero temperature coefficient resistor can be obtained by adjusting the positive temperature coefficient resistor and the negative temperature coefficient resistor, so that the sensitivity of the oscillation frequency of the clock generation circuit to the temperature is effectively reduced.
Furthermore, the duty ratio of the clock signal is adjusted by setting the selection capacitor and adjusting the capacitance value of the selection capacitor, so that the clock signal with the adjustable duty ratio is generated.
Drawings
FIG. 1 is a circuit diagram of a clock generation circuit described in embodiment 1;
fig. 2 is a circuit diagram of the clock generation circuit described in embodiment 2.
Detailed Description
In order to make the technical problem solved by the present invention, the technical solution and the beneficial effects thereof are more clearly understood, and the following detailed description is made for the present invention. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Example 1
As shown in fig. 1, the present embodiment 1 provides a clock generation circuit for generating a clock signal of a fixed frequency; the clock generation circuit comprises a first zero temperature coefficient resistor; and the first zero temperature coefficient resistor is used for temperature compensation.
In this embodiment 1, the clock generating circuit includes a first P-type MOS transistor MP1, a second P-type MOS transistor MP2, a third P-type MOS transistor MP3, a fourth P-type MOS transistor MP4, a fifth P-type MOS transistor MP5, a sixth P-type MOS transistor MP6, a seventh P-type MOS transistor MP7, a first N-type MOS transistor MN1, a second N-type MOS transistor MN2, a third N-type MOS transistor MN3, a fourth N-type MOS transistor MN4, a fifth N-type MOS transistor MN5, a sixth N-type MOS transistor MN6, a seventh N-type MOS transistor MN7, a first zero temperature coefficient resistor, a capacitor C1, a first inverter, and a second inverter; the first zero temperature coefficient resistor comprises a first positive temperature coefficient resistor RP1 and a first negative temperature coefficient resistor RN1.
One end of the first positive temperature coefficient resistor RP1 is connected with one end of the first negative temperature coefficient resistor RN1; the other end of the first positive temperature coefficient resistor RP1 is connected with the drain electrode of the first N-type MOS tube MN1 and the grid electrode of the first N-type MOS tube MN 1; the other end of the first negative temperature coefficient resistor RN1 is connected to both the drain of the first P-type MOS transistor MP1 and the gate of the first P-type MOS transistor MP 1.
The drain electrode of the first N-type MOS tube MN1 is connected with the grid electrode of the first N-type MOS tube MN1, the grid electrode of the second N-type MOS tube MN2 and the grid electrode of the seventh N-type MOS tube MN 7; the grid electrode of the second N-type MOS tube MN2 and the grid electrode of the seventh N-type MOS tube MN7 are connected to the grid electrode of the first N-type MOS tube MN 1; the drain electrode of the first P-type MOS transistor MP1 is connected with the grid electrode of the first P-type MOS transistor MP1, the grid electrode of the second P-type MOS transistor MP2 and the grid electrode of the sixth P-type MOS transistor MP 6; the grid electrode of the second P-type MOS transistor MP2 and the grid electrode of the sixth P-type MOS transistor MP6 are both connected to the grid electrode of the first P-type MOS transistor MP 1; the drain electrode of the second P-type MOS tube MP2 is connected with the source electrode of the third P-type MOS tube MP 3; the drain electrode of the second N-type MOS tube MN2 is connected with the source electrode of the third N-type MOS tube MN 3; the drain electrode of the third P-type MOS tube MP3 is connected with the drain electrode of the third N-type MOS tube MN 3; the grid electrode of the third P-type MOS transistor MP3 is connected with the grid electrode of the third N-type MOS transistor MN 3.
The grid electrode of the fourth P-type MOS transistor MP4 is connected with the grid electrode of the fifth N-type MOS transistor MN 5; one end of the capacitor C1 is connected with the drain electrode of the third P-type MOS tube MP3, the drain electrode of the third N-type MOS tube MN3, the grid electrode of the fourth P-type MOS tube MP4 and the grid electrode of the fifth N-type MOS tube MP5, and the other end of the capacitor C1 is connected to GND; the drain electrode of the fourth P-type MOS transistor MP4 is connected with the source electrode of the fifth P-type MOS transistor MP 5; the source electrode of the fourth N-type MOS tube MN4 is connected with the drain electrode of the fifth N-type MOS tube MN 5; the drain electrode of the fifth P-type MOS tube MP5 is connected with the drain electrode of the fourth N-type MOS tube MN 4; the grid electrode of the fifth P-type MOS transistor MP5 is connected with the grid electrode of the fourth N-type MOS transistor MN 4; the grid electrode of the fifth P-type MOS tube MP5 is connected with the grid electrode of the third N-type MOS tube MN 3; the drain electrode of the sixth P-type MOS transistor MP6 is connected with the source electrode of the seventh P-type MOS transistor MP 7; the source electrode of the sixth N-type MOS tube MN6 is connected with the drain electrode of the seventh N-type MOS tube MN 7; the drain electrode of the sixth N-type MOS transistor MN6 is connected with the drain electrode of the seventh P-type MOS transistor MP 7; the grid electrode of the sixth N-type MOS transistor MN6 is connected with the grid electrode of the seventh P-type MOS transistor MP 7; the drain electrode of the seventh P-type MOS transistor MP7 is connected with the drain electrode of the fifth P-type MOS transistor MP 5; the drain electrode of the seventh P-type MOS transistor MP7 is connected with the input end of the first phase inverter, the output end of the first phase inverter is connected with the grid electrode of the third N-type MOS transistor MN3, and the output end of the first phase inverter is connected with the input end of the second phase inverter; the output end of the first inverter and the input end of the second inverter are both connected with a CLKN signal source; the output end of the second inverter is connected with the gate of the seventh P-type MOS transistor MP7 and both connected to the output pin CLK.
In this embodiment 1, the source electrode of the first P-type MOS transistor MP1, the source electrode of the second P-type MOS transistor MP2, the source electrode of the fourth P-type MOS transistor MP4, and the source electrode of the sixth P-type MOS transistor MP6 are all connected to VDD; the source electrode of the first N-type MOS tube MN1, the source electrode of the second N-type MOS tube MN2, the source electrode of the fifth N-type MOS tube MN5 and the source electrode of the seventh N-type MOS tube MN7 are all connected to GND; preferably, the ratio of the sizes of the first P-type MOS transistor MP1 to the second P-type MOS transistor MP2 is 1; the size ratio of the first N-type MOS transistor MN1 to the second N-type MOS transistor MN2 is 1.
The working principle is as follows:
the clock generation circuit described in this embodiment 1 adjusts the resistance values of the positive temperature coefficient resistor and the negative temperature coefficient resistor by setting the positive temperature coefficient resistor and the negative temperature coefficient resistor, so that the positive temperature coefficient resistor and the negative temperature coefficient resistor are combined to form a zero temperature coefficient resistor, and then the oscillation frequency of the circuit is rendered insensitive to temperature, thereby avoiding the influence of temperature factors on the circuit and improving the reliability of the circuit.
In this embodiment 1, the currents of the first P-type MOS transistor MP1 and the first N-type MOS transistor MN1 are the same and are both denoted as a current I; the voltage of the capacitor C1 is denoted as C 1 The oscillation period of the circuit is marked as T, the resistance value of the first positive temperature coefficient resistor RP1 is marked as RP, and the resistance value of the first negative temperature coefficient resistor RN1 is marked as RN; wherein the current I is:
when the charging current of the capacitor C1 is 4I, the voltage C of the capacitor C1 1 Has a swing amplitude of V DD -V GSP4 -V GSN5 When the gate-source voltages of the first N-type MOS transistor MN1 and the fifth N-type MOS transistor MN5 are cancelled out and the gate-source voltages of the first P-type MOS transistor MP1 and the fourth P-type MOS transistor MP4 are cancelled out, the following formula is satisfied:
therefore, the oscillation period of the clock generation circuit is only related to the resistor C1, the first positive temperature coefficient resistor RP1 and the first negative temperature coefficient resistor RN1; therefore, the resistance values of the positive temperature coefficient resistor and the negative temperature coefficient resistor are adjusted to be combined to form a zero temperature coefficient resistor, and the oscillation frequency of the circuit can be rendered insensitive to temperature.
Example 2
This embodiment 2 provides a clock generation circuit for generating a clock signal with a selectable duty ratio; the clock generation circuit comprises a second zero temperature coefficient resistor and a selection capacitor C2; the second zero temperature coefficient resistor is used for temperature compensation; and the selection capacitor C2 is used for controlling the duty ratio.
As shown in fig. 2, the clock generating circuit described in this embodiment 2 includes an eighth P-type MOS transistor MP8, a ninth P-type MOS transistor MP9, a tenth P-type MOS transistor MP10, an eleventh P-type MOS transistor MP11, a twelfth P-type MOS transistor MP12, a thirteenth P-type MOS transistor MP13, a fourteenth P-type MOS transistor MP14, a fifteenth P-type MOS transistor MP15, an eighth N-type MOS transistor MN8, a ninth N-type MOS transistor MN9, a tenth N-type MOS transistor MN10, an eleventh N-type MOS transistor MN11, a twelfth N-type MOS transistor MN12, a thirteenth N-type MOS transistor MN13, a fourteenth N-type MOS transistor MN14, a second zero temperature coefficient resistor, a selection capacitor C2, a third inverter, and a fourth inverter; the second zero temperature coefficient resistor comprises a second positive temperature coefficient resistor RP2 and a second negative temperature coefficient resistor RN2.
One end of the second positive temperature coefficient resistor RP2 is connected with one end of the second negative temperature coefficient resistor RN2; the other end of the second positive temperature coefficient resistor RP2 is connected with the drain electrode of the fourteenth N-type MOS tube MN14 and the grid electrode of the fourteenth N-type MOS tube MN 2; the other end of the second negative temperature coefficient resistor RN2 is connected to the drain of the fifteenth P-type MOS transistor MP15 and the gate of the fifteenth P-type MOS transistor MP 15.
The grid electrode of the eighth P-type MOS transistor MP8, the grid electrode of the tenth P-type MOS transistor MP10 and the grid electrode of the thirteenth P-type MOS transistor MP13 are all connected to the grid electrode of the first fifth P-type MOS transistor MP 15; the drain electrode of the eighth P-type MOS transistor MP8 is connected with the source electrode of the ninth P-type MOS transistor MP 9; the drain electrode of the eighth N-type MOS transistor MN8 is connected with the drain electrode of the tenth P-type MOS transistor MP 10; the source electrode of the eighth N-type MOS transistor MN8 is connected with the drain electrode of the ninth P-type MOS transistor MP 9; the grid electrode of the eleventh P-type MOS tube MP11 is connected with the grid electrode of the eleventh N-type MOS tube MN 11; the drain electrode of the eighth N-type MOS tube MN8 is connected with the drain electrode of the ninth N-type MOS tube MN9 and the grid electrode of the ninth N-type MOS tube MN 9; the gate of the ninth MOS tube MN9 is also connected with a CLKN signal source; one end of the selection capacitor C2 is connected to both the drain of the ninth P-type MOS transistor MP9 and the gate of the eleventh P-type MOS transistor MP11, and the other end of the selection capacitor C2 is connected to GND.
The drain electrode of the eleventh P-type MOS transistor MP11 is connected with the source electrode of the twelfth P-type MOS transistor MP 12; a source electrode of the tenth N-type MOS transistor MN10 is connected to a drain electrode of the eleventh N-type MOS transistor MN 11; the drain electrode of the twelfth P-type MOS tube MP12 is connected with the drain electrode of the tenth N-type MOS tube MN 10; the grid electrode of the twelfth P-type MOS tube MP12 is connected with the grid electrode of the tenth N-type MOS tube MN 10; the grid electrode of the tenth N-type MOS tube MN10 is connected with the grid electrode of the ninth P-type MOS tube MP 9; the drain electrode of the thirteenth P-type MOS transistor MP13 is connected with the source electrode of the fourteenth P-type MOS transistor MP 14; the source electrode of the twelfth N-type MOS tube MN12 is connected with the drain electrode of the thirteenth N-type MOS tube MN 13; the drain electrode of the twelfth N-type MOS tube MN12 is connected with the drain electrode of the fourteenth P-type MOS tube MP 14; the grid electrode of the twelfth N-type MOS tube MN12 is connected with the grid electrode of the fourteenth P-type MOS tube MP14 and both connected with the CLK signal source; the drain electrode of the fourteenth P-type MOS transistor MP14 is connected with the drain electrode of the twelfth P-type MOS transistor MP 12; the drain of the fourteenth P-type MOS transistor MP14 is connected to the input terminal of the third inverter, the output terminal of the third inverter is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter is connected to the DCLK output pin.
The source electrode of the eighth P-type MOS transistor MP8, the source electrode of the tenth P-type MOS transistor MP10, the source electrode of the eleventh P-type MOS transistor MP11, the source electrode of the thirteenth P-type MOS transistor MP13, and the source electrode of the fifteenth P-type MOS transistor MP15 are all connected to VDD; the source electrode of the ninth N-type MOS transistor MN9, the source electrode of the eleventh N-type MOS transistor MN11, the source electrode of the thirteenth N-type MOS transistor MN13, and the source electrode of the fourteenth N-type MOS transistor MN14 are all connected to GND.
The working principle of the clock generation circuit described in this embodiment 2 is basically the same as that of the clock generation circuit described in embodiment 1, but the difference is that the duty ratio of the clock signal is adjusted by setting the selective capacitor C2 and adjusting the capacitance value of the selective capacitor, so as to generate the clock signal with adjustable duty ratio.
The present invention also provides a DC-DC converter including the clock generation circuit described in embodiment 1 or embodiment 2; the DC-DC converter is a switching power supply converter with fixed working frequency.
Clock generation circuit and DC-DC converter, adopt to set up zero temperature coefficient resistance in the clock generation circuit for the oscillation frequency of clock generation circuit shows for the insensitivity to the temperature, effectively avoids the influence of temperature factor to switch power supply circuit, has improved the reliability that clock generation circuit reaches.
The utility model relates to a clock generating circuit, belonging to the field of integrated circuit switch power supply, comprising a clock generating circuit for generating fixed frequency and a clock generating circuit for generating selectable duty ratio by setting a selective capacitor; the clock generation circuit is not influenced by the process, the temperature and the power supply voltage, so that high reliability is ensured, the working frequency of the clock generation circuit has long-time stability, and the clock generation circuit has low sensitivity to the power supply voltage and stability; the DC-DC converter with the clock generation circuit is satisfactory for being used in Internet of things, wireless sensors and embedded devices to reliably work at a fixed frequency.
The above embodiment is only one of the embodiments that can realize the technical solution of the present invention, and the scope of the present invention is not limited only by the embodiment, but also includes any variations, substitutions and other embodiments that can be easily conceived by those skilled in the art within the technical scope of the present invention.
Claims (8)
1. A clock generation circuit is characterized in that the clock generation circuit is used for generating a clock signal with a fixed frequency; the clock generation circuit comprises a first zero temperature coefficient resistor; the first zero temperature coefficient resistor is used for temperature compensation;
the clock generation circuit comprises a first P-type MOS tube MP1, a second P-type MOS tube MP2, a third P-type MOS tube MP3, a fourth P-type MOS tube MP4, a fifth P-type MOS tube MP5, a sixth P-type MOS tube MP6, a seventh P-type MOS tube MP7, a first N-type MOS tube MN1, a second N-type MOS tube MN2, a third N-type MOS tube MN3, a fourth N-type MOS tube MN4, a fifth N-type MOS tube MN5, a sixth N-type MOS tube MN6, a seventh N-type MOS tube MN7, a first zero-temperature coefficient resistor, a capacitor C1, a first phase inverter and a second phase inverter;
one end of the first zero temperature coefficient resistor is connected with the drain electrode of the first N-type MOS tube MN1 and the grid electrode of the first N-type MOS tube MN 1; the other end of the first zero temperature coefficient resistor is connected with the drain electrode of the first P-type MOS tube MP1 and the grid electrode of the first P-type MOS tube MP 1; the drain electrode of the first N-type MOS transistor MN1 is connected with the grid electrode of the first N-type MOS transistor MN1, the grid electrode of the second N-type MOS transistor MN2 and the grid electrode of the seventh N-type MOS transistor MN 7; the grid electrode of the second N-type MOS tube MN2 and the grid electrode of the seventh N-type MOS tube MN7 are connected to the grid electrode of the first N-type MOS tube MN 1;
the drain electrode of the first P-type MOS transistor MP1 is connected with the grid electrode of the first P-type MOS transistor MP1, the grid electrode of the second P-type MOS transistor MP2 and the grid electrode of the sixth P-type MOS transistor MP 6; the grid electrode of the second P-type MOS transistor MP2 and the grid electrode of the sixth P-type MOS transistor MP6 are both connected to the grid electrode of the first P-type MOS transistor MP 1; the drain electrode of the second P-type MOS tube MP2 is connected with the source electrode of the third P-type MOS tube MP 3; the drain electrode of the second N-type MOS tube MN2 is connected with the source electrode of the third N-type MOS tube MN 3; the drain electrode of the third P-type MOS tube MP3 is connected with the drain electrode of the third N-type MOS tube MN 3; the grid electrode of the third P-type MOS transistor MP3 is connected with the grid electrode of the third N-type MOS transistor MN 3;
the grid electrode of the fourth P-type MOS transistor MP4 is connected with the grid electrode of the fifth N-type MOS transistor MN 5; one end of the capacitor C1 is connected with the drain electrode of the third P-type MOS transistor MP3, the drain electrode of the third N-type MOS transistor MN3, the grid electrode of the fourth P-type MOS transistor MP4 and the grid electrode of the fifth N-type MOS transistor MP5, and the other end of the capacitor C1 is connected to GND; the drain electrode of the fourth P-type MOS transistor MP4 is connected with the source electrode of the fifth P-type MOS transistor MP 5; the source electrode of the fourth N-type MOS tube MN4 is connected with the drain electrode of the fifth N-type MOS tube MN 5; the drain electrode of the fifth P-type MOS tube MP5 is connected with the drain electrode of the fourth N-type MOS tube MN 4; the grid electrode of the fifth P-type MOS transistor MP5 is connected with the grid electrode of the fourth N-type MOS transistor MN 4;
the grid electrode of the fifth P-type MOS tube MP5 is connected with the grid electrode of the third N-type MOS tube MN 3; the drain electrode of the sixth P-type MOS transistor MP6 is connected with the source electrode of the seventh P-type MOS transistor MP 7; the source electrode of the sixth N-type MOS tube MN6 is connected with the drain electrode of the seventh N-type MOS tube MN 7; the drain electrode of the sixth N-type MOS transistor MN6 is connected with the drain electrode of the seventh P-type MOS transistor MP 7; the grid electrode of the sixth N-type MOS transistor MN6 is connected with the grid electrode of the seventh P-type MOS transistor MP 7; the drain electrode of the seventh P-type MOS transistor MP7 is connected with the drain electrode of the fifth P-type MOS transistor MP 5; the drain electrode of the seventh P-type MOS tube MP7 is connected with the input end of the first phase inverter, the output end of the first phase inverter is connected with the grid electrode of the third N-type MOS tube MN3, the output end of the first phase inverter is connected with the input end of the second phase inverter, and the output end of the second phase inverter is connected with the grid electrode of the seventh P-type MOS tube MP 7.
2. The clock generation circuit of claim 1, wherein the first zero temperature coefficient resistor comprises a first positive temperature coefficient resistor RP1 and a first negative temperature coefficient resistor RN1; one end of the first positive temperature coefficient resistor RP1 is connected with one end of the first negative temperature coefficient resistor RN1; the other end of the first positive temperature coefficient resistor RP1 is connected with the drain electrode of the first N-type MOS tube MN1 and the grid electrode of the first N-type MOS tube MN 1; the other end of the first negative temperature coefficient resistor RN1 is connected with the drain electrode of the first P-type MOS transistor MP1 and the grid electrode of the first P-type MOS transistor MP 1.
3. The clock generating circuit as claimed in claim 1, wherein the source of the first P-type MOS transistor MP1, the source of the second P-type MOS transistor MP2, the source of the fourth P-type MOS transistor MP4 and the source of the sixth P-type MOS transistor MP6 are all connected to VDD.
4. The clock generating circuit of claim 1, wherein the source of the first N-type MOS transistor MN1, the source of the second N-type MOS transistor MN2, the source of the fifth N-type MOS transistor MN5, and the source of the seventh N-type MOS transistor MN7 are all connected to GND.
5. The clock generating circuit of claim 1, wherein the ratio of the sizes of the first P-type MOS transistor MP1 to the second P-type MOS transistor MP2 is 1; the size ratio of the first N-type MOS transistor MN1 to the second N-type MOS transistor MN2 is 1.
6. A clock generation circuit, wherein the clock generation circuit is configured to generate a clock signal having a selectable duty cycle; the clock generation circuit comprises a second zero temperature coefficient resistor and a selection capacitor C2; the second zero temperature coefficient resistor is used for temperature compensation; the selection capacitor C2 is used for controlling the duty ratio;
the clock generating circuit comprises an eighth P-type MOS tube MP8, a ninth P-type MOS tube MP9, a tenth P-type MOS tube MP10, an eleventh P-type MOS tube MP11, a twelfth P-type MOS tube MP12, a thirteenth P-type MOS tube MP13, a fourteenth P-type MOS tube MP14, a fifteenth P-type MOS tube MP15, an eighth N-type MOS tube MN8, a ninth N-type MOS tube MN9, a tenth N-type MOS tube MN10, an eleventh N-type MOS tube MN11, a twelfth N-type MOS tube MN12, a thirteenth N-type MOS tube MN13, a fourteenth N-type MOS tube MN14, a second zero-temperature coefficient resistor, a selection capacitor C2, a third inverter and a fourth inverter;
one end of the second zero temperature coefficient resistor is connected with the drain electrode of the fourteenth N-type MOS tube MN14 and the grid electrode of the fourteenth N-type MOS tube MN 14; the other end of the second zero temperature coefficient resistor is connected with the drain electrode of the fifteenth P-type MOS transistor MP15 and the grid electrode of the fifteenth P-type MOS transistor MP 15;
the grid electrode of the eighth P-type MOS transistor MP8, the grid electrode of the tenth P-type MOS transistor MP10 and the grid electrode of the thirteenth P-type MOS transistor MP13 are all connected to the grid electrode of the first five P-type MOS transistor MP 15; the drain electrode of the eighth P-type MOS transistor MP8 is connected with the source electrode of the ninth P-type MOS transistor MP 9; the drain electrode of the eighth N-type MOS transistor MN8 is connected with the drain electrode of the tenth P-type MOS transistor MP 10; the source electrode of the eighth N-type MOS transistor MN8 is connected with the drain electrode of the ninth P-type MOS transistor MP 9; the grid electrode of the eleventh P-type MOS tube MP11 is connected with the grid electrode of the eleventh N-type MOS tube MN 11; the drain electrode of the eighth N-type MOS tube MN8 is connected with the drain electrode of the ninth N-type MOS tube MN9 and the grid electrode of the ninth N-type MOS tube MN 9;
one end of the selection capacitor C2 is connected with the drain electrode of the ninth P-type MOS transistor MP9 and the grid electrode of the eleventh P-type MOS transistor MP11, and the other end of the selection capacitor C2 is connected to GND; the drain electrode of the eleventh P-type MOS transistor MP11 is connected with the source electrode of the twelfth P-type MOS transistor MP 12; the source electrode of the tenth N-type MOS tube MN10 is connected with the drain electrode of the eleventh N-type MOS tube MN 11; the drain electrode of the twelfth P-type MOS tube MP12 is connected with the drain electrode of the tenth N-type MOS tube MN 10; the grid electrode of the twelfth P-type MOS tube MP12 is connected with the grid electrode of the tenth N-type MOS tube MN 10; the grid electrode of the tenth N-type MOS transistor MN10 is connected with the grid electrode of the ninth P-type MOS transistor MP 9;
the drain electrode of the thirteenth P-type MOS transistor MP13 is connected with the source electrode of the fourteenth P-type MOS transistor MP 14; the source electrode of the twelfth N-type MOS tube MN12 is connected with the drain electrode of the thirteenth N-type MOS tube MN 13; the drain electrode of the twelfth N-type MOS tube MN12 is connected with the drain electrode of the fourteenth P-type MOS tube MP 14; the grid electrode of the twelfth N-type MOS tube MN12 is connected with the grid electrode of the fourteenth P-type MOS tube MP 14; the drain electrode of the fourteenth P-type MOS transistor MP14 is connected with the drain electrode of the twelfth P-type MOS transistor MP 12; the drain of the fourteenth P-type MOS transistor MP14 is connected to the input of the third inverter, and the output of the third inverter is connected to the input of the fourth inverter.
7. The clock generation circuit of claim 6, wherein the second zero temperature coefficient resistor comprises a second positive temperature coefficient resistor RP2 and a second negative temperature coefficient resistor RN2; one end of the second positive temperature coefficient resistor RP2 is connected with one end of the second negative temperature coefficient resistor RN2; the other end of the second positive temperature coefficient resistor RP2 is connected with the drain electrode of the fourteenth N-type MOS tube MN14 and the grid electrode of the fourteenth N-type MOS tube MN 2; the other end of the second negative temperature coefficient resistor RN2 is connected to the drain of the fifteenth P-type MOS transistor MP15 and the gate of the fifteenth P-type MOS transistor MP 15.
8. A DC-DC converter, characterized in that it comprises a clock generation circuit according to any one of claims 1 to 7; the DC-DC converter is a switching power supply converter with fixed working frequency.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116961623A (en) * | 2023-09-20 | 2023-10-27 | 江苏帝奥微电子股份有限公司 | High-precision duty ratio control circuit and control method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116961623A (en) * | 2023-09-20 | 2023-10-27 | 江苏帝奥微电子股份有限公司 | High-precision duty ratio control circuit and control method thereof |
| CN116961623B (en) * | 2023-09-20 | 2023-12-08 | 江苏帝奥微电子股份有限公司 | High-precision duty ratio control circuit and control method thereof |
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