CN212343748U - Pulse width frequency adjustable CMOS ring oscillator - Google Patents
Pulse width frequency adjustable CMOS ring oscillator Download PDFInfo
- Publication number
- CN212343748U CN212343748U CN201922287122.4U CN201922287122U CN212343748U CN 212343748 U CN212343748 U CN 212343748U CN 201922287122 U CN201922287122 U CN 201922287122U CN 212343748 U CN212343748 U CN 212343748U
- Authority
- CN
- China
- Prior art keywords
- type mos
- mos tube
- input
- electrode
- mos transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
The utility model belongs to the technical field of clock oscillator, specifically disclose an adjustable CMOS ring oscillator of pulse width frequency, contain the output stage circuit that inverted output type Schmidt trigger and be connected with it. The utility model has the advantages of simple structure easily realizes, and adopts N type MOS pipe as delay capacitance, and the area is littleer, and the integrated level is higher. The frequency and the pulse width can be adjusted by adjusting the delay generated by the resistor and the capacitor, the adjustable range is wide, the flexibility of circuit design is improved, and the practicability is high.
Description
Technical Field
The utility model belongs to the technical field of clock oscillator, especially, relate to an adjustable CMOS ring oscillator of pulse width frequency.
Background
The oscillator circuit is a circuit which converts direct current into alternating current signals with certain frequency and outputs the alternating current signals through self-excitation energy, along with the development of integrated circuit technology, the position of the oscillator in a chip is more and more important, and in order to meet the requirements of different occasions on different types of oscillators, novel oscillators with various structures are provided; because of its easy realization, low power consumption, high integration level, small chip area occupation, etc., the ring oscillator is widely applied to integrated circuit chips, such as phase-locked loop circuits, and schmitt triggers are the most important components in the ring oscillator.
At present, a ring oscillator has high frequency and non-adjustable frequency and pulse width, and the frequency and pulse width of actual test have deviation from simulation values due to the influence of process manufacturing, so that the circuit accuracy is reduced.
SUMMERY OF THE UTILITY MODEL
In order to solve the problem, the utility model provides an adjustable CMOS ring oscillator of pulse width frequency, including the output stage circuit of opposition output type Schmidt trigger and being connected with it, its waveform that utilizes the return difference characteristic of Schmidt trigger to inductance capacitance charge-discharge circuit adjusts, has improved the interference killing feature of circuit, even contain a large amount of noises in the input signal, produces good pulse signal behind the Schmidt trigger.
As a further explanation of the above scheme, the reverse phase output schmitt trigger includes a first P-type MOS transistor, a second P-type MOS transistor, a third P-type MOS transistor, a fourth P-type MOS transistor, a first N-type MOS transistor, a second N-type MOS transistor, a third N-type MOS transistor, a fourth N-type MOS transistor, an input end, and an output end;
the source electrode of the first P-type MOS tube, the source electrode of the third P-type MOS tube and the source electrode of the fourth P-type MOS tube are connected with a power supply;
the grid electrode of the first P-type MOS tube, the grid electrode of the second P-type MOS tube, the grid electrode of the first N-type MOS tube and the grid electrode of the second N-type MOS tube are connected with the input end;
the drain electrode of the first P-type MOS tube and the source electrode of the second P-type MOS tube are connected with the drain electrode of the third P-type MOS tube MP 3;
the drain electrode of the second P-type MOS tube, the grid electrode of the fourth P-type MOS tube and the drain electrode of the second N-type MOS tube MN2 are connected with the grid electrode of the fourth N-type MOS tube;
the grid electrode of the third P-type MOS tube, the drain electrode of the fourth P-type MOS tube, the grid electrode of the third N-type MOS tube and the drain electrode of the fourth N-type MOS tube are connected with the output end;
the drain electrode of the first N-type MOS tube and the source electrode of the second N-type MOS tube are connected with the drain electrode of the third N-type MOS tube;
and the source electrode of the first N-type MOS tube, the source electrode of the third N-type MOS tube and the source electrode of the fourth N-type MOS tube are connected with the ground.
As a further explanation of the above scheme, the output stage circuit includes a fifth N-type MOS transistor, a sixth N-type MOS transistor, a first resistor, a second resistor, a first inverter, a second inverter, a third inverter, a three-input and gate, and a two-input and gate;
the input end of the first phase inverter, the input end of the third phase inverter and the input end of the three-input AND gate are connected with the output end of the Schmitt trigger;
the output end of the first inverter is connected with one end of a first resistor;
the other end of the first resistor and the grid electrode of the fifth N-type MOS transistor are connected with the input end of the second inverter;
the output end of the second inverter is connected with the input end of the three-input AND gate;
the output end of the third inverter is connected with the input ends of the two input AND gates;
the output ends of the two input AND gates are connected with one end of a second resistor;
the other end of the second resistor and the grid electrode of the sixth N-type MOS tube are connected with the input end of the Schmitt trigger;
and the drain electrode of the fifth N-type MOS tube, the source electrode of the fifth N-type MOS tube, the drain electrode of the sixth N-type MOS tube and the source electrode of the sixth N-type MOS tube are all connected with the ground.
The utility model has the advantages that: the utility model has the advantages of simple structure easily realizes, and adopts N type MOS pipe as delay capacitance, and the area is littleer, and the integrated level is higher. The frequency and the pulse width can be adjusted by adjusting the delay generated by the resistor and the capacitor, the adjustable range is wide, the flexibility of circuit design is improved, and the practicability is high.
Drawings
FIG. 1: the utility model discloses a circuit structure diagram of a pulse width frequency adjustable CMOS ring oscillator;
Detailed Description
The present invention will be further described with reference to fig. 1 and the following embodiments.
The embodiment provides a pulse width frequency adjustable CMOS ring oscillator, which comprises an inverted output type Schmitt trigger, an output stage circuit connected with the inverted output type Schmitt trigger, and a power supply VDD;
referring to fig. 1, the reverse phase output schmitt trigger includes a first P-type MOS transistor MP1, a second P-type MOS transistor MP2, a third P-type MOS transistor MP3, a fourth P-type MOS transistor MP4, a first N-type MOS transistor MN1, a second N-type MOS transistor MN2, a third N-type MOS transistor MN3, a fourth N-type MOS transistor MN4, an input terminal X, and an output terminal Y;
the connection relationship of each device is as follows: the source of the first P-type MOS tube MP1, the source of the third P-type MOS tube MP3, the source of the fourth P-type MOS tube MP4 are connected with a power supply VDD, the gate of the first P-type MOS tube MP1, the gate of the second P-type MOS tube MP2, the gate of the first N-type MOS tube MN1, and the gate of the second N-type MOS tube MN2 are connected with an input signal X, the drain of the first P-type MOS tube MP1 and the source of the second P-type MOS tube MP2 are connected with the drain of the third P-type MOS tube MP3, the drain of the second P-type MOS tube MP2, the gate of the fourth P-type MOS tube MP4, the drain of the second N-type MOS tube MN 7378 are connected with the gate of the fourth N-type MOS tube MN4, the gate of the third P-type MOS tube MP3, the drain of the fourth P-type MOS tube MP4, the gate of the third N-type MOS tube MN3, the drain of the fourth N-type MOS tube MP2 4, and the drain of the third P-type MOS tube MN 4642 are connected with the drain of the first MN2, the drain of the second N-type MOS tube MN 4642, the source of the first N-type MOS transistor, the source of the third N-type MOS transistor MN3, and the source of the fourth N-type MOS transistor MN4 are connected to ground GND.
The schmitt trigger works as follows, if only the inverter formed by the first P-type MOS transistor MP1 and the first N-type MOS transistor MN1 has forward and reverse conversion levels around VDD/2, and after the second and third P-type MOS transistors MP2 and MP3 and the second and third N-type MOS transistors MN2 and MN3 are added, when the voltage at the X point is 0, the first N-type MOS transistor MN1 and the second N-type MOS transistor MN2 are both turned off, at this time, M in fig. 1 is at a high level, and at the same time, the first P-type MOS transistor MP1 and the second P-type MOS transistor MP2 are both turned on; when the voltage of the point X rises to VTH, the first N-type MOS tube MN1 is turned on, but at the moment, the source end potential of the second N-type MOS tube MN2 is higher, and the first N-type MOS tube MN1 still keeps cut off; the voltage of the point X is increased to VDD/2 and still kept cut off, only when the voltage of the point X is increased to enable the first P-type MOS tube MP1 and the second P-type MOS tube MP2 to be cut off, the voltage of the point M is reduced, the output Y voltage of an inverter formed by the fourth P-type MOS tube MP4 and the fourth N-type MOS tube MN4 is inverted to be changed into high level, the third N-type MOS tube MN3 is conducted to pull the voltage of the source end of the second N-type MOS tube MN2 to be low level, and the voltage of the point M is pulled lower to 0V, so that positive feedback is formed; the same principle is that: when the voltage at the point X is VDD, the first P-type MOS transistor MP1 and the second P-type MOS transistor MP2 are both turned off, and the voltage at the point M is low, and the first N-type MOS transistor MN1 and the second N-type MOS transistor MN2 are both turned on. The voltage of the point X needs to be reduced to cut off the first N-type MOS transistor MN1, the voltage of the point M is increased, the voltage of the point Y is inverted to be low level, the third P-type MOS transistor MP3 is switched on to pull the voltage of the source end of the second P-type MOS transistor MP3 down to high level, and the voltage of the point M is pulled higher; therefore, the forward conduction voltage of the Schmitt trigger is larger than VDD/2, and the reverse conduction voltage is smaller than VDD/2, so that hysteresis characteristics are shown.
Referring to fig. 1, the output stage circuit includes a fifth N-type MOS transistor MN5, a sixth N-type MOS transistor MN5, a first resistor R1, a second resistor R2, a first inverter INV1, a second inverter INV2, a third inverter INV3, a three-input AND gate AND3, AND a two-input AND gate AND 2;
the connection relationship of each device is as follows: an input end of a first inverter INV1, an input end of a third inverter INV3 AND an input end C of a three-input AND gate are connected with an output end Y of the Schmitt trigger, an output end of a first inverter INV1 is connected with one end of a first resistor R1, the other end of the first resistor R1 AND a gate of a fifth N-type MOS tube MN5 are connected with an input end of a second inverter INV2, an output end of the second inverter INV2 is connected with an input end B of a three-input AND gate 3, an input end A of the three-input AND gate AND3 AND an input end A of a two-input AND gate 2 are connected with an enable signal EN, an output end Z of the three-input AND gate 3 is connected with an output signal CLK, an output end of the third inverter INV3 is connected with an input end B of a two-input AND gate 2, an output end Z of the two-input AND gate 2 is connected with one end of a second resistor R2, the other end of the second resistor R2 AND a gate of a sixth N, the drain of the fifth N-type MOS transistor MN5, the source of the fifth N-type MOS transistor MN5, the drain of the sixth N-type MOS transistor MN6, and the source of the sixth N-type MOS transistor MN6 are connected to ground GND.
The output stage circuit is divided into an upper part and a lower part, the upper part and the reverse phase output type Schmitt trigger form an oscillation loop, and the waveform of the loop is rectified by utilizing the return difference characteristic of the Schmitt trigger; the second resistor R2 and the sixth N-type MOS transistor MN6 form a delay unit so as to control the oscillation frequency of the oscillator, and different oscillation frequencies can be realized by adjusting the capacitance value of the second resistor R2 or the sixth N-type MOS transistor MN 6; the lower half part is a clock output circuit; the MOS capacitor formed by the second resistor R2 and the sixth N-type MOS transistor MN6 realizes the frequency regulation function by changing the delay size; the EN signal is used as an enabling signal control end, the oscillator works normally at a high level, and the oscillator does not work at a low level; the lower half part of the output stage realizes the function of adjusting the pulse width, the MOS capacitor formed by the first resistor R1 and the fifth N-type MOS transistor MN5 can generate delay, and different delays can be realized by changing the capacitance value of the MOS capacitor, so that different pulse widths are generated.
The above only is the embodiment of the present invention, not limiting the scope of the present invention, all the equivalent structures or equivalent processes of the present invention are used in the specification and the attached drawings, or directly or indirectly applied to other related technical fields, and the same principle is included in the protection scope of the present invention.
Claims (2)
1. A pulse width frequency adjustable CMOS ring oscillator is characterized by comprising an inverted output type Schmitt trigger and an output stage circuit connected with the inverted output type Schmitt trigger, wherein the output stage circuit comprises a fifth N-type MOS tube, a sixth N-type MOS tube, a first resistor, a second resistor, a first phase inverter, a second phase inverter, a third phase inverter, a three-input AND gate and a two-input AND gate;
the input end of the first phase inverter, the input end of the third phase inverter and the input end of the three-input AND gate are connected with the output end of the Schmitt trigger;
the output end of the first inverter is connected with one end of a first resistor;
the other end of the first resistor and the grid electrode of the fifth N-type MOS transistor are connected with the input end of the second inverter;
the output end of the second inverter is connected with the input end of the three-input AND gate;
the output end of the third inverter is connected with the input ends of the two input AND gates;
the output ends of the two input AND gates are connected with one end of a second resistor;
the other end of the second resistor and the grid electrode of the sixth N-type MOS tube are connected with the input end of the Schmitt trigger;
and the drain electrode of the fifth N-type MOS tube, the source electrode of the fifth N-type MOS tube, the drain electrode of the sixth N-type MOS tube and the source electrode of the sixth N-type MOS tube are all connected with the ground.
2. The CMOS ring oscillator with adjustable pulse width and frequency of claim 1, wherein the reverse phase output type Schmitt trigger comprises a first P type MOS transistor, a second P type MOS transistor, a third P type MOS transistor, a fourth P type MOS transistor, a first N type MOS transistor, a second N type MOS transistor, a third N type MOS transistor, a fourth N type MOS transistor, an input end and an output end;
the source electrode of the first P-type MOS tube, the source electrode of the third P-type MOS tube and the source electrode of the fourth P-type MOS tube are connected with a power supply;
the grid electrode of the first P-type MOS tube, the grid electrode of the second P-type MOS tube, the grid electrode of the first N-type MOS tube and the grid electrode of the second N-type MOS tube are connected with the input end;
the drain electrode of the first P-type MOS tube and the source electrode of the second P-type MOS tube are connected with the drain electrode of the third P-type MOS tube MP 3;
the drain electrode of the second P-type MOS tube, the grid electrode of the fourth P-type MOS tube and the drain electrode of the second N-type MOS tube MN2 are connected with the grid electrode of the fourth N-type MOS tube;
the grid electrode of the third P-type MOS tube, the drain electrode of the fourth P-type MOS tube, the grid electrode of the third N-type MOS tube and the drain electrode of the fourth N-type MOS tube are connected with the output end;
the drain electrode of the first N-type MOS tube and the source electrode of the second N-type MOS tube are connected with the drain electrode of the third N-type MOS tube;
and the source electrode of the first N-type MOS tube, the source electrode of the third N-type MOS tube and the source electrode of the fourth N-type MOS tube are connected with the ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922287122.4U CN212343748U (en) | 2019-12-18 | 2019-12-18 | Pulse width frequency adjustable CMOS ring oscillator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922287122.4U CN212343748U (en) | 2019-12-18 | 2019-12-18 | Pulse width frequency adjustable CMOS ring oscillator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212343748U true CN212343748U (en) | 2021-01-12 |
Family
ID=74063709
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922287122.4U Active CN212343748U (en) | 2019-12-18 | 2019-12-18 | Pulse width frequency adjustable CMOS ring oscillator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN212343748U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110943713A (en) * | 2019-12-18 | 2020-03-31 | 西安航天民芯科技有限公司 | Pulse width frequency adjustable CMOS ring oscillator |
-
2019
- 2019-12-18 CN CN201922287122.4U patent/CN212343748U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110943713A (en) * | 2019-12-18 | 2020-03-31 | 西安航天民芯科技有限公司 | Pulse width frequency adjustable CMOS ring oscillator |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11349456B2 (en) | Ultra-low energy per cycle oscillator topology | |
| CN104242874A (en) | relaxation oscillator | |
| US10862426B2 (en) | Clock generator | |
| CN210431389U (en) | Oscillator circuit and integrated circuit | |
| Mahato | Ultra low frequency CMOS ring oscillator design | |
| CN212343748U (en) | Pulse width frequency adjustable CMOS ring oscillator | |
| CN109286372B (en) | High-precision oscillator circuit | |
| CN101237226A (en) | Oscillator | |
| CN110943713A (en) | Pulse width frequency adjustable CMOS ring oscillator | |
| CN110336558B (en) | Oscillator circuit and integrated circuit | |
| US10826465B2 (en) | Reduced quiescent current PVT compensated oscillator | |
| CN110445467B (en) | Oscillator circuit | |
| CN218335982U (en) | Clock generation circuit and DC-DC converter | |
| CN106992769B (en) | E-TSPC trigger | |
| CN107959476B (en) | Low-power consumption current starvation type oscillator circuit | |
| CN111831043A (en) | High-precision oscillator circuit | |
| CN106339025A (en) | Low-voltage and high-precision band-gap reference circuit applied to node of Internet of Things | |
| CN107086783B (en) | High-power switch circuit | |
| CN109474260B (en) | Digital adjustable oscillator | |
| CN111193475B (en) | High-precision low-power-consumption oscillator | |
| CN114640324A (en) | Low-power-consumption periodic pulse generation circuit | |
| CN107947766A (en) | A kind of pierce circuit of frequency-adjustable applied to Switching Power Supply | |
| CN108599745B (en) | Single-capacitor duty ratio controllable oscillator | |
| Chang et al. | An energy-efficient self-charged crystal oscillator with a quadrature-phase shifter technique | |
| CN117254775B (en) | Self-bias oscillating circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |