CN109286372B - High-precision oscillator circuit - Google Patents

High-precision oscillator circuit Download PDF

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CN109286372B
CN109286372B CN201811093420.3A CN201811093420A CN109286372B CN 109286372 B CN109286372 B CN 109286372B CN 201811093420 A CN201811093420 A CN 201811093420A CN 109286372 B CN109286372 B CN 109286372B
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tube
nmos
pmos
nmos transistor
transistor
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CN109286372A (en
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周泽坤
王韵坤
王安琪
石跃
王卓
张波
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1228—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier comprising one or more field effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1237—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator
    • H03B5/1275—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator having further means for varying a parameter in dependence on the frequency
    • H03B5/129—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator having further means for varying a parameter in dependence on the frequency the parameter being a bias voltage or a power supply

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Abstract

A high-precision oscillator circuit belongs to the technical field of electronic circuits. The oscillator comprises a lower limit comparator, an upper limit comparator, an RS latch, a first current source, a second current source, a first capacitor, a first switch tube and a second switch tube, wherein the R input end of the RS latch is connected with the output end of the lower limit comparator, the S input end of the RS latch is connected with the output end of the upper limit comparator, and the output end of the RS latch is connected with the grids of the first switch tube and the second switch tube and serves as the output end of an oscillator circuit; the drain electrode of the first switching tube is connected with the drain electrode of the second switching tube, the negative input end of the lower limit comparator and the positive input end of the upper limit comparator, and is grounded after passing through the first capacitor, and the source electrode of the first switching tube is grounded after passing through the second current source; the source electrode of the second switching tube is connected with a power supply voltage after passing through the first current source; the positive input end of the lower limit comparator is connected with a lower limit threshold voltage; the negative input terminal of the upper limit comparator is connected to the upper limit threshold voltage. The invention can realize the accurate control of the frequency of the oscillator and has the characteristic of high precision.

Description

High-precision oscillator circuit
Technical Field
The invention belongs to the technical field of electronic circuits, and particularly relates to a high-precision oscillator circuit.
Background
Oscillators are important components of many electronic systems and are widely used in circuits such as power converters, microprocessors, and switching power supplies. The oscillator mainly has the function of providing clock signals with certain frequency for other circuits in the system, and ensures stable and coordinated operation of the circuit system. With the development of electronic circuit technology, new requirements for high-performance and high-stability oscillators are continuously provided.
The circuit of the conventional oscillator is shown in fig. 1, and includes a lower limit comparator COMP1, an upper limit comparator COMP2, an RS latch, a current limiting resistor R, a charging and discharging capacitor C, and a discharging transistor M1. In an initial state, the voltage on the capacitor C is 0V, the lower limit comparator COMP1 outputs a high level, the upper limit comparator COMP2 outputs a low level, the RS latch outputs a low level, the transistor M1 is turned off, and the power supply voltage VDD charges the capacitor C. When the voltage on the capacitor C rises to the lower threshold voltage VTH _ L, the lower limit comparator COMP1 outputs a low level, the RS latch still outputs a low level, and the power supply voltage VDD continues to charge the capacitor C. When the voltage on the capacitor C rises to the upper limit threshold voltage VTH _ H, the upper limit comparator COMP2 outputs a high level, the RS latch outputs a high level, the transistor M1 is turned on, the capacitor C is discharged, and the voltage of the capacitor C falls. When the voltage of the capacitor C drops to the lower threshold voltage VTH _ L, the lower limit comparator COMP1 is turned high, the RS latch outputs a low level, the transistor M1 is turned off, the discharge stops, the power supply voltage VDD starts to charge the capacitor C, and a new cycle starts, thereby generating a sawtooth clock signal on the capacitor C and a square wave clock signal at the output of the RS latch as an output signal of the oscillator circuit.
For a traditional oscillator circuit, the frequency cannot be accurately controlled, the response speed of the lower limit comparator COMP1 and the response speed of the upper limit comparator COMP2 are limited, the capacitor voltage often generates overshoot and undershoot conditions, the sawtooth wave clock signal is deformed, and the oscillator precision is reduced.
Disclosure of Invention
Aiming at the problems that the frequency cannot be accurately controlled and the oscillator is not high in accuracy in the traditional oscillator circuit, the invention provides the high-accuracy oscillator circuit, the first capacitor C1 is charged and discharged by a constant current source to realize the accurate control of the frequency, in addition, an upper limit comparator COMP2 structure with an output clamping position and a lower limit comparator COMP1 structure for enhancing the positive conversion rate are also provided, the overshoot suppression and the undershoot suppression of a sawtooth wave signal generated by the oscillator are realized, and the accuracy of the oscillator is further improved.
The technical scheme of the invention is as follows:
a high-precision oscillator circuit comprises a lower limit comparator COMP1, an upper limit comparator COMP2 and a logic control charge-discharge module,
the logic control charging and discharging module comprises an RS latch, a first current source I1, a second current source I2, a first capacitor C1, a first switch tube M1 and a second switch tube M2, wherein the first switch tube M1 is an N-type switch tube, and the second switch tube M2 is a P-type switch tube;
the R input end of the RS latch is connected with the output end of a lower limit comparator COMP1, the S input end of the RS latch is connected with the output end of an upper limit comparator COMP2, and the output end of the RS latch is connected with the grids of a first switch tube M1 and a second switch tube M2 and serves as the output end of the oscillator circuit;
the drain of the first switch tube M1 is connected to the drain of the second switch tube M2, the negative input terminal of the lower limit comparator COMP1 and the positive input terminal of the upper limit comparator COMP2, and is grounded after passing through the first capacitor C1, and the source thereof is grounded after passing through the second current source I2;
the source electrode of the second switch tube M2 is connected with the power supply voltage VDD after passing through the first current source I1;
the positive input end of the lower limit comparator COMP1 is connected with a lower limit threshold voltage VTH _ L;
the negative input terminal of the upper limit comparator COMP2 is connected to the upper limit threshold voltage VTH _ H.
Specifically, the upper limit comparator COMP2 includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, an eighteenth NMOS transistor MNC1, a nineteenth NMOS transistor MNC2, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, a first inverter INV1, and a second inverter INV2,
the grid electrode of the first NMOS tube MN1 is connected with the grid electrode of the third NMOS tube MN3, the grid electrode and the drain electrode of the eighteenth NMOS tube MNC1 and the first bias current IBIAS1, the drain electrodes of the first NMOS tube MN1 are connected with the grid electrodes of the fourth PMOS tube MP4 and the sixth PMOS tube MP6 and the grid electrode and the drain electrode of the first PMOS tube MP1, and the source electrode of the first NMOS tube MN2 is connected with the drain electrode of the second NMOS tube MN 2;
the grid electrode of the fourth NMOS transistor MN4 is connected with the source electrode of an eighteenth NMOS transistor MNC1, the grid electrodes of a second NMOS transistor MN2 and a seventh NMOS transistor MN7 and the grid electrode and the drain electrode of a nineteenth NMOS transistor MNC2, the drain electrode of the fourth NMOS transistor MN4 is connected with the source electrode of a third NMOS transistor MN3, and the source electrode of the fourth NMOS transistor MN is connected with the source electrodes of a nineteenth NMOS transistor MNC2, a second NMOS transistor MN2, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9 and an eleventh NMOS transistor MN11 and is grounded GND;
the grid electrode of the third PMOS transistor MP3 is connected to the drain electrode of the third NMOS transistor MN3, the grid electrode and the drain electrode of the second PMOS transistor MP2, and the grid electrodes of the fifth PMOS transistor MP5 and the seventh PMOS transistor MP7, the drain electrode thereof is connected to the drain electrode of the fifth NMOS transistor MN5 and the source electrode of the fourth PMOS transistor MP4, and the source electrode thereof is connected to the source electrodes of the first PMOS transistor MP1, the second PMOS transistor MP2, the fifth PMOS transistor MP5 and the seventh PMOS transistor MP7 and is connected to the power supply voltage VDD;
the grid electrode of the fifth NMOS transistor MN5 is used as the negative input end of the upper limit comparator COMP2, and the source electrode of the fifth NMOS transistor MN5 is connected with the source electrode of the sixth NMOS transistor MN6 and the drain electrode of the seventh NMOS transistor MN 7;
the gate of the sixth NMOS transistor MN6 is used as the positive input terminal of the upper limit comparator COMP2, and the drain thereof is connected to the drain of the fifth PMOS transistor MP5 and the source of the sixth PMOS transistor MP 6;
the gate of the ninth NMOS transistor MN9 is connected to the gate and the drain of the eighth NMOS transistor MN8 and the drain of the fourth PMOS transistor MP4, and the drain thereof is connected to the drain of the sixth PMOS transistor MP6, the gate of the eleventh NMOS transistor MN11, and the gate and the drain of the tenth NMOS transistor MN 10;
an input end of the first inverter INV1 is connected to the source of the tenth NMOS transistor MN10 and the drains of the seventh PMOS transistor MP7 and the eleventh NMOS transistor MN11, an output end thereof is connected to an input end of the second inverter INV2, and an output end of the second inverter INV2 is used as an output end of the upper limit comparator COMP 2.
Specifically, the lower limit comparator COMP1 includes a first triode Q1, a second triode Q2, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fifteenth PMOS transistor MP15, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a fifteenth NMOS transistor MN15, a sixteenth NMOS transistor MN16, a seventeenth NMOS transistor MN17, a twentieth NMOS transistor MNC3, a twenty-first NMOS transistor MNC4, a third inverter INV3, a fourth inverter INV4, a resistor R1, and a second capacitor C2,
the grid electrode of the twelfth NMOS tube MN12 is connected with the grid electrode and the drain electrode of the twentieth NMOS tube MNC3 and the second bias current IBIAS2, the drain electrode of the twelfth NMOS tube MN12 is connected with the grid electrodes and the drain electrodes of the ninth PMOS tube MP9, the tenth PMOS tube MP10, the thirteenth PMOS tube MP13 and the eighth PMOS tube MP8, and the source electrode of the twelfth NMOS tube MN13 is connected with the drain electrode of the thirteenth NMOS tube MN 13;
the grid electrode of the seventeenth NMOS transistor MN17 is connected with the grid electrode of the thirteenth NMOS transistor MN13, the source electrode of the twentieth NMOS transistor MNC3 and the grid electrode and the drain electrode of the twenty-first NMOS transistor MNC4, the drain electrode of the seventeenth NMOS transistor MNC is connected with the drain electrode of the fourteenth PMOS transistor MP14 and the input end of the third inverter INV3, and the source electrode of the seventeenth NMOS transistor MN is connected with the source electrodes of the thirteenth NMOS transistor MN13, the fourteenth NMOS transistor MN14, the fifteenth NMOS transistor MN15, the sixteenth NMOS transistor MN16 and the twenty-first NMOS transistor MNC4 and is grounded GND;
a gate of the twelfth PMOS transistor MP12 is used as a positive input end of the lower limit comparator COMP1, a source thereof is connected to a source of the eleventh PMOS transistor MP11 and a drain of the ninth PMOS transistor MP9, and a drain thereof is connected to a drain of the fifteenth NMOS transistor MN15, a gate of the sixteenth NMOS transistor MN16, and one end of the resistor R1;
the grid electrode of the eleventh PMOS tube MP11 is connected with the emitter electrode of the first triode Q1 and the drain electrodes of the tenth PMOS tube MP10 and the sixteenth NMOS tube MN16, passes through the second capacitor C2 and then is connected with the other end of the resistor R1, and the drain electrode of the eleventh PMOS tube MP11 is connected with the grid electrode of the fifteenth NMOS tube MN15 and the grid electrode and the drain electrode of the fourteenth NMOS tube MN 14;
an emitter of the second triode Q2 is used as a negative input end of the lower limit comparator COMP1, a base of the second triode Q2 is connected with a base and a collector of the first triode Q1 and a drain of the thirteenth PMOS transistor MP13, and a collector of the second triode Q2 is connected with a gate and a drain of the fifteenth PMOS transistor MP15 and a gate of the fourteenth PMOS transistor MP 14;
the sources of the eighth PMOS tube MP8, the ninth PMOS tube MP9, the tenth PMOS tube MP10, the thirteenth PMOS tube MP13, the fourteenth PMOS tube MP14 and the fifteenth PMOS tube MP15 are connected with a power supply voltage VDD;
an input end of the fourth inverter INV4 is connected to an output end of the third inverter INV3, and an output end thereof is used as an output end of the lower limit comparator COMP 1.
The invention has the beneficial effects that: the invention utilizes the constant current source to charge and discharge the first capacitor C1, thus realizing the accurate control of the frequency of the oscillator; in addition, through the output clamping of the upper limit comparator COMP2 and the positive slew rate enhancement of the lower limit comparator COMP1, the overshoot suppression and the undershoot suppression of a sawtooth wave signal generated by the oscillator are realized, and the accuracy of the oscillator is ensured.
Drawings
Fig. 1 is a circuit diagram of a conventional oscillator.
Fig. 2 is an overall topology diagram of a high-precision oscillator circuit according to the present invention.
Fig. 3 is a circuit configuration diagram of an upper limit comparator for realizing overshoot suppression in the embodiment.
Fig. 4 is a circuit configuration diagram of a lower limit comparator for realizing undershoot suppression in the embodiment.
Detailed Description
The invention is described in detail below with reference to the figures and specific embodiments.
Fig. 2 shows an overall topology diagram of a high-precision oscillator circuit according to the present invention, which includes a lower limit comparator COMP1, an upper limit comparator COMP2, and a logic control charging/discharging module, where the logic control charging/discharging module includes an RS latch, a first current source I1, a second current source I2, a first capacitor C1, a first switch tube M1, and a second switch tube M2, where the first switch tube M1 is an N-type switch tube, and the second switch tube M2 is a P-type switch tube; the R input end of the RS latch is connected with the output end of a lower limit comparator COMP1, the S input end of the RS latch is connected with the output end of an upper limit comparator COMP2, and the output end of the RS latch is connected with the grids of a first switch tube M1 and a second switch tube M2 and serves as the output end of the oscillator circuit; the drain of the first switch tube M1 is connected to the drain of the second switch tube M2, the negative input terminal of the lower limit comparator COMP1 and the positive input terminal of the upper limit comparator COMP2, and is grounded after passing through the first capacitor C1, and the source thereof is grounded after passing through the second current source I2; the source electrode of the second switch tube M2 is connected with the power supply voltage VDD after passing through the first current source I1; the positive input end of the lower limit comparator COMP1 is connected with a lower limit threshold voltage VTH _ L; the negative input terminal of the upper limit comparator COMP2 is connected to the upper limit threshold voltage VTH _ H.
In an initial state, the voltage of the first capacitor C1 is 0V, the lower limit comparator COMP1 outputs a high level, the upper limit comparator COMP2 outputs a low level, the RS latch outputs a low level, the second switch tube M2 is turned on, the first switch tube M1 is turned off, and the power supply voltage VDD charges the first capacitor C1 through the first current source I1. When the voltage on the first capacitor C1 rises to the lower threshold voltage VTH _ L, the lower comparator COMP1 outputs a low level, the RS latch still outputs a low level, and the first current source I1 continues to charge the first capacitor C1. When the voltage on the first capacitor C1 rises to the upper threshold voltage VTH _ H, the upper comparator COMP2 outputs a high level, the RS latch outputs a high level, the first switch M1 is turned on, the second switch M2 is turned off, the second current source I2 is connected to the first capacitor C1, a constant current discharge path is formed between the first capacitor C1 and the ground, the charge on the first capacitor C1 decreases, the second current source I2 discharges the first capacitor C1, and the voltage on the first capacitor C1 decreases. When the voltage of the first capacitor C1 drops to the lower threshold voltage VTH _ L, the lower limit comparator COMP1 goes high, the RS latch outputs a low level, the second switch M2 is turned on, the first switch M1 is turned off, the power supply voltage VDD starts to charge the first capacitor C1, a new cycle starts, and the voltage across the first capacitor C1 repeats between the upper threshold voltage VTH _ H and the lower threshold voltage VTH _ L, thereby generating the sawtooth clock signal RAMP across the first capacitor C1 and the square wave clock signal CLK at the RS latch output as the output signal of the oscillator circuit. The oscillator clock period T may be expressed as:
Figure BDA0001804943210000051
wherein VTHHIs the voltage value of the upper threshold voltage VTH _ H, VTHLIs the voltage value of the lower threshold voltage VTH _ L, C is the capacitance value of the first capacitor C1, I1And I2Is the current magnitude of the first current source I1 and the second current source I2. According to the invention, the constant current source is used for charging and discharging the first capacitor C1, namely the first current source I1 is used for charging the first capacitor C1, and the second current source I2 is used for discharging the first capacitor C1, so that the time of the rising edge and the falling edge of a sawtooth wave signal output by the oscillator can be controlled, and the frequency can be accurately controlled.
A circuit implementation structure of an upper limit comparator COMP2 is shown in fig. 3, and includes a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a seventh NMOS tube MN6, an eighth NMOS tube MN6, a ninth NMOS tube MN6, a tenth NMOS tube MN6, an eleventh NMOS tube MN6, an eighteenth NMOS tube MNC 6, a nineteenth NMOS tube MNC 6, a first PMOS tube MP6, a second PMOS tube 6, a third PMOS tube MP6, a fourth PMOS tube MP6, a fifth PMOS tube MP6, a sixth PMOS tube MP6, a seventh PMOS tube MP6, a first inverter INV 6 and a second inverter INV 6, a drain of the first NMOS tube MN6 is connected to a drain of the NMOS tube MN6, a drain of the first NMOS tube MN6, a drain of the sixth NMOS tube MN6, a drain of the PMOS tube MN6, a drain of the NMOS tube MN6, a drain of the PMOS tube ibmos 6, and a drain of the PMOS 6 are connected to a drain of the NMOS tube ias 6, and a drain of the NMOS tube 6; the grid electrode of the fourth NMOS transistor MN4 is connected with the source electrode of an eighteenth NMOS transistor MNC1, the grid electrodes of a second NMOS transistor MN2 and a seventh NMOS transistor MN7 and the grid electrode and the drain electrode of a nineteenth NMOS transistor MNC2, the drain electrode of the fourth NMOS transistor MN4 is connected with the source electrode of a third NMOS transistor MN3, and the source electrode of the fourth NMOS transistor MN is connected with the source electrodes of a nineteenth NMOS transistor MNC2, a second NMOS transistor MN2, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9 and an eleventh NMOS transistor MN11 and is grounded GND; the grid electrode of the third PMOS transistor MP3 is connected to the drain electrode of the third NMOS transistor MN3, the grid electrode and the drain electrode of the second PMOS transistor MP2, and the grid electrodes of the fifth PMOS transistor MP5 and the seventh PMOS transistor MP7, the drain electrode thereof is connected to the drain electrode of the fifth NMOS transistor MN5 and the source electrode of the fourth PMOS transistor MP4, and the source electrode thereof is connected to the source electrodes of the first PMOS transistor MP1, the second PMOS transistor MP2, the fifth PMOS transistor MP5 and the seventh PMOS transistor MP7 and is connected to the power supply voltage VDD; the grid electrode of the fifth NMOS transistor MN5 is used as the negative input end of the upper limit comparator COMP2, and the source electrode of the fifth NMOS transistor MN5 is connected with the source electrode of the sixth NMOS transistor MN6 and the drain electrode of the seventh NMOS transistor MN 7; the gate of the sixth NMOS transistor MN6 is used as the positive input terminal of the upper limit comparator COMP2, and the drain thereof is connected to the drain of the fifth PMOS transistor MP5 and the source of the sixth PMOS transistor MP 6; the gate of the ninth NMOS transistor MN9 is connected to the gate and the drain of the eighth NMOS transistor MN8 and the drain of the fourth PMOS transistor MP4, and the drain thereof is connected to the drain of the sixth PMOS transistor MP6, the gate of the eleventh NMOS transistor MN11, and the gate and the drain of the tenth NMOS transistor MN 10; an input end of the first inverter INV1 is connected to the source of the tenth NMOS transistor MN10 and the drains of the seventh PMOS transistor MP7 and the eleventh NMOS transistor MN11, an output end thereof is connected to an input end of the second inverter INV2, and an output end of the second inverter INV2 is used as an output end of the upper limit comparator COMP 2.
In this embodiment, the upper limit comparator COMP2 can realize an overshoot suppression function, and the eighteenth NMOS transistor MNC1, the nineteenth NMOS transistor MNC2, the first PMOS transistor MP1, the second PMOS transistor MP2, the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 constitute a cascode current mirror, so as to mirror the first bias current IBIAS1 to other branches. A fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, an eighth NMOS transistor MN8, and a ninth NMOS transistor MN9 form a first stage of an upper limit comparator COMP2, and the first stage of the upper limit comparator COMP2 is a folded cascode structure. The eleventh NMOS transistor MN11 and the seventh PMOS transistor MP7 form a second stage of the upper limit comparator COMP2, and the second stage of the upper limit comparator COMP2 is a common source structure. In this embodiment, a tenth NMOS transistor MN10 is added between the first stage and the second stage of the upper limit comparator COMP2, and the tenth NMOS transistor MN10 mainly functions to realize transient enhancement when the output of the comparator is turned from low to high, so as to reduce the overshoot of the sawtooth wave of the oscillator. Taking the upper limit threshold voltage VTH _ H as 1.2V as an example, when the voltage on the first capacitor C1 drops below 1.2V, the output of the upper limit comparator COMP2 is turned from high to low, at this time, the tenth NMOS transistor MN10 is turned on, and there is one more current path in the circuit, so that the output of the first stage and the second stage of the upper limit comparator COMP2 is clamped, the gate of the eleventh NMOS transistor MN11 is not pulled to the power supply voltage VDD, and the drain of the eleventh NMOS transistor MN11 is not pulled to the ground GND, which reduces the requirement of the comparator for next-time flipping voltage swing, and realizes transient enhancement of the comparator output from low to high. The specific clamping analysis is as follows.
In some embodiments, the size ratio of the second PMOS transistor MP2, the third PMOS transistor MP3, the fifth PMOS transistor MP5 and the seventh PMOS transistor MP7 in the upper limit comparator COMP2 is preferably:
Figure BDA0001804943210000061
the size ratio of the fourth NMOS transistor MN4 to the seventh NMOS transistor MN7 can be expressed as:
Figure BDA0001804943210000071
therefore, when the positive and negative input voltages of the upper limit comparator COMP2 are equal and all the tubes are in the saturation region, the current in each tube is as follows:
IMN5＝IMN6＝IBIAS
IMP3＝IMP5＝3IBIAS
IMN8＝IMN9＝2IBIAS
IMP7＝IMN11＝IBIAS
wherein IBIASFor the current value of the first bias current IBIAS1, when the voltage on the first capacitor C1 is higher than 1.2V, the tail current flows completely through the fifth NMOS transistor MN5, and no current flows through the sixth NMOS transistor MN 6. The tenth NMOS transistor MN10 is turned on to form a new current path, and a part of the current of the branch where the fifth PMOS transistor MP5 is located flows into the eleventh NMOS transistor MN11 through the tenth NMOS transistor MN10, and then the currents of the ninth NMOS transistor MN9, the tenth NMOS transistor MN10, and the eleventh NMOS transistor MN11 are distributed as follows:
IDS，MN9＝IBIAS
IDS，MN10＝2IBIAS
IDS，MN11＝3IBIAS
the tenth NMOS transistor MN10 operates in a saturation region, the eleventh NMOS transistor MN11 operates in a linear region, and the drain-source currents of the tenth NMOS transistor MN10 and the eleventh NMOS transistor MN11 can be expressed as:
Figure BDA0001804943210000072
Figure BDA0001804943210000073
wherein μ is the mobility of electrons, COXIs the unit area gate oxide capacitance (W/L)MN10And (W/L)MN11Size ratio, V, of the tenth NMOS transistor MN10 and the eleventh NMOS transistor MN11GS,MN10And VGS,MN11Is the gate-source voltage, V, of the tenth NMOS transistor MN10 and the eleventh NMOS transistor MN11DS,MN11Is the drain-source voltage, V, of the eleventh NMOS transistor MN11THIs the threshold voltage of the NMOS transistor.
Gate-source voltage V of eleventh NMOS transistor MN11GS，MN11Drain source voltage VDS，MN11And the gate-source voltage V of the tenth NMOS transistor MN10GS，MN10The following relationships exist:
VGS，MN11-VGS，MN10＝VDS，MN11
in parallel, the drain-source voltage of the eleventh NMOS transistor MN11 has a bit value:
Figure BDA0001804943210000081
as can be seen from the above analysis, in the present embodiment, by adding a current path to the upper limit comparator COMP2, transient enhancement of the upper limit comparator COMP2 is achieved, and voltage overshoot on the first capacitor C1 is suppressed. The first inverter INV1 and the second inverter INV2 are used to shape the output waveform of the upper limit comparator COMP 2.
As shown in fig. 4, a circuit implementation structure of the lower limit comparator COMP1 is provided, which includes a first transistor Q1, a second transistor Q2, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fifteenth PMOS transistor MP15, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a fifteenth NMOS transistor MN15, a sixteenth NMOS transistor MN16, a seventeenth NMOS transistor MN17, a twentieth NMOS transistor MNC3, a twenty first NMOS transistor MNC4, a third inverter INV3, a fourth inverter ibinv 4, a resistor R1 and a second capacitor C2, wherein a gate of the twelfth NMOS transistor MN12 is connected to drain and drain of the twentieth NMOS transistor MN3 and a second bias current of the second NMOS transistor MNs 2, the drain electrode of the PMOS transistor is connected with the grid electrodes of the ninth PMOS transistor MP9, the tenth PMOS transistor MP10 and the thirteenth PMOS transistor MP13 as well as the grid electrode and the drain electrode of the eighth PMOS transistor MP8, and the source electrode of the PMOS transistor is connected with the drain electrode of the thirteenth NMOS transistor MN 13; the grid electrode of the seventeenth NMOS transistor MN17 is connected with the grid electrode of the thirteenth NMOS transistor MN13, the source electrode of the twentieth NMOS transistor MNC3 and the grid electrode and the drain electrode of the twenty-first NMOS transistor MNC4, the drain electrode of the seventeenth NMOS transistor MNC is connected with the drain electrode of the fourteenth PMOS transistor MP14 and the input end of the third inverter INV3, and the source electrode of the seventeenth NMOS transistor MN is connected with the source electrodes of the thirteenth NMOS transistor MN13, the fourteenth NMOS transistor MN14, the fifteenth NMOS transistor MN15, the sixteenth NMOS transistor MN16 and the twenty-first NMOS transistor MNC4 and is grounded GND; the gate of the twelfth PMOS transistor MP12 is used as the positive input end of the lower limit comparator COMP1, the source thereof is connected to the source of the eleventh PMOS transistor MP11 and the drain of the ninth PMOS transistor MP9, and the drain thereof is connected to the drain of the fifteenth NMOS transistor MN15, the gate of the sixteenth NMOS transistor MN16 and one end of the resistor R1; the grid electrode of the eleventh PMOS tube MP11 is connected with the emitter electrode of the first triode Q1 and the drain electrodes of the tenth PMOS tube MP10 and the sixteenth NMOS tube MN16, passes through the second capacitor C2 and then is connected with the other end of the resistor R1, and the drain electrode of the eleventh PMOS tube MP11 is connected with the grid electrode of the fifteenth NMOS tube MN15 and the grid electrode and the drain electrode of the fourteenth NMOS tube MN 14; an emitter of the second triode Q2 serves as a negative input end of the lower limit comparator COMP1, a base of the second triode Q2 is connected with a base and a collector of the first triode Q1 and a drain of the thirteenth PMOS transistor MP13, and a collector of the second triode Q2 is connected with a gate and a drain of the fifteenth PMOS transistor MP15 and a gate of the fourteenth PMOS transistor MP 14; the sources of the eighth PMOS tube MP8, the ninth PMOS tube MP9, the tenth PMOS tube MP10, the thirteenth PMOS tube MP13, the fourteenth PMOS tube MP14 and the fifteenth PMOS tube MP15 are connected with a power supply voltage VDD; an input end of the fourth inverter INV4 is connected to an output end of the third inverter INV3, and an output end thereof is used as an output end of the lower limit comparator COMP 1.
The twentieth NMOS transistor MNC3, the twenty-first NMOS transistor MNC4, the twelfth NMOS transistor MN12 and the thirteenth NMOS transistor MN13 form a cascode current mirror, and the current is accurately mirrored to each branch. The ninth PMOS transistor MP9, the tenth PMOS transistor MP10, the eleventh PMOS transistor MP11, the twelfth PMOS transistor MP12, the fourteenth NMOS transistor MN14, the fifteenth NMOS transistor MN15, and the sixteenth NMOS transistor MN16 form a unity gain buffer, and the miller capacitance, i.e., the second capacitance C2 and the resistance R1, ensure the stability of the unity gain buffer. The unit gain buffer mainly functions to isolate the differential input pair of the lower limit comparator COMP1 from the lower limit threshold voltage VTH _ L, so as to prevent crosstalk caused by the oscillator output, and at the same time, the unit gain buffer can absorb the current of the first transistor Q1.
The lower limit comparator COMP1 adopts base coupling to realize differential input to the first transistor Q1 and the second transistor Q2. The thirteenth PMOS transistor MP13 mirrors the current in the eighth PMOS transistor MP8 to ensure the quiescent operating point of the first transistor Q1. The output current of the lower limit comparator COMP1 and the size of the output capacitor limit the slew rate of the lower limit comparator COMP1, and the triode has strong current capability, so that the slew rate is enhanced. The current of the transistor can be expressed as:
Figure BDA0001804943210000091
wherein, ICIs the collector current of the triode, VBEFor base-emitter voltages of triodes, VTIs a thermal voltage, e is a natural constant, VCEIs the collector-emitter voltage, VAIs the early voltage.
The current of the triode is exponentially related to the base-emitter, when the drain voltages of the first switch tube M1 and the second switch tube M2, that is, the voltage RAMP of the sawtooth wave signal, are lower than the lower limit threshold voltage VTH _ L, the second triode Q2 generates a large pull-down current, the current is mirrored to the fourteenth PMOS tube MP14 through the fifteenth PMOS tube MP15, the drain potential of the fourteenth PMOS tube MP4 is pulled up rapidly, and after being shaped through the third inverter INV3 and the fourth inverter INV4, the lower limit comparator COMP1 outputs a high level, so that the positive slew rate is enhanced, when the voltage on the first capacitor C1 is lower than the lower limit threshold voltage VTH _ L, the lower limit comparator COMP1 can respond rapidly, and voltage undershoot on the first capacitor C1 is suppressed.
In summary, the first capacitor C1 is charged and discharged by the constant current source, so that the frequency of the oscillator is accurately controlled; in addition, a current path is added in the upper limit comparator COMP2, transient enhancement of the upper limit comparator COMP2 is achieved, voltage overshoot on the first capacitor C1 is restrained, the positive slew rate is enhanced through the structure of the lower limit comparator COMP1, quick response can be achieved, voltage undershoot on the first capacitor C1 is restrained, and accuracy of the oscillator is further improved.
Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.

Claims (2)

1. A high-precision oscillator circuit comprises a lower limit comparator (COMP1), an upper limit comparator (COMP2) and a logic control charge-discharge module,
the logic control charging and discharging module is characterized by comprising an RS latch, a first current source (I1), a second current source (I2), a first capacitor (C1), a first switch tube (M1) and a second switch tube (M2), wherein the first switch tube (M1) is an N-type switch tube, and the second switch tube (M2) is a P-type switch tube;
the R input end of the RS latch is connected with the output end of a lower limit comparator (COMP1), the S input end of the RS latch is connected with the output end of an upper limit comparator (COMP2), and the output end of the RS latch is connected with the grids of a first switching tube (M1) and a second switching tube (M2) and serves as the output end of the oscillator circuit;
the drain electrode of the first switch tube (M1) is connected with the drain electrode of the second switch tube (M2), the negative input end of the lower limit comparator (COMP1) and the positive input end of the upper limit comparator (COMP2), and is grounded after passing through the first capacitor (C1), and the source electrode of the first switch tube is grounded after passing through the second current source (I2);
the source electrode of the second switch tube (M2) is connected with a power supply Voltage (VDD) after passing through the first current source (I1);
the positive input end of the lower limit comparator (COMP1) is connected with a lower limit threshold voltage (VTH _ L);
the negative input end of the upper limit comparator (COMP2) is connected with an upper limit threshold voltage (VTH _ H);
the lower limit comparator (COMP1) comprises a first triode (Q1), a second triode (Q2), an eighth PMOS tube (MP8), a ninth PMOS tube (MP9), a tenth PMOS tube (MP10), an eleventh PMOS tube (MP11), a twelfth PMOS tube (MP12), a thirteenth PMOS tube (MP13), a fourteenth PMOS tube (MP14), a fifteenth PMOS tube (MP15), a twelfth NMOS tube (MN12), a thirteenth NMOS tube (MN13), a fourteenth NMOS tube (MN14), a fifteenth NMOS tube (MN15), a sixteenth NMOS tube (MN16), a seventeenth NMOS tube (MN17), a twentieth NMOS tube (MNC3), a twenty first NMOS tube (MNC4), a third inverter (INV3), a fourth inverter (INV4), a resistor (R1) and a second capacitor (C2),
the grid electrode of the twelfth NMOS tube (MN12) is connected with the grid electrode and the drain electrode of the twentieth NMOS tube (MNC3) and the second bias current (IBIAS2), the drain electrode of the twelfth NMOS tube is connected with the grid electrodes and the drain electrode of the ninth PMOS tube (MP9), the tenth PMOS tube (MP10) and the thirteenth PMOS tube (MP13) and the grid electrode and the drain electrode of the eighth PMOS tube (MP8), and the source electrode of the twelfth NMOS tube is connected with the drain electrode of the thirteenth NMOS tube (MN 13);
the grid electrode of a seventeenth NMOS transistor (MN17) is connected with the grid electrode of a thirteenth NMOS transistor (MN13), the source electrode of a twentieth NMOS transistor (MNC3) and the grid electrode and the drain electrode of a twenty-first NMOS transistor (MNC4), the drain electrode of the seventeenth NMOS transistor is connected with the drain electrode of a fourteenth PMOS transistor (MP14) and the input end of a third inverter (INV3), and the source electrode of the seventeenth NMOS transistor is connected with the source electrodes of a thirteenth NMOS transistor (MN13), a fourteenth NMOS transistor (MN14), a fifteenth NMOS transistor (MN15), a sixteenth NMOS transistor (MN16) and a twenty-first NMOS transistor (MNC4) and is Grounded (GND);
a gate of the twelfth PMOS transistor (MP12) is used as a positive input end of the lower limit comparator (COMP1), a source thereof is connected with a source of the eleventh PMOS transistor (MP11) and a drain of the ninth PMOS transistor (MP9), and a drain thereof is connected with a drain of the fifteenth NMOS transistor (MN15), a gate of the sixteenth NMOS transistor (MN16) and one end of the resistor (R1);
the grid electrode of an eleventh PMOS tube (MP11) is connected with the emitter electrode of the first triode (Q1) and the drain electrodes of the tenth PMOS tube (MP10) and the sixteenth NMOS tube (MN16), and is connected with the other end of the resistor (R1) after passing through the second capacitor (C2), and the drain electrode of the eleventh PMOS tube is connected with the grid electrode of the fifteenth NMOS tube (MN15) and the grid electrode and the drain electrode of the fourteenth NMOS tube (MN 14);
an emitter of the second triode (Q2) is used as a negative input end of the lower limit comparator (COMP1), a base electrode of the second triode is connected with a base electrode and a collector of the first triode (Q1) and a drain electrode of the thirteenth PMOS tube (MP13), and a collector electrode of the second triode is connected with a grid electrode and a drain electrode of the fifteenth PMOS tube (MP15) and a grid electrode of the fourteenth PMOS tube (MP 14);
the sources of an eighth PMOS (MP8), a ninth PMOS (MP9), a tenth PMOS (MP10), a thirteenth PMOS (MP13), a fourteenth PMOS (MP14) and a fifteenth PMOS (MP15) are connected with the power supply Voltage (VDD);
the input end of the fourth inverter (INV4) is connected to the output end of the third inverter (INV3), and the output end of the fourth inverter (INV4) is used as the output end of the lower limit comparator (COMP 1).
2. The high precision oscillator circuit according to claim 1, wherein the upper limit comparator (COMP2) comprises a first NMOS transistor (MN1), a second NMOS transistor (MN2), a third NMOS transistor (MN3), a fourth NMOS transistor (MN4), a fifth NMOS transistor (MN5), a sixth NMOS transistor (MN6), a seventh NMOS transistor (MN7), an eighth NMOS transistor (MN8), a ninth NMOS transistor (MN9), a tenth NMOS transistor (MN10), an eleventh NMOS transistor (MN11), an eighteenth NMOS transistor (MNC1), a nineteenth NMOS transistor (MNC2), a first PMOS transistor (MP1), a second PMOS transistor (MP2), a third PMOS transistor (MP3), a fourth PMOS transistor (MP4), a fifth PMOS transistor (MP 96 5), a sixth PMOS transistor (MP6), a seventh transistor (MP7), a first inverter (INV1) and a second inverter (INV2),
the grid electrode of the first NMOS tube (MN1) is connected with the grid electrode of the third NMOS tube (MN3), the grid electrode and the drain electrode of the eighteenth NMOS tube (MNC1) and the first bias current (IBIAS1), the drain electrode of the first NMOS tube is connected with the grid electrodes of the fourth PMOS tube (MP4) and the sixth PMOS tube (MP6) and the grid electrode and the drain electrode of the first PMOS tube (MP1), and the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube (MN 2);
the grid electrode of the fourth NMOS tube (MN4) is connected with the source electrode of the eighteenth NMOS tube (MNC1), the grid electrodes of the second NMOS tube (MN2) and the seventh NMOS tube (MN7) and the grid electrode and the drain electrode of the nineteenth NMOS tube (MNC2), the drain electrode of the fourth NMOS tube is connected with the source electrode of the third NMOS tube (MN3), and the source electrode of the fourth NMOS tube is connected with the source electrodes of the nineteenth NMOS tube (MNC2), the second NMOS tube (MN2), the seventh NMOS tube (MN7), the eighth NMOS tube (MN8), the ninth NMOS tube (MN9) and the eleventh NMOS tube (MN11) and is Grounded (GND);
the grid electrode of the third PMOS tube (MP3) is connected with the drain electrode of the third NMOS tube (MN3), the grid electrode and the drain electrode of the second PMOS tube (MP2) and the grid electrodes of the fifth PMOS tube (MP5) and the seventh PMOS tube (MP7), the drain electrode of the third PMOS tube is connected with the drain electrode of the fifth NMOS tube (MN5) and the source electrode of the fourth PMOS tube (MP4), and the source electrode of the third PMOS tube is connected with the source electrodes of the first PMOS tube (MP1), the second PMOS tube (MP2), the fifth PMOS tube (MP5) and the seventh PMOS tube (MP7) and is connected with a power supply Voltage (VDD);
the grid electrode of the fifth NMOS transistor (MN5) is used as the negative input end of the upper limit comparator (COMP2), and the source electrode of the fifth NMOS transistor is connected with the source electrode of the sixth NMOS transistor (MN6) and the drain electrode of the seventh NMOS transistor (MN 7);
the grid electrode of a sixth NMOS tube (MN6) is used as the positive input end of the upper limit comparator (COMP2), and the drain electrode of the sixth NMOS tube is connected with the drain electrode of a fifth PMOS tube (MP5) and the source electrode of a sixth PMOS tube (MP 6);
the gate of the ninth NMOS transistor (MN9) is connected with the gate and the drain of the eighth NMOS transistor (MN8) and the drain of the fourth PMOS transistor (MP4), and the drain of the ninth NMOS transistor is connected with the drain of the sixth PMOS transistor (MP6), the gate of the eleventh NMOS transistor (MN11) and the gate and the drain of the tenth NMOS transistor (MN 10);
the input end of the first inverter (INV1) is connected to the source of the tenth NMOS transistor (MN10) and the drains of the seventh PMOS transistor (MP7) and the eleventh NMOS transistor (MN11), the output end thereof is connected to the input end of the second inverter (INV2), and the output end of the second inverter (INV2) is used as the output end of the upper limit comparator (COMP 2).
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