CN107276587B - Oscillator circuit with external synchronization function - Google Patents
Oscillator circuit with external synchronization function Download PDFInfo
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- CN107276587B CN107276587B CN201710699918.3A CN201710699918A CN107276587B CN 107276587 B CN107276587 B CN 107276587B CN 201710699918 A CN201710699918 A CN 201710699918A CN 107276587 B CN107276587 B CN 107276587B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/104—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional signal from outside the loop for setting or controlling a parameter in the loop
Abstract
An oscillator circuit with an external synchronization function belongs to the technical field of electronic circuits. The frequency of the oscillator is adjusted by adding an external resistor in the oscillator circuit and adjusting the size of the external resistor; in addition, a synchronous circuit is added, the frequency of the synchronous oscillator is forced to be synchronized through a synchronous control signal SYNC, and a stable and reliable clock signal CLK is obtained; meanwhile, the constant current source is used for discharging the oscillator capacitor, so that the discharging time, namely the time when the clock signal CLK is at a high level, is controllable, and the problem that the circuit cannot respond due to the fact that the high level time of the clock signal CLK is too short can be solved. The oscillator circuit provided by the invention has the advantages of adjustable oscillation frequency, realization of external synchronization, high stability and capability of effectively suppressing the problems of intermodulation interference, electromagnetic interference and the like in the circuit.
Description
Technical Field
The invention belongs to the technical field of electronic circuits, and particularly relates to an oscillator circuit capable of realizing external synchronization.
Background
In the field of electronic circuit technology, oscillators are generally used to provide stable and reliable clock signals for system circuits, so as to ensure stable and coordinated operation of the circuit systems.
The circuit of a conventional oscillator is shown in fig. 1. The circuit comprises the following components: the circuit comprises a charging and discharging capacitor C0, a current limiting resistor R0, a lower limit comparator COMP1, an upper limit comparator COMP2, an RS latch and a discharging MOS transistor MN 0. The non-inverting input end of the lower limit comparator COMP1 is connected with the lower limit threshold voltage Vth _ L, the inverting input end of the lower limit comparator COMP1 is connected with the upper pole plate of the capacitor C0, and the output end of the lower limit comparator COMP1 is connected with the R end of the RS latch; the non-inverting input end of the upper limit comparator COMP2 and the inverting input end of the COMP1 are connected with the upper plate of the capacitor C0, the inverting end of the upper limit comparator COMP2 is connected with the upper limit threshold voltage Vth _ H, and the output end of the upper limit comparator COMP1 is connected with the S end of the RS trigger; the forward output end Q of the RS trigger is connected to the grid of the MN0 tube in turn.
When the upper plate voltage Vc of the capacitor C0 is 0V in the initial state, the output of the lower limit comparator COMP1 is high, the output of the upper limit comparator COMP2 is low, and then the output of the Q end of the RS latch is low, the MN0 tube is cut off, VDD charges the capacitor C0 through the resistor R0, and the voltage on the capacitor C0 starts to rise. When the upper plate voltage Vc of the capacitor C0 rises to the lower threshold voltage Vth _ L, the lower limit comparator COMP1 outputs low, that is, the R end of the RS latch turns low, but the output end Q does not turn and remains low, and the capacitor C0 continues to charge. Until Vc reaches the upper threshold Vth _ H, at this time, the output of the upper limit comparison COMP2 is turned high, the output Q of the RS latch is turned high, and MN0 is turned on. After MN0 is turned on, the charge on the capacitor C0 is discharged rapidly through the MN0 tube, and the voltage Vc of the upper plate of the capacitor C0 is reduced. When Vc is lowered to a lower threshold Vth _ L, the output of the lower limit comparator is turned high, so that the output end Q of the RS trigger is turned low, the MN0 tube is cut off, VDD starts to charge the capacitor C0 through the RC series branch, the voltage Vc of the upper plate of the capacitor C0 starts to rise again, and the next period starts. The oscillation in this cycle generates the oscillation signal CLK.
However, with the conventional oscillator circuit of fig. 1, the charging and discharging frequency cannot be controlled. Moreover, each circuit module in the electronic system has its own specific oscillation frequency, so that the circuit has problems of intermodulation interference, electromagnetic interference and the like, and the circuit function may be affected in severe cases.
Disclosure of Invention
The invention aims to design an oscillator circuit with adjustable oscillation frequency and capable of realizing external synchronization, thereby eliminating the problems of intermodulation interference, electromagnetic interference and the like of the circuit and improving the stability of a clock system.
The technical scheme of the invention is as follows:
an oscillator circuit with external synchronization function is characterized by comprising a lower limit comparator COMP1, an upper limit comparator COMP2, a clamping operational amplifier OP, an RS latch, a buffer, an OR gate, a synchronization circuit, a first NMOS transistor MN1, a second NMOS transistor MN2, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first resistor R1, a second resistor R2, an external resistor RT, a capacitor C and a first current source Ibisa1,
the non-inverting input end of the clamping operational amplifier OP is connected with a clamping reference voltage Vref _ GM, the inverting input end of the clamping operational amplifier OP is connected with the source electrode of a second NMOS tube MN2 after passing through the series structure of a first resistor R1 and a second resistor R2, the output end of the clamping operational amplifier OP is connected with the grid electrode of the second NMOS tube MN2, and the series point of the first resistor R1 and the second resistor R2 is grounded after passing through an external resistor RT;
the grid-drain short circuit of the second PMOS pipe MP2 is connected with the grid of the third PMOS pipe MP3 and the drain of the second NMOS pipe MN2, and the source electrode of the second PMOS pipe MP2 and the source electrode of the third PMOS pipe MP3 are connected with the power supply voltage;
the source electrode of the first PMOS tube MP1 is connected with the drain electrode of the third PMOS tube MP3, and the drain electrode of the first PMOS tube MP1 is connected with the drain electrode of the first NMOS tube MN1, the inverting input end of the lower limit comparator COMP1 and the non-inverting input end of the upper limit comparator COMP 2; the negative electrode of the first current source Ibias1 is connected with the source electrode of the first NMOS tube MN1, the positive electrode thereof is grounded and connected with the lower polar plate of the capacitor C, and the upper polar plate of the capacitor C is used as the output end of the oscillator circuit;
the non-inverting input end of a lower limit comparator COMP1 is connected with a lower threshold voltage Vth _ L, and the output end of the lower limit comparator COMP1 is connected with the R input end of the RS latch after passing through the buffer; an inverting input end of the upper limit comparator COMP2 is connected with the upper threshold voltage Vth _ H, and an output end thereof is connected with a first input end of the or gate; the input end of the synchronous circuit is connected with the synchronous control signal, and the output end of the synchronous circuit is connected with the second input end of the OR gate;
the S input end of the RS latch is connected with the output end of the OR gate, and the output end of the RS latch outputs a clock signal CLK and is connected with the grid electrodes of the first NMOS tube MN1 and the first PMOS tube MP 1.
Specifically, the synchronization circuit includes a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a first capacitor C1, a second capacitor C2, a third resistor R3, a fourth resistor R4, a second current source Ibias2, a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, and a NAND gate NAND,
one end of the third resistor R3 is connected with the synchronous control signal, and the other end is connected with the drain electrode of the fourth NMOS transistor MN4 and the grid electrode of the sixth NMOS transistor MN 6;
the grid-drain short circuit of the third NMOS tube MN3 is connected with the grids of the fourth NMOS tube MN4 and the fifth NMOS tube MN5 and the anode of a second current source Ibias2, and the cathode of the second current source Ibias2 is connected with the power voltage;
the gate-drain short circuit of the fourth PMOS transistor MP4 is connected with the drain of the fifth NMOS transistor MN5 and the gate of the fifth PMOS transistor MP 5;
the input end of the first inverter INV1 is connected to the drains of the fifth PMOS transistor MP5 and the sixth NMOS transistor MN6, and the output end thereof is connected to the gates of the sixth PMOS transistor MP6 and the seventh NMOS transistor MN7 and the first input end of the nand gate;
the source electrode of the sixth PMOS transistor MP6 is connected to the power supply voltage through the fourth resistor R4, and the drain electrode thereof is connected to the drain electrode of the seventh NMOS transistor MN7 and the input end of the second inverter INV2, and is grounded through the first capacitor C1;
the input end of the third inverter INV3 is connected to the output end of the second inverter INV2, passes through the second capacitor C2, and is grounded, and the output end of the third inverter INV3 is connected to the second input end of the NAND gate NAND;
the input end of the fourth inverter INV4 is connected to the output end of the NAND gate NAND, and the output end of the fourth inverter is used as the output end of the synchronization circuit to output the narrow PULSE modulation signal PULSE;
the sources of the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are connected with the power supply voltage, and the sources of the third NMOS tube MN3, the fourth NMOS tube MN4, the fifth NMOS tube MN5, the sixth NMOS tube MN6 and the seventh NMOS tube MN7 are grounded.
The invention has the beneficial effects that: the oscillator can adjust the self frequency by adjusting the external resistor RT; meanwhile, an external synchronization signal SYNC can be used for forcibly setting the oscillation frequency to obtain a stable and reliable clock signal CLK; in addition, because the oscillator capacitor C is discharged by using the constant current source, the discharge time, namely the time when the clock signal CLK is at a high level, is controllable, and the problem that the circuit cannot respond because the high level time of the clock signal CLK is too short can not occur; the oscillator circuit provided by the invention has high stability, and can effectively inhibit the problems of intermodulation interference, electromagnetic interference and the like in the circuit.
Drawings
FIG. 1 is a circuit schematic of a conventional oscillator;
FIG. 2 is a schematic diagram of an oscillator circuit with external synchronization function according to the present invention;
FIG. 3 is a circuit diagram of a synchronization circuit in an embodiment;
FIG. 4 is a diagram illustrating the synchronization function of the present invention;
FIG. 5 is a timing diagram illustrating the frequency of the oscillator controlled by the SYNC control signal SYNC according to the present invention.
Detailed Description
The invention is described in detail below with reference to the figures and specific embodiments.
As shown in fig. 2, the oscillator circuit diagram with external synchronization function provided by the present invention is shown, wherein the RS latch is active at low level, the first current source Ibias1 is a constant current source, the second PMOS transistor MP2 and the third PMOS transistor MP3 form a current mirror structure, and since the output terminal of the clamping operational amplifier OP is connected back to the inverting input terminal of the clamping operational amplifier OP through the second NMOS transistor MN2, the second resistor R2 and the first resistor R1 to form negative feedback, after the external resistor RT is connected to the ground at the serial point of the first resistor R1 and the second resistor R2, the voltage across the external resistor RT is the clamping reference voltage Vref _ GM connected to the non-inverting input terminal of the clamping operational amplifier OP. So that the external resistor RT has a current of
Since the current charges the capacitor C through the current mirror formed by the second PMOS transistor MP2 and the third PMOS transistor MP3, the charging current of the capacitor C is obtained as follows:
k1 is the mirror image ratio of the second PMOS tube MP2 and the third PMOS tube MP3, Vref _ GM is the clamping reference voltage, and RT is the external resistor.
And the capacitor C is discharged by the first constant current source Ibias1, so that the discharge current of the capacitor C is obtained as follows:
Ioff＝Ibias1(2)
the oscillator charging time is therefore:
where C is the oscillator capacitance, Vth _ H is the upper comparator threshold, and Vth _ L is the lower comparator threshold.
Discharge time of
The oscillator frequency period is therefore:
where T is the oscillator period and fsw is the oscillator frequency.
The expressions (1), (2), (3), (4) and (5) are solved to obtain the expression of the external resistance RT and the oscillator frequency fsw:
as shown in fig. 3, which is a circuit structure of the synchronous circuit in the embodiment, the third NMOS transistor MN3 forms a current mirror structure with the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5, the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 also form a current mirror structure, and the second current source Ibias2 is a constant current source. When the externally given synchronization control signal SYNC is low, the fourth NMOS transistor MN4 is pushed into the linear region, the gate potential of the sixth NMOS transistor MN6 is low, so that the sixth NMOS transistor MN6 is turned off, the input terminal of the first inverter INV1 is high, and the output thereof is low. When the synchronous control signal SYNC is high, the fourth PMOS transistor MP4 works in the saturation region, and in this embodiment, the ratio of the third NMOS transistor MN3 to the fourth NMOS transistor MN4 to the fifth NMOS transistor MN5 is 1:1:1, so the current on the third resistor R3 is Ibias2, and the gate voltage of the sixth NMOS transistor MN6 is VSYNC-Ibias2×R3So that the sixth NMOS transistor MN6 is turned on, the input terminal of the first inverter INV1 is pulled low, and its output is high.
From the above analysis, it can be known that the output of the first inverter INV1 is a periodic square wave signal with the same frequency and phase as the synchronization control signal SYNC, and only the external synchronization control signal SYNC level is converted into the circuit internal level. Because one side of the output signal of the first inverter INV1 is directly connected to one input terminal of the NAND gate NAND, and the other side of the output signal is connected to the other input terminal of the NAND gate NAND after a short delay is generated by the second inverter INV2, the third inverter INV3, the first capacitor C1 and the second capacitor C2. There is a delay difference between the two input square wave signals of the NAND gate NAND, and thus a wide PULSE modulation signal having the same frequency as the synchronization control signal SYNC is generated, and the signal becomes a narrow PULSE modulation signal PULSE after passing through the fourth inverter INV 4.
Fig. 4 shows a schematic diagram of an oscillator circuit after the synchronization control signal SYNC is added, and fig. 2 shows a specific circuit.
Fig. 5 shows a timing chart of the synchronous control signal SYNC controlling the oscillator frequency, where Va and Vb signals are two input signals of the NAND gate NAND, the narrow PULSE modulation signal PULSE is a modulation signal output by the synchronous circuit after the synchronous control signal SYNC is added, and is a narrow PULSE signal, Vc is the voltage on the oscillator capacitor, and CLK is the output clock signal. For the specific circuit of fig. 2, the circuit modulation signal PULSE generated by the synchronization circuit is connected to one input terminal of the OR gate OR, and the other input terminal is the output of the upper limit comparator COMP 2. When the frequency of the synchronous control signal SYNC is higher than the working frequency of the synchronous control signal SYNC, and the oscillator is charged but does not reach the upper threshold voltage Vth _ H, the PULSE modulation signal PULSE signal is turned high, no matter how the output of the upper limit comparator COMP2 is, the output of the OR gate OR outputs high level, that is, the S end of the RS flip-flop is set to 1, the output end of the RS flip-flop is turned high, the capacitor C starts to discharge in advance, when the output of the lower limit comparator COMP1 is turned low when the output of the RS flip-flop is discharged to the lower threshold Vth _ L, the R end of the RS flip-flop is pulled high, the output end Q of the RS flip-flop is set to 0, the oscillator starts to be charged, and thus, a period is completed, and the synchronization of the oscillator frequency and the synchronous control signal SYNC.
The invention has the advantages that the required oscillator frequency can be obtained by adjusting the external resistor RT according to the formula (6), and the adjusting range is 100KHz-600 KHz; meanwhile, the oscillator capacitor C is discharged by using the constant current source, so that the discharge time, namely the time when the clock signal CLK is at a high level, is controllable, and the problem that the circuit cannot respond due to the fact that the high level time of the clock signal CLK is too short can be solved. Meanwhile, the oscillator can force the frequency of the synchronous oscillator by adding a synchronous control signal SYNC additionally, and a stable and reliable clock signal CLK can be obtained. The synchronization function of the invention can be widely applied to various oscillator circuits and is compatible with all the components of synchronous electronics.
Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (1)
1. An oscillator circuit with an external synchronization function is characterized by comprising a lower limit comparator (COMP1), an upper limit comparator (COMP2), a clamping operational amplifier (OP), an RS latch, a buffer, an OR gate, a synchronization circuit, a first NMOS (N-channel metal oxide semiconductor) tube (MN1), a second NMOS (N-channel metal oxide semiconductor) tube (MN2), a first PMOS (MP1), a second PMOS (MP2), a third PMOS (MP3), a first resistor (R1), a second resistor (R2), an external Resistor (RT), a capacitor (C) and a first current source (Ibisa1),
the non-inverting input end of the clamping operational amplifier (OP) is connected with a clamping reference voltage (Vref _ GM), the inverting input end of the clamping operational amplifier is connected with the source electrode of a second NMOS tube (MN2) through the series structure of a first resistor (R1) and a second resistor (R2), the output end of the clamping operational amplifier is connected with the grid electrode of the second NMOS tube (MN2), and the series point of the first resistor (R1) and the second resistor (R2) is grounded through an external Resistor (RT);
the gate-drain short circuit of the second PMOS tube (MP2) is connected with the gate of the third PMOS tube (MP3) and the drain of the second NMOS tube (MN2), and the source of the second PMOS tube (MP2) and the source of the third PMOS tube (MP3) are connected with the power supply voltage;
the source electrode of the first PMOS tube (MP1) is connected with the drain electrode of the third PMOS tube (MP3), and the drain electrode of the first PMOS tube (MP 3526) is connected with the drain electrode of the first NMOS tube (MN1), the inverted input end of the lower limit comparator (COMP1) and the non-inverted input end of the upper limit comparator (COMP 2); the negative electrode of the first current source (Ibias1) is connected with the source electrode of the first NMOS tube (MN1), the positive electrode of the first current source is grounded and connected with the lower polar plate of the capacitor (C), and the upper polar plate of the capacitor (C) is used as the output end of the oscillator circuit;
the non-inverting input end of a lower limit comparator (COMP1) is connected with a lower threshold voltage (Vth _ L), and the output end of the lower limit comparator is connected with the R input end of the RS latch after passing through the buffer; the inverting input end of the upper limit comparator (COMP2) is connected with the threshold voltage (Vth _ H), and the output end of the upper limit comparator is connected with the first input end of the OR gate; the input end of the synchronous circuit is connected with the synchronous control signal, and the output end of the synchronous circuit is connected with the second input end of the OR gate;
the S input end of the RS latch is connected with the output end of the OR gate, and the output end of the RS latch outputs a clock signal (CLK) and is connected with the grid electrodes of the first NMOS tube (MN1) and the first PMOS tube (MP 1);
the synchronous circuit comprises a third NMOS transistor (MN3), a fourth NMOS transistor (MN4), a fifth NMOS transistor (MN5), a sixth NMOS transistor (MN6), a seventh NMOS transistor (MN7), a fourth PMOS transistor (MP4), a fifth PMOS transistor (MP5), a sixth PMOS transistor (MP6), a first capacitor (C1), a second capacitor (C2), a third resistor (R3), a fourth resistor (R4), a second current source (Ibias2), a first inverter (INV1), a second inverter (INV2), a third inverter (INV3), a fourth inverter (INV4) and a NAND gate (NAND),
one end of the third resistor (R3) is connected with the synchronous control signal, and the other end of the third resistor is connected with the drain electrode of the fourth NMOS transistor (MN4) and the grid electrode of the sixth NMOS transistor (MN 6);
the grid-drain of the third NMOS tube (MN3) is in short circuit connection with the grids of the fourth NMOS tube (MN4) and the fifth NMOS tube (MN5) and the anode of the second current source (Ibias2), and the cathode of the second current source (Ibias2) is connected with the power voltage;
the gate-drain short circuit of the fourth PMOS tube (MP4) is connected with the drain electrode of the fifth NMOS tube (MN5) and the gate electrode of the fifth PMOS tube (MP 5);
the input end of the first inverter (INV1) is connected with the drains of the fifth PMOS transistor (MP5) and the sixth NMOS transistor (MN6), and the output end thereof is connected with the gates of the sixth PMOS transistor (MP6) and the seventh NMOS transistor (MN7) and the first input end of the nand gate;
the source electrode of the sixth PMOS tube (MP6) is connected with the power voltage through a fourth resistor (R4), and the drain electrode of the sixth PMOS tube is connected with the drain electrode of the seventh NMOS tube (MN7) and the input end of the second inverter (INV2) and is grounded through a first capacitor (C1);
the input end of the third inverter (INV3) is connected with the output end of the second inverter (INV2) and is grounded after passing through the second capacitor (C2), and the output end of the third inverter is connected with the second input end of the NAND gate (NAND);
the input end of the fourth inverter (INV4) is connected with the output end of the NAND gate (NAND), and the output end of the fourth inverter is used as the output end of the synchronous circuit to output a narrow PULSE modulation signal (PULSE);
the source electrodes of the fourth PMOS tube (MP4) and the fifth PMOS tube (MP5) are connected with power supply voltage, and the source electrodes of the third NMOS tube (MN3), the fourth NMOS tube (MN4), the fifth NMOS tube (MN5), the sixth NMOS tube (MN6) and the seventh NMOS tube (MN7) are grounded.
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| CN108777571B (en) * | 2018-07-27 | 2024-04-02 | 无锡雷利电子控制技术有限公司 | Signal generation circuit structure |
| CN109496012B (en) * | 2018-11-20 | 2020-07-10 | 电子科技大学 | Variable turn-off time control circuit for L ED constant current driving device |
| CN109660220A (en) * | 2018-12-19 | 2019-04-19 | 四川长虹电器股份有限公司 | Amplifier output signal clamp voltage control circuit |
| CN111181552B (en) * | 2020-01-08 | 2023-03-24 | 电子科技大学 | Bidirectional frequency synchronous oscillator circuit |
| CN111193500B (en) * | 2020-01-15 | 2023-04-07 | 电子科技大学 | Oscillator capable of synchronizing external clock |
| CN111629463B (en) * | 2020-06-12 | 2022-06-17 | 深圳昂瑞微电子技术有限公司 | Oscillating circuit |
| CN113452353B (en) * | 2021-06-29 | 2023-06-09 | 深圳市长运通半导体技术有限公司 | Oscillator with adjustable frequency and external synchronous clock function |
| CN114629440B (en) * | 2022-05-17 | 2022-09-13 | 深圳市泰德半导体有限公司 | Programmable oscillator circuit and power management chip |
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