CN111193500B - Oscillator capable of synchronizing external clock - Google Patents
Oscillator capable of synchronizing external clock Download PDFInfo
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- CN111193500B CN111193500B CN202010039806.7A CN202010039806A CN111193500B CN 111193500 B CN111193500 B CN 111193500B CN 202010039806 A CN202010039806 A CN 202010039806A CN 111193500 B CN111193500 B CN 111193500B
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- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
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Abstract
An oscillator capable of synchronizing an external clock belongs to the technical field of electronic circuits. According to the oscillator provided by the invention, the synchronous external clock module is additionally arranged, when the external clock is required to be synchronized, the output clock of the oscillator is synchronized to the external clock, and when the external clock is not required to be synchronized, the clock signal is generated inside the oscillator, so that the function of synchronizing the external clock is realized, and the consistency of cooperative work of a plurality of chips is facilitated; in addition, only the rising edge of an external clock is synchronized, the duty ratio is not synchronized together, and the duty ratio is determined by the narrow pulse width and the clock period; the comparator is improved, so that the error overturning of the comparator during the clock synchronization is avoided; frequency dithering functions are also added to optimize the EMI characteristics of the system.
Description
Technical Field
The invention belongs to the technical field of electronic circuits, and relates to an oscillator which can realize the function of synchronizing an external clock, is provided with an oscillator which can realize the frequency jittering function, and can be suitable for a BUCK circuit, a BOOST circuit or other circuits needing system clocks.
Background
In the BUCK circuit of the switching power supply, under the control mode of pulse width modulation PWM, the starting of an upper tube is determined by a system clock, and the closing of the upper tube is determined by a PWM comparator and peak current limit comparison. Therefore, in the BUCK chip, a module for generating a system clock is required. When a plurality of chips work cooperatively, in order to ensure the working consistency of the chips, the same external clock is used for control, and the error of the internal clock caused by various non-ideal factors is avoided.
In a System On Chip (SOC) with high integration, electromagnetic interference (EMI) characteristics of a BUCK power supply are receiving particular attention, and particularly, the switching frequency of a switching power supply is becoming higher. BUCK power supplies are widely used due to their high efficiency, but have the disadvantage of high output ripple and noise ratio, which may affect sensitive analog modules that are powered and sensitive analog modules that are integrated around the BUCK power supplies.
The noise of the BUCK circuit can be embodied in EMI, which is specified by electromagnetic compatibility (EMC) standards. EMI of BUCKs can be divided into conducted EMI and radiated EMI. Conducted EMI is primarily propagated through the signal lines at a lower frequency. Radiated EMI propagates through a spatial electromagnetic field, with higher frequencies. The energy spikes of EMI are mainly distributed at the switching frequency of BUCK and the frequency multiplication thereof, and the EMC standard is achieved by optimizing the energy spikes of EMI. Currently, the EMI optimization methods include segment driving, frequency dithering, etc. The segmented drive optimizes EMI by controlling di/dt and dv/dt of the power tube, and the frequency jitter is an energy spike that disperses EMI by dithering the switching frequency.
A conventional system clock generation circuit is shown in fig. 1. INTVCC is the supply voltage. The operational amplifier OP, the first NMOS transistor MN1 and the frequency selection resistor RT form an equivalent current source, and Vref1 is a first reference voltage. The voltage at the upper end of the frequency selection resistor RT is clamped to the first reference voltage Vref1 by the operational amplifier OP, and the current I = Vref1/RT is generated at this time. After the charging current I passes through a current mirror image formed by the first PMOS tube MP1 and the second MOS tube MP2, the timing capacitor Cc is charged, until the voltage on the timing capacitor Cc reaches a second reference voltage Vref2, the comparator CMP is turned over, and a control signal is generated to control the second NMOS tube MN2 to discharge the timing capacitor Cc, so that a clock period is formed. After the discharge is completed, the comparator CMP is turned over, and the charging current I continues to charge the timing capacitor Cc. And generating a system clock in a repeated way.
When the chips work in cooperation, if respective system internal clocks are adopted, even if the same frequency-selecting resistor RT is selected, errors may be generated in the respective system internal clocks due to the influence of temperature, core and the working environment inside the chips, thereby affecting the working consistency of the chips.
Disclosure of Invention
Aiming at the problems of chip consistency and low electromagnetic interference (EMI) characteristic caused by the fact that the traditional oscillators respectively generate system internal clocks, the invention provides the oscillator, which increases the logic of a synchronous clock and can realize the combined use of multiple chips; the comparator is improved, so that the error overturning of the comparator during the clock synchronization is avoided; frequency dithering functions are also added to optimize the EMI characteristics of the system.
The technical scheme of the invention is as follows:
an oscillator capable of synchronizing external clock comprises an operational amplifier, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a timing capacitor and a comparator,
the non-inverting input end of the operational amplifier is connected with a first reference voltage, the inverting input end of the operational amplifier is connected with the source electrode of the first NMOS tube and is connected with the frequency-selecting resistor, and the output end of the operational amplifier is connected with the grid electrode of the first NMOS tube;
the grid source of the first PMOS tube is in short circuit and is connected with the drain electrode of the first NMOS tube and the grid electrode of the second PMOS tube, and the source electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube and power supply voltage;
the inverting input end of the comparator is connected with a second reference voltage, and the positive input end of the comparator is connected with the drain electrode of the second PMOS tube and the drain electrode of the second NMOS tube and is grounded after passing through the timing capacitor;
the source electrode of the second NMOS tube is grounded;
the oscillator also comprises a synchronous external clock module, the synchronous external clock module comprises a first resistor, an odd number of first Schmitt triggers, a second Schmitt trigger, a third Schmitt trigger, a first capacitor, a second capacitor, a third capacitor, a first phase inverter, a second phase inverter, a third phase inverter, a fourth phase inverter, a fifth phase inverter, a NAND gate and a third PMOS tube,
one end of the first resistor is used as a first input end of the synchronous external clock module and is connected with an external clock signal, and the other end of the first resistor is grounded through a third capacitor on one hand and is connected with the input end of a fifth inverter through the odd-number first Schmitt triggers in cascade connection on the other hand;
the first input end of the NAND gate is connected with the output end of the fifth phase inverter and the input end of the fourth phase inverter, the second input end of the NAND gate is connected with the output end of the fourth phase inverter and is grounded after passing through the first capacitor, and the output end of the NAND gate is connected with the grid electrode of the third PMOS tube;
the source electrode of the third PMOS tube is connected with power supply voltage, and the drain electrode of the third PMOS tube is connected with the output end of the first phase inverter and the input end of the second phase inverter and is grounded after passing through the second capacitor;
the input end of the second Schmitt trigger is used as the second input end of the synchronous external clock module and is connected with the output end of the comparator, and the output end of the second Schmitt trigger is connected with the input end of the first phase inverter;
the input end of the third Schmitt trigger is connected with the output end of the second phase inverter, and the output end of the third Schmitt trigger is used as the output end of the oscillator and is connected with the grid electrode of the second NMOS tube after passing through the third phase inverter;
the output signal of the comparator is constantly at a low level when the oscillator synchronizes the external clock.
Specifically, the comparator comprises a second resistor, a third resistor, a fourth capacitor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor and a twelfth PMOS transistor, and the comparator comprises two inverting input ends and a non-inverting input end;
the grid electrode of the sixth NMOS tube is used as the non-inverting input end of the comparator, the source electrodes of the sixth NMOS tube are connected with the source electrodes of the seventh NMOS tube and the eighth NMOS tube and the drain electrode of the third NMOS tube, and the drain electrode of the sixth NMOS tube is connected with the drain electrode of the fifth PMOS tube, the grid electrode and the drain electrode of the seventh PMOS tube and the grid electrode of the sixth PMOS tube;
the grid electrode of the seventh NMOS tube is used as a first inverted input end of the comparator and is connected with the second reference voltage, and the drain electrode of the seventh NMOS tube is connected with the drain electrode of the eighth NMOS tube, the grid electrode and the drain electrode of the fourth PMOS tube and the grid electrode of the fifth PMOS tube;
the grid electrode of the eighth NMOS tube is used as a second inverting input end of the comparator and is connected with the first control signal;
the first control signal is constantly at a low level when the oscillator is not synchronized with the external clock, and is turned to a high level when the oscillator is synchronized with the external clock;
the source electrode of the sixth PMOS tube is connected with the source electrodes of the fourth PMOS tube and the fifth PMOS tube and is connected with power supply voltage, and the drain electrode of the sixth PMOS tube is connected with the source electrode of the seventh PMOS tube and one end of the fourth resistor and serves as the output end of the comparator;
the other end of the fourth resistor is grounded;
the grid electrode of the fifth NMOS tube is connected with the grid electrode and the drain electrode of the fourth NMOS tube and the grid electrode of the third NMOS tube and is connected with a third bias voltage, the source electrode of the fifth NMOS tube is connected with the source electrodes of the third NMOS tube, the fourth NMOS tube, the tenth NMOS tube and the eleventh NMOS tube and is grounded, and the drain electrode of the fifth NMOS tube is connected with the source electrode of the twelfth NMOS tube and the second inverting input end of the comparator;
the grid electrode of the ninth NMOS tube is connected with the first bias voltage, the source electrode of the ninth NMOS tube is grounded after passing through the second resistor, and the drain electrode of the ninth NMOS tube is connected with the grid electrode of the tenth NMOS tube, the drain electrode of the eleventh PMOS tube and one end of the fourth capacitor;
the other end of the fourth capacitor is grounded through a third resistor;
the grid electrode of the eleventh PMOS tube is connected with the output end of the NAND gate in the synchronous external clock module, and the source electrode of the eleventh PMOS tube is connected with the power supply voltage;
the grid electrode of the ninth PMOS tube is connected with the grid electrode of the tenth PMOS tube, the grid electrode of the twelfth PMOS tube, the grid electrode and the drain electrode of the eighth PMOS tube and the second bias voltage, the drain electrode of the ninth PMOS tube is connected with the drain electrode of the tenth NMOS tube and the grid electrode of the eleventh NMOS tube, and the source electrode of the ninth PMOS tube is connected with the source electrodes of the eighth PMOS tube, the tenth PMOS tube and the twelfth PMOS tube and is connected with the power supply voltage;
the grid electrode of the twelfth NMOS tube is connected with the drain electrodes of the tenth PMOS tube and the eleventh NMOS tube, and the drain electrode of the twelfth NMOS tube is connected with the drain electrode of the twelfth PMOS tube.
Specifically, the operational amplifier comprises a fifth resistor, a fifth capacitor, a sixth capacitor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a thirteenth NMOS transistor and a fourteenth NMOS transistor, and the operational amplifier comprises two non-inverting input terminals and one inverting input terminal;
a grid electrode of the fifteenth PMOS tube is used as an inverting input end of the operational amplifier, a drain electrode of the fifteenth PMOS tube is connected with a drain electrode of the fourteenth NMOS tube, one end of the fifth resistor and one end of the sixth capacitor, and a source electrode of the fifteenth PMOS tube is connected with source electrodes of the sixteenth PMOS tube and the seventeenth PMOS tube and a drain electrode of the fourteenth PMOS tube;
the other end of the sixth capacitor is grounded, and the other end of the fifth resistor is grounded after passing through the fifth capacitor;
a grid electrode of a sixteenth PMOS tube is used as a first non-inverting input end of the operational amplifier and is connected with the first reference voltage, and a drain electrode of the sixteenth PMOS tube is connected with a grid electrode of a fourteenth NMOS tube, a drain electrode of an eighteenth PMOS tube, and a grid electrode and a drain electrode of a thirteenth NMOS tube;
the source electrodes of the thirteenth NMOS tube and the fourteenth NMOS tube are grounded;
a grid electrode of the seventeenth PMOS tube is used as a second non-inverting input end of the operational amplifier and is connected with a second control signal, and a drain electrode of the seventeenth PMOS tube is connected with a source electrode of the eighteenth PMOS tube;
the second control signal is a triangular wave signal;
the grid electrode of the eighteenth PMOS tube is connected with an enable signal;
the grid and the drain of the thirteenth PMOS tube are connected with the grid of the fourteenth PMOS tube and the fourth bias voltage, and the source of the thirteenth PMOS tube is connected with the source of the fourteenth PMOS tube and the power supply voltage.
The invention has the beneficial effects that: the synchronous external clock module is added, so that the oscillator can synchronize an external clock, and multi-chip combined use can be realized; the comparator is improved, so that the error overturning of the comparator during the clock synchronization is avoided; frequency dithering functions are also added to optimize the EMI characteristics of the system.
Drawings
Fig. 1 is a diagram of a conventional system clock equivalent architecture.
Fig. 2 is an equivalent architecture diagram of an oscillator capable of synchronizing an external clock according to the present invention.
Fig. 3 is a structural diagram of a synchronous external clock module in an oscillator capable of synchronizing an external clock according to the present invention.
Fig. 4 is a diagram illustrating an implementation of a comparator in an oscillator capable of synchronizing an external clock according to the present invention.
Fig. 5 is an architecture diagram of an operational amplifier in an oscillator capable of synchronizing an external clock according to the present invention using a clamped operational amplifier capable of performing frequency jitter.
Fig. 6 is a functional diagram of an oscillator capable of synchronizing an external clock according to the present invention.
Detailed Description
The invention is further illustrated with reference to the accompanying drawings and specific embodiments.
In order to enable the chip to work with a plurality of chips in a cooperative mode, a synchronous external clock module (SYNC) is added to the traditional structure to achieve the function of synchronizing the external clock, and the consistency of the cooperative work of the chips is facilitated. As shown in fig. 2, the oscillator provided by the present invention includes an operational amplifier OP, a first NMOS transistor MN1, a second NMOS transistor MN2, a first PMOS transistor MP1, a second PMOS transistor MP2, a timing capacitor, a comparator CMP and a synchronous external clock module, wherein a non-inverting input terminal of the operational amplifier OP is connected to a first reference voltage Vref1, an inverting input terminal thereof is connected to a source of the first NMOS transistor MN1 and connected to a frequency-selecting resistor, and an output terminal thereof is connected to a gate of the first NMOS transistor MN 1; the gate-source short circuit of the first PMOS transistor MP1 is connected with the drain electrode of the first NMOS transistor MN1 and the grid electrode of the second PMOS transistor MP2, and the source electrode of the first PMOS transistor MP1 is connected with the source electrode of the second PMOS transistor MP2 and the power supply voltage INTVCC; the inverting input end of the comparator CMP is connected with a second reference voltage Vref2, and the positive input end of the comparator CMP is connected with the drain electrode of a second PMOS tube MP2 and the drain electrode of a second NMOS tube MN2 and is grounded after passing through a timing capacitor; the source of the second NMOS transistor MN2 is grounded.
Fig. 3 is a schematic diagram of an internal structure of a synchronous external clock module, where the synchronous external clock module includes a first resistor R1, odd first schmitt triggers SMIT1, second schmitt triggers SMIT2, third schmitt triggers SMIT3, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first inverter inv1, a second inverter inv2, a third inverter inv3, a fourth inverter inv4, a fifth inverter inv5, a NAND gate NAND2, and a third PMOS transistor MP3, one end of the first resistor R1 is used as a first input end of the synchronous external clock module and connected to an external clock signal, and the other end of the first resistor R1 is grounded through the third capacitor C3 and connected to an input end of the fifth inverter inv5 through the odd cascaded first schmitt triggers SMIT 1; the first input end of the NAND gate NAND2 is connected with the output end of the fifth inverter inv5 and the input end of the fourth inverter inv4, the second input end of the NAND gate is connected with the output end of the fourth inverter inv4, the NAND gate is grounded after passing through the first capacitor C1, and the output end of the NAND gate is connected with the grid electrode of the third PMOS tube MP 3; the source electrode of the third PMOS transistor MP3 is connected to the power supply voltage INTVCC, and the drain electrode thereof is connected to the output terminal of the first inverter inv1 and the input terminal of the second inverter inv2 and grounded through the second capacitor C2; the input end of a second Schmitt trigger SMIT2 serving as a second input end of the synchronous external clock module is connected with the output end of the comparator CMP, and the output end of the second Schmitt trigger SMIT2 is connected with the input end of the first phase inverter inv 1; the input end of the third schmitt trigger SMIT3 is connected with the output end of the second inverter inv2, and the output end thereof is used as the output end of the oscillator and is connected with the gate of the second NMOS transistor MN2 after passing through the third inverter inv 3.
The first input end of the synchronous external clock module is connected with an external clock signal, when the external clock is required to be synchronized, the external clock is connected to the first input end of the synchronous external clock module, and when the external clock is not required to be synchronized, the first input end of the synchronous external clock module is grounded or connected with a power supply voltage INTVCC.
When the external clock is not synchronized, the output of the NAND gate NAND2 is always at a high level, the third PMOS transistor MP3 is always turned off, and the system clock is generated by charging and discharging the timing capacitor Cc, i.e., the signal is transmitted from the output terminal CMP _ OUT of the comparator to the output terminals CLK and SYNC _ OUT of the oscillator.
When the external clock is synchronized and the external clock jumps from high to low, both input terminals of the NAND gate NAND2 are at low level simultaneously due to the first capacitor C1, so that a narrow pulse is generated at the output of the NAND gate NAND2, the pulse width is determined by the time constant of the node Y (i.e. the output terminal of the fourth inverter inv 4), and the time constant of the node Y is determined by the equivalent resistance and the capacitance of the node Y, specifically, the on-resistance of the first capacitor C1 and the preceding inverter in fig. 3. During the narrow pulse, the third PMOS transistor MP3 is turned on to supply current to the node X (i.e., the drain terminal of the third PMOS transistor). At the same time, since it is desirable for the external clock to control the entire loop, the comparator output should be constantly low, i.e., the output voltage CMP _ OUT of the comparator CMP is constantly low. Node Z (i.e., the output of the second schmitt trigger) is constantly high. The input of the first inverter inv1, which is constantly high, discharges node X. Therefore, during the narrow pulse, the third PMOS transistor MP3 charges the node X, and the first inverter inv1 discharges the node X. Also, during the narrow pulse, the node X needs to be charged to the threshold voltage of the second inverter inv2 or more. As a result, U > (Q1-Q2)/C2 = Vth, where U is a voltage value of the node X, Q1 is an amount of electric charge coupled from the third PMOS transistor MP3 to the node X during the narrow pulse, Q2 is an amount of electric charge discharged from the node X by the first inverter inv1 during the narrow pulse, and Vth is a switching threshold of the second inverter inv2, thereby determining a width-to-length ratio of the third PMOS transistor MP3 and a value of the second capacitor C2. During the narrow pulse, it is ensured that X reaches the switching threshold of the second inverter inv2, i.e. the function of synchronizing the external clock is ensured. The synchronous external clock of the invention is characterized in that only the rising edge of the external clock is synchronized, the duty cycle is not synchronized together, and the duty cycle is determined by the narrow pulse width and the clock period.
An output signal of the comparator CMP needs to be a low level constantly when the oscillator synchronizes the external clock, and a schematic diagram of a circuit form of the comparator CMP is given as shown in fig. 4, including a second resistor R2, a third resistor R3, a fourth resistor R4, a fourth capacitor C4, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, and a twelfth PMOS transistor MP12, where the comparator CMP includes two inverting input terminals and a non-inverting input terminal; the grid electrode of the sixth NMOS tube MN6 is used as the non-inverting input end of the comparator CMP, the source electrodes of the sixth NMOS tube MN6 are connected with the source electrodes of the seventh NMOS tube MN7 and the eighth NMOS tube MN8 and the drain electrode of the third NMOS tube MN3, and the drain electrode of the sixth NMOS tube MP6 is connected with the drain electrode of the fifth PMOS tube MP5, the grid electrode and the drain electrode of the seventh PMOS tube MP 7; the grid electrode of the seventh NMOS tube MN7 is used as a first inverting input end of the comparator CMP and is connected with a second reference voltage Vref2, and the drain electrode of the seventh NMOS tube MN8 is connected with the drain electrode of the eighth NMOS tube MN8, the grid electrode and the drain electrode of the fourth PMOS tube MP4 and the grid electrode of the fifth PMOS tube MP 5; the grid electrode of the eighth NMOS transistor MN8 is used as a second inverting input end of the comparator CMP and is connected with a first control signal; the first control signal is constantly at a low level when the oscillator does not synchronize the external clock, and is turned to a high level when the oscillator synchronizes the external clock; the source electrode of the sixth PMOS transistor MP6 is connected to the source electrodes of the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 and to the power supply voltage INTVCC, and the drain electrode thereof is connected to the source electrode of the seventh PMOS transistor MP7 and one end of the fourth resistor R4 and serves as the output terminal of the comparator CMP; the other end of the fourth resistor R4 is grounded; the grid electrode of the fifth NMOS tube MN5 is connected with the grid electrode and the drain electrode of the fourth NMOS tube MN4 and the grid electrode of the third NMOS tube MN3 and is connected with a third bias voltage LA3, the source electrode of the fifth NMOS tube MN5 is connected with the source electrodes of the third NMOS tube MN3, the fourth NMOS tube MN4, the tenth NMOS tube MN10 and the eleventh NMOS tube MN11 and is grounded, and the drain electrode of the fifth NMOS tube MN5 is connected with the source electrode of the twelfth NMOS tube MN12 and the second inverting input end of the comparator CMP; the gate of the ninth NMOS transistor MN9 is connected to the first bias voltage LA1, the source thereof is grounded through the second resistor R2, and the drain thereof is connected to the gate of the tenth NMOS transistor MN10, the drain of the eleventh PMOS transistor MP11, and one end of the fourth capacitor C4; the other end of the fourth capacitor C4 is grounded through a third resistor R3; the gate of the eleventh PMOS transistor MP11 is connected to the output of the NAND gate NAND2 in the synchronous external clock module, and the source thereof is connected to the power supply voltage INTVCC; a gate of the ninth PMOS transistor MP9 is connected to a gate of the tenth PMOS transistor MP10, a gate of the twelfth PMOS transistor MP12, a gate and a drain of the eighth PMOS transistor MP8, and a second bias voltage LA2, a drain of the ninth PMOS transistor MP9 is connected to a drain of the tenth NMOS transistor MN10 and a gate of the eleventh NMOS transistor MN11, and a source of the ninth PMOS transistor MP9 is connected to a source of the eighth PMOS transistor MP8, a source of the tenth PMOS transistor MP10, and a source of the twelfth PMOS transistor MP12 and connected to a power supply voltage INTVCC; the grid electrode of the twelfth NMOS transistor MN12 is connected with the drain electrodes of the tenth PMOS transistor MP10 and the eleventh NMOS transistor MN11, and the drain electrode thereof is connected with the drain electrode of the twelfth PMOS transistor MP 12.
In the embodiment, in order to avoid the factors such as ground bounce and crosstalk from causing the comparator CMP to be turned over by mistake, the comparator CMP is improved, and the noise margin is increased. In the comparator CMP of this embodiment, the gate of the sixth NMOS transistor MN6 is a non-inverting input terminal, and the gates of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 are inverting input terminals. The first bias voltage LA1, the second bias voltage LA2, and the third bias voltage LA3 are gate voltages provided by the external bias current mirror, in this embodiment, an inverting input terminal, that is, a gate terminal of the eighth NMOS transistor MN8 is added to the comparator CMP, and the voltage of the first control signal Vsy connected to the input terminal is constantly at a low level when the external clock is not synchronized and at a high level when the external clock is synchronized.
The specific working process of the comparator CMP in this embodiment is as follows: when the external clock is not synchronized, the output signal NAND2_ OUT of the NAND gate is constantly at a high level, at this time, the node a (i.e., the drain of the eleventh PMOS transistor MP 11) is discharged to the ground potential by the ninth NMOS transistor MN9, the node B (i.e., the drain of the ninth PMOS transistor MP 9) is charged to the power supply voltage INTVCC by the ninth PMOS transistor MP9, the node C (i.e., the drain of the eleventh NMOS transistor MN 11) is discharged to the ground potential by the eleventh NMOS transistor MN11, and the potential of the second inverting input terminal of the comparator CMP is discharged to the ground potential by the fifth NMOS transistor MN 5. When an external clock is synchronized, the output signal NAND2_ OUT of the NAND gate is a downward narrow pulse signal, the voltage of the node a is charged to the power supply voltage INTVCC in one or more cycles, after the node a reaches the threshold voltage of the tenth NMOS transistor MN10, the node B is discharged to the ground by the tenth NMOS transistor MN10, the node C is charged to the power supply voltage INTVCC by the tenth PMOS transistor MP10, and the potential of the second inverting input terminal of the comparator CMP is charged to the power supply voltage INTVCC by the twelfth PMOS transistor MP 12. The grid end of the seventh NMOS tube MN7 is connected with a second reference voltage Vref2, and the grid end of the sixth NMOS tube MN6 is connected with the upper polar plate of the timing capacitor Cc. Because the potential of the second inverting input end of the comparator CMP is the power supply voltage INTVCC, the noise margin of the output signal CMP _ OUT of the comparator is changed from the original Vref2 to INTVCC, and the possibility of error overturn of the comparator CMP is reduced.
In SOC, especially in high frequency applications, EMI characteristics of BUCK power supplies need to be of particular concern. The BUCK power supply can generate EMI in a high-frequency switch, which affects the normal operation of a sensitive module integrated on the same chip. In the framework of the traditional system clock, the frequency jitter function is added, and the frequency of the system clock is jittered, so that EMI energy peaks at the switching frequency and the frequency multiplication part of the switching frequency are dispersed, and the aim of optimizing the EMI is fulfilled. As shown in fig. 5, the operational amplifier OP used in this embodiment has an increased frequency jitter function, and includes a fifth resistor R5, a fifth capacitor C5, a sixth capacitor C6, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fifteenth PMOS transistor MP15, a sixteenth PMOS transistor MP16, a seventeenth PMOS transistor MP17, an eighteenth PMOS transistor MP18, a thirteenth NMOS transistor MN13, and a fourteenth NMOS transistor MN14, and includes two non-inverting input terminals and one inverting input terminal; a gate of the fifteenth PMOS transistor MP15 serves as an inverting input terminal of the operational amplifier OP, a drain thereof is connected to a drain of the fourteenth NMOS transistor MN14, an end of the fifth resistor R5, and an end of the sixth capacitor C6, and a source thereof is connected to sources of the sixteenth PMOS transistor MP16 and the seventeenth PMOS transistor MP17, and a drain of the fourteenth PMOS transistor MP 14; the other end of the sixth capacitor C6 is grounded, and the other end of the fifth resistor R5 is grounded after passing through the fifth capacitor C5; a gate of the sixteenth PMOS transistor MP16 is used as a first non-inverting input terminal of the operational amplifier OP and is connected to the first reference voltage Vref1, and a drain thereof is connected to a gate of the fourteenth NMOS transistor MN14, a drain of the eighteenth PMOS transistor MP18, and a gate and a drain of the thirteenth NMOS transistor MN 13; the source electrodes of the thirteenth NMOS transistor MN13 and the fourteenth NMOS transistor MN14 are grounded; the grid electrode of the seventeenth PMOS tube MP17 is used as the second non-inverting input end of the operational amplifier OP and is connected with the second control signal, and the drain electrode of the seventeenth PMOS tube MP17 is connected with the source electrode of the eighteenth PMOS tube MP 18; the second control signal is a triangular wave signal; the gate of the eighteenth PMOS transistor MP18 is connected with an enable signal; the gate and the drain of the thirteenth PMOS transistor MP13 are connected to the gate of the fourteenth PMOS transistor MP14 and the fourth bias voltage LA4, and the source thereof is connected to the source of the fourteenth PMOS transistor MP14 and the power supply voltage INTVCC.
In this embodiment, the gate of the fifteenth PMOS transistor MP15 is connected to the upper end of the frequency-selecting resistor RT, the sixteenth PMOS transistor MP16 is connected to the first reference voltage Vref1, and the second control signal Vs is a periodic triangular signal. When the system does not need frequency jitter, the enable signal En is high, and at this time, the voltage at the upper end of the frequency selecting resistor RT is clamped to the first reference voltage Vref1 by the operational amplifier OP, so that the current I = Vref1/RT is generated. The frequency f of the system clock is determined by equation (1):
when the system needs frequency jitter, the enable signal En is low, and at this time, the voltage at the upper end of the frequency selection resistor RT is clamped to the second control signal Vs, which is a periodic triangular wave signal, so that the charging current I of the timing capacitor Cc changes, and the switching frequency jitters.
Fig. 6 is a functional diagram of the oscillator in the present embodiment. Fig. 6 (a) is a functional diagram of frequency jitter, and fig. 6 (b) is a functional diagram of synchronous clock. In fig. 6 (a), when the clock jitter enable signal is asserted, the potential of the clamp point RT of the charging current of the timing capacitor Cc is clamped to the second control signal Vs, which changes the magnitude of the charging current, thereby causing the clock signal CLK output by the oscillator to generate irregular jitter. In fig. 6 (b), when the oscillator synchronizes the external clock signal, the level of the second inverting input terminal of the comparator is rapidly pulled to a high level by the signal generated by the synchronized external clock module according to the present invention, and the output of the comparator is not turned over by mistake. At this time, the clock signal CLK output from the oscillator matches the external clock signal connected to the synchronous external clock module.
In summary, the present invention provides an oscillator, which adds a function of synchronizing clocks to a conventional system clock structure, and can implement multi-chip combined use; the comparator CMP is improved, so that the error turnover of the comparator during the clock synchronization is avoided; frequency dithering functions are also added to optimize the EMI characteristics of the system.
Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (3)
1. An oscillator capable of synchronizing external clock comprises an operational amplifier, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a timing capacitor and a comparator,
the non-inverting input end of the operational amplifier is connected with a first reference voltage, the inverting input end of the operational amplifier is connected with the source electrode of the first NMOS tube and is connected with the frequency-selecting resistor, and the output end of the operational amplifier is connected with the grid electrode of the first NMOS tube;
the grid source of the first PMOS tube is in short circuit and is connected with the drain electrode of the first NMOS tube and the grid electrode of the second PMOS tube, and the source electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube and power supply voltage;
the inverting input end of the comparator is connected with a second reference voltage, and the positive input end of the comparator is connected with the drain electrode of the second PMOS tube and the drain electrode of the second NMOS tube and is grounded after passing through the timing capacitor;
the source electrode of the second NMOS tube is grounded;
the oscillator is characterized by further comprising a synchronous external clock module, wherein the synchronous external clock module comprises a first resistor, odd first Schmitt triggers, a second Schmitt trigger, a third Schmitt trigger, a first capacitor, a second capacitor, a third capacitor, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a NAND gate and a third PMOS tube,
one end of the first resistor is used as a first input end of the synchronous external clock module and is connected with an external clock signal, and the other end of the first resistor is grounded through a third capacitor on one hand and is connected with the input end of a fifth inverter through the odd-number first Schmitt triggers in cascade connection on the other hand;
the first input end of the NAND gate is connected with the output end of the fifth phase inverter and the input end of the fourth phase inverter, the second input end of the NAND gate is connected with the output end of the fourth phase inverter and is grounded after passing through the first capacitor, and the output end of the NAND gate is connected with the grid electrode of the third PMOS tube;
the source electrode of the third PMOS tube is connected with power supply voltage, and the drain electrode of the third PMOS tube is connected with the output end of the first phase inverter and the input end of the second phase inverter and is grounded after passing through the second capacitor;
the input end of the second Schmitt trigger is used as the second input end of the synchronous external clock module and is connected with the output end of the comparator, and the output end of the second Schmitt trigger is connected with the input end of the first phase inverter;
the input end of the third Schmitt trigger is connected with the output end of the second phase inverter, and the output end of the third Schmitt trigger is used as the output end of the oscillator and is connected with the grid electrode of the second NMOS tube after passing through the third phase inverter;
the output signal of the comparator is constantly at a low level when the oscillator synchronizes the external clock.
2. The oscillator according to claim 1, wherein the comparator comprises a second resistor, a third resistor, a fourth capacitor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, and a twelfth PMOS transistor, and the comparator comprises two inverting inputs and a non-inverting input;
the grid electrode of the sixth NMOS tube is used as the non-inverting input end of the comparator, the source electrodes of the sixth NMOS tube are connected with the source electrodes of the seventh NMOS tube and the eighth NMOS tube and the drain electrode of the third NMOS tube, and the drain electrode of the sixth NMOS tube is connected with the drain electrode of the fifth PMOS tube, the grid electrode and the drain electrode of the seventh PMOS tube and the grid electrode of the sixth PMOS tube;
the grid electrode of the seventh NMOS tube is used as a first inverted input end of the comparator and is connected with the second reference voltage, and the drain electrode of the seventh NMOS tube is connected with the drain electrode of the eighth NMOS tube, the grid electrode and the drain electrode of the fourth PMOS tube and the grid electrode of the fifth PMOS tube;
the grid electrode of the eighth NMOS tube is used as a second inverting input end of the comparator and is connected with the first control signal;
the first control signal is constantly at a low level when the oscillator is not synchronized with the external clock, and is turned to a high level when the oscillator is synchronized with the external clock;
a source electrode of the sixth PMOS tube is connected with source electrodes of the fourth PMOS tube and the fifth PMOS tube and is connected with power supply voltage, and a drain electrode of the sixth PMOS tube is connected with a source electrode of the seventh PMOS tube and one end of the fourth resistor and serves as an output end of the comparator;
the other end of the fourth resistor is grounded;
the grid electrode of the fifth NMOS tube is connected with the grid electrode and the drain electrode of the fourth NMOS tube and the grid electrode of the third NMOS tube and is connected with a third bias voltage, the source electrode of the fifth NMOS tube is connected with the source electrodes of the third NMOS tube, the fourth NMOS tube, the tenth NMOS tube and the eleventh NMOS tube and is grounded, and the drain electrode of the fifth NMOS tube is connected with the source electrode of the twelfth NMOS tube and the second inverted input end of the comparator;
the grid electrode of the ninth NMOS tube is connected with the first bias voltage, the source electrode of the ninth NMOS tube is grounded after passing through the second resistor, and the drain electrode of the ninth NMOS tube is connected with the grid electrode of the tenth NMOS tube, the drain electrode of the eleventh PMOS tube and one end of the fourth capacitor;
the other end of the fourth capacitor is grounded through a third resistor;
the grid electrode of the eleventh PMOS tube is connected with the output end of the NAND gate in the synchronous external clock module, and the source electrode of the eleventh PMOS tube is connected with the power supply voltage;
the grid electrode of the ninth PMOS tube is connected with the grid electrode of the tenth PMOS tube, the grid electrode of the twelfth PMOS tube, the grid electrode and the drain electrode of the eighth PMOS tube and the second bias voltage, the drain electrode of the ninth PMOS tube is connected with the drain electrode of the tenth NMOS tube and the grid electrode of the eleventh NMOS tube, and the source electrode of the ninth PMOS tube is connected with the source electrodes of the eighth PMOS tube, the tenth PMOS tube and the twelfth PMOS tube and is connected with the power supply voltage;
the grid electrode of the twelfth NMOS tube is connected with the drain electrodes of the tenth PMOS tube and the eleventh NMOS tube, and the drain electrode of the twelfth NMOS tube is connected with the drain electrode of the twelfth PMOS tube.
3. The oscillator according to claim 1 or 2, wherein the operational amplifier comprises a fifth resistor, a fifth capacitor, a sixth capacitor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a thirteenth NMOS transistor and a fourteenth NMOS transistor, and the operational amplifier comprises two non-inverting input terminals and one inverting input terminal;
a grid electrode of the fifteenth PMOS tube is used as an inverting input end of the operational amplifier, a drain electrode of the fifteenth PMOS tube is connected with a drain electrode of the fourteenth NMOS tube, one end of the fifth resistor and one end of the sixth capacitor, and a source electrode of the fifteenth PMOS tube is connected with source electrodes of the sixteenth PMOS tube and the seventeenth PMOS tube and a drain electrode of the fourteenth PMOS tube;
the other end of the sixth capacitor is grounded, and the other end of the fifth resistor is grounded after passing through the fifth capacitor;
a grid electrode of a sixteenth PMOS tube is used as a first non-inverting input end of the operational amplifier and is connected with the first reference voltage, and a drain electrode of the sixteenth PMOS tube is connected with a grid electrode of a fourteenth NMOS tube, a drain electrode of an eighteenth PMOS tube, and a grid electrode and a drain electrode of a thirteenth NMOS tube;
the source electrodes of the thirteenth NMOS tube and the fourteenth NMOS tube are grounded;
a grid electrode of the seventeenth PMOS tube is used as a second non-inverting input end of the operational amplifier and is connected with a second control signal, and a drain electrode of the seventeenth PMOS tube is connected with a source electrode of the eighteenth PMOS tube;
the second control signal is a triangular wave signal;
the grid electrode of the eighteenth PMOS tube is connected with an enabling signal;
the grid electrode and the drain electrode of the thirteenth PMOS tube are connected with the grid electrode and the fourth bias voltage of the fourteenth PMOS tube, and the source electrode of the thirteenth PMOS tube is connected with the source electrode and the power supply voltage of the fourteenth PMOS tube.
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