CN116015061A

CN116015061A - Slope compensation circuit, method for generating ramp compensation signal and electronic chip

Info

Publication number: CN116015061A
Application number: CN202310193885.0A
Authority: CN
Inventors: 张朋; 马培; 张洪俞
Original assignee: NANJING MICRO ONE ELECTRONICS Inc
Current assignee: NANJING MICRO ONE ELECTRONICS Inc
Priority date: 2023-03-02
Filing date: 2023-03-02
Publication date: 2023-04-25

Abstract

The invention provides a slope compensation circuit, a method for generating a slope compensation signal and an electronic chip, which are applied to the technical field of switching power supplies, wherein a signal input module is used for inputting a control signal CON, and a capacitor C1 is short-circuited when an external circuit does not need compensation; the direct current reference module is used for providing direct current working current, leading the NMOS tube I N1 and the NMOS tube II N2 to be fully conducted, realizing the function of the whole-course compensation of the oblique wave compensation circuit, and leading the compensation output module not to output signals when the external circuit does not need the compensation; the compensation output module is used for outputting a ramp compensation signal Islope; the direct current reference module is electrically connected with the signal input module and the compensation output module respectively. According to the circuit, the NMOS tube I N1 and the NMOS tube II N2 are not influenced by the charge and discharge time of the capacitor, the function of whole-course oblique wave compensation is achieved, and the generated compensation current has the characteristic of being consistent in linearity through a negative feedback structure.

Description

Slope compensation circuit, method for generating ramp compensation signal and electronic chip

Technical Field

The invention belongs to the technical field of switching power supplies, and particularly relates to a slope compensation circuit, a method for generating a ramp compensation signal and an electronic chip.

Background

In the switching power supply circuit, the circuit adopts a current mode control architecture, and when the on duty ratio of the system is more than 50%, subharmonic oscillation occurs, and the duration of the on time is short. The current waveform is represented as a magnitude wave, and serious system operation abnormality can be caused. In order to avoid the subharmonic oscillation, a slope compensation circuit is introduced to correct the waveform of the inductive current, so as to achieve the effect of stabilizing the system operation.

Subharmonic oscillations as shown in fig. 1, typically occur in large duty cycle current waveforms, inductor current waveform I shown in solid lines _LM0 Representing the inductor current waveform during normal operation when a current disturbance I is introduced _e After that, the inductor current waveform becomes I shown by the dotted line _LM1 It can be seen that the error of the inductance current in the subsequent period is gradually amplified, the system is unstable, and the oscillation period is mostly twice of the switching period, at this time, the duty ratio is relatively large, and a common suppression method is to add a slope as shown in fig. 2, and when the duty ratio is too large, the peak value of the original current is reached in advance through built-in slope compensation. I indicated by a broken line in FIG. 2 _LM3 An inductor current waveform when the system is unstable after the occurrence of subharmonic oscillation is shown, and an inductor current waveform I shown by a solid line is shown _LM2 Indicating the corrected inductor current waveform after increasing the Slope signal, it can be seen that the current error signal gradually decays in amplitude until stable every time it passes through one cycle after the Slope signal is introduced, i.e., slope compensation.

The slope compensation circuit is a circuit module which is indispensable to a current mode control architecture, and the implementation modes are various. The common compensation current generating circuit generally charges the compensation capacitor by current, the generated capacitor voltage controls and enhances the grid electrode of the NMOS tube, and the grid electrode voltage V of the NMOS tube _GS To generate a compensation current.

The above compensation method has two disadvantages: 1. the slope compensation current cannot be generated until the voltage on the compensation capacitor is larger than the threshold value of the enhancement NMOS transistor, and the enhancement NMOS transistor is conducted and needs the gate voltage V _GS Is larger than the threshold value of the enhanced NMOS tubeThe NMOS transistor is turned on after the compensation capacitor is charged for a certain period of time, i.e., there is a waiting time for the charging process. 2. Simply pass gate voltage V _GS Current I generated by variation _D Poor linearity due to the equation according to Sasa

The current and the voltage are in a nonlinear relation.

Disclosure of Invention

In view of the above problems in the prior art, the invention aims to provide a simple slope compensation circuit, wherein the NMOS tube I N1 and the NMOS tube II N2 are not affected by the charge and discharge time of a capacitor, have the function of whole-course oblique wave compensation, and enable the generated compensation current to have the characteristic of linear consistency through a negative feedback structure.

A simple ramp compensation circuit comprising:

the signal input module is used for inputting a control signal CON and short-circuiting a capacitor C1 when the external circuit does not need compensation;

the direct current reference module is used for providing direct current working current, leading the NMOS tube I N1 and the NMOS tube II N2 to be fully conducted, realizing the function of the whole-course compensation of the oblique wave compensation circuit, and leading the compensation output module not to output signals when the external circuit does not need the compensation;

the compensation output module is used for outputting a ramp compensation signal is slope;

the direct current reference module is electrically connected with the signal input module and the compensation output module respectively.

The signal input module comprises a first current source I1, a second NMOS tube N2, a third NMOS tube N3, a third resistor R3 and a second resistor R2, wherein one end of the first current source I1 is electrically connected with the gates of the third resistor R3 and the second NMOS tube N2, the source electrode of the second NMOS tube N2 is connected with the second resistor R2, the drain electrode is connected with the compensation output module, the other end of the second resistor R2 is grounded, the other end of the third resistor R3 is connected with the drain electrodes of the first capacitor C1 and the third NMOS tube N3, the other end of the first capacitor C1 and the source electrode of the third NMOS tube N3 are grounded, and the grid electrode of the third NMOS tube N3 is connected with a control signal CON;

the direct current reference module comprises a current source II I2, a resistor I R1, a resistor IV R4, an NMOS tube I N1 and a first current mirror unit, wherein one end of the current source II I2 is electrically connected with a grid electrode of the NMOS tube I N1 and the resistor IV R4, a drain electrode of the NMOS tube I N1 is connected with the first current mirror unit, a source electrode is connected with the resistor I R1, the other ends of the resistor I R1 and the resistor IV R4 are grounded, and the first current mirror unit is connected with the compensation output module;

the parameters of the first current source I1 and the second current source I2 are the same, the parameters of the first resistor R1 and the second resistor R2 are the same, and the parameters of the third resistor R3 and the fourth resistor R4 are the same.

In order to accurately mirror the current, the compensation output module comprises a second current mirror unit, the second current mirror unit comprises a PMOS tube III P3 and a PMOS tube IV P4, the grid electrode and the drain electrode of the PMOS tube III P3 are electrically connected with the grid electrode of the PMOS tube IV P4 and the drain electrode of the NMOS tube II N2, and the drain electrode of the PMOS tube IV P4 outputs a ramp compensation signal Islope.

The first current mirror unit comprises a first PMOS tube P1 and a second PMOS tube P2, wherein the grid electrode and the drain electrode of the first PMOS tube P1 are short-circuited to the drain electrode of the first NMOS tube N1, the grid electrode of the first PMOS tube P1 is connected with the grid electrode of the second PMOS tube P2, and the drain electrode of the second PMOS tube P2 is electrically connected with the grid electrode and the drain electrode of the third PMOS tube P3.

In order to facilitate power supply, the first current source I1 and the second current source I2 are electrically connected with the power supply, and the sources of the first PMOS tube P1, the second PMOS tube P2, the third PMOS tube P3 and the fourth PMOS tube P4 are electrically connected with the power supply.

In a second aspect of the present invention, a method for generating a ramp compensation signal is provided, wherein when a control signal CON is at a low level, a ramp compensation circuit is in a compensation phase; when the control signal CON is at a high level, the slope compensation circuit is in a non-compensation phase, the compensation phase comprising the following processes:

inputting a low-level control signal CON, and at the moment, switching an NMOS transistor three N3 off;

the current source I1 charges the capacitor C1 through the resistor tri-R3 to generate a ramp voltage Vslpoe_in at the gate of the NMOS transistor N2, and the slope of the ramp voltage is then

The ramp voltage Vslope_in generates a current I_P3 through the common source amplifier NMOS transistor N2, and the current is changed at the moment

The current I_P3 is mirrored through the PMOS tube III P3 and the PMOS tube IV P4 to obtain a slope compensation current signal Islope, wherein when the PMOS tube III P3 and the PMOS tube IV P4 are the same, the slope compensation slope is

The non-compensation phase comprises the following processes:

inputting a high-level control signal CON, and at the moment, inputting a switch NMOS tube three N3 to be conducted, and discharging the charge of a capacitor C1;

because the parameters of the first current source I1 and the second current source I2 are the same, and the parameters of the resistor three R3 and the resistor four R4 are the same, the grid potentials generated in the NMOS tube I1 and the NMOS tube II N2 of the common source amplifier are the same, so that the NMOS tube I1 and the NMOS tube II N2 are always conducted;

because the parameters of the first resistor R1 and the second resistor R2 are the same, equal currents are generated on the first resistor R1 and the second resistor R2, and therefore the currents flowing through the first PMOS tube P1 and the second PMOS tube P2 in the first current mirror unit are equal;

at this time, the PMOS transistor three P3 and the PMOS transistor four P4 in the second current mirror do not generate current, and the output ramp compensation signal is slope=0.

In a third aspect of the present invention, an electronic chip is provided, including:

a ramp compensation module, which is the ramp compensation circuit of any one of claims 1 to 5, for outputting a ramp compensation signal is slope;

an enabling control module for controlling the enabling of the electronic chip;

an amplifier for detecting a change in the feedback signal FB voltage;

a comparator for comparing an output signal of the amplifier with an output signal of the ramp compensation circuit, thereby outputting a signal capable of controlling a duty ratio of the electronic chip;

the logic control module is used for controlling logic change of the electronic chip and comprises protection logic, starting logic and power-on logic;

the driving module is used for amplifying the logic signals output by the logic control module so as to control the on and off of the upper switch MOS tube and the lower switch MOS tube;

the current limiting detection module is used for detecting the current flowing in the switch MOS tube and limiting the current in the switch MOS tube so as to prevent the working current of the electronic chip from being overlarge;

the switch MOS tube comprises an NMOS tube N4 and a PMOS tube P5.

The amplifier is an error amplifier, a feedback signal FB is input to an inverting input end of the error amplifier, a non-inverting input end of the error amplifier is connected with a threshold voltage, an output end of the error amplifier is connected with an inverting input end of a comparator, the output end of the error amplifier is further electrically connected with a resistor five R5 and a capacitor two C2 which are connected in series, the output end of the comparator is connected with a logic control module, the logic control module is further connected with a current limiting detection module and a driving module, and the current limiting detection module is further electrically connected with a ramp wave compensation circuit;

the driving module is respectively connected with the grid electrodes of the NMOS tube N4 and the PMOS tube P5, the source electrode of the PMOS tube P5 is connected with the current limiting detection module, the drain electrode is connected with the drain electrode of the NMOS tube N4, the drain electrodes of the NMOS tube N4 and the PMOS tube P5 are electrically connected with the SW port, and the source electrode of the NMOS tube N4 is grounded;

the electronic chip comprises a VIN port connected with the current limiting detection module, an EN port connected with the enabling control module and a FB port of the inverting input end of the error amplifier.

The beneficial effects of the invention are as follows: according to the slope compensation circuit, the method for generating the oblique wave compensation signal and the electronic chip, the grid voltages of the NMOS tube I N1 and the NMOS tube II N2 are raised through adding the resistor III R3 and the resistor IV R4, so that the NMOS tube I N1 and the NMOS tube II N2 work in the whole course, the circuit can realize the whole-course slope compensation function, and meanwhile, the generated compensation current has the characteristic of being consistent in linearity through the source negative feedback resistor I R1 and the resistor II R2; in addition, through adjusting the proportion relation of the three P3 PMOS tubes and the four P4 PMOS tubes, the compensation slope can be increased or reduced more conveniently under the condition that the sizes of the first capacitor C1, the first current source I1 and the second current source I2 are not changed, so that a proper compensation effect is achieved, and the applicability is higher.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention. In the drawings:

FIG. 1 is a current waveform of subharmonic oscillation in a conventional switching power supply;

FIG. 2 is a current waveform after slope compensation of subharmonic oscillations in a conventional switching power supply;

FIG. 3 is a circuit block diagram of the present invention;

FIG. 4 is a flow chart of the compensation phase of the present invention;

FIG. 5 is a flow chart of the non-compensation phase of the present invention;

FIG. 6 is a signal waveform diagram of the present invention;

fig. 7 is a circuit block diagram of the present invention applied to an electronic chip.

Marked in the figure as: 101. a signal input module; 102. a direct current reference module; 103. and a compensation output module.

Detailed Description

Example 1

As shown in FIG. 3, the simple slope compensation circuit comprises a signal input module, a direct current reference module and a compensation output module, wherein the direct current reference module is respectively and electrically connected with the signal input module and the compensation output module, and outputs a ramp compensation signal I s slope after the control signal CON is processed by the circuit.

The signal input module is used for inputting a control signal CON, and short-circuits a capacitor C1 when the external circuit does not need compensation; the direct current reference module is used for providing direct current working current, so that the NMOS tube I N1 and the NMOS tube II N2 are conducted in the whole process, the function of whole-process compensation of the oblique wave compensation circuit is realized, and when the external circuit does not need compensation, the compensation output module does not output signals; the compensation output module is used for outputting a ramp compensation signal is slope;

as shown in fig. 3, the signal input module 101 includes a first current source I1, a second NMOS transistor N2, a third NMOS transistor N3, a third resistor R3, and a second resistor R2. Wherein, NMOS tube three N3 is as input switch, NMOS tube two N2 is as common source amplifier.

Specifically, the first current source I1 is electrically connected to the power supply, one end of the first current source I1 is electrically connected to the third resistor R3 and the second NMOS transistor N2, the source electrode of the second NMOS transistor N2 is connected to the second resistor R2, the drain electrode is connected to the compensation output module 103, the other end of the second resistor R2 is grounded, the other end of the third resistor R3 is connected to the first capacitor C1 and the drain electrode of the third NMOS transistor N3, the other end of the first capacitor C1 and the source electrode of the third NMOS transistor N3 are grounded, and the gate electrode of the third NMOS transistor N3 is connected to the control signal CON.

As shown in fig. 3, the dc reference module 102 includes a current source ii 2, a resistor R1, a resistor R4, an NMOS transistor N1, and a first current mirror unit. The second current source I2 is electrically connected with a power supply, one end of the second current source I2 is electrically connected with a grid electrode of the first NMOS tube N1 and a resistor four R4 respectively, a drain electrode of the first NMOS tube N1 is connected with the first current mirror unit, a source electrode of the first NMOS tube N1 is connected with the resistor one R1, the other ends of the resistor one R1 and the resistor four R4 are grounded, and the first current mirror unit is connected with the compensation output module 103; the first current mirror unit comprises a first PMOS tube P1 and a second PMOS tube P2, wherein the grid electrode and the drain electrode of the first PMOS tube P1 are short-circuited to the drain electrode of the first NMOS tube N1, the grid electrode of the first PMOS tube P1 is connected with the grid electrode of the second PMOS tube P2, the drain electrode of the second PMOS tube P2 is electrically connected with the grid electrode and the drain electrode of the third PMOS tube P3, and the source electrodes of the first PMOS tube P1 and the second PMOS tube P2 are electrically connected with a power supply.

Specifically, in order to make the gate potentials generated by the NMOS transistor N1 and the NMOS transistor N2 of the common source amplifier be the same, so that the NMOS transistor N1 and the NMOS transistor N2 are always turned on, the charging waiting time is reduced, and the parameters of the current source I1 and the current source I2 are required to be the same, and the parameters of the resistor three R3 and the resistor four R4 are required to be the same. In order that the currents of the first PMOS tube P1 and the second PMOS tube P2 in the first current mirror unit are equal, so that the third PMOS tube P3 and the fourth PMOS tube P4 in the second current mirror unit do not generate current, the parameters of the first resistor R1 and the second resistor R2 are required to be set to be the same.

As shown in fig. 3, the compensation output module 103 includes a second current mirror unit, where the second current mirror unit includes a PMOS transistor three P3 and a PMOS transistor four P4, the gate and the drain of the PMOS transistor three P3 are electrically connected to the gate of the PMOS transistor four P4 and the drain of the NMOS transistor two N2, the drain of the PMOS transistor four P4 outputs a ramp compensation signal Islope, and the sources of the PMOS transistor three P3 and the PMOS transistor four P4 are electrically connected to the power supply.

Example two

As shown in fig. 4 and 5, a second aspect of the present invention provides a method for generating a ramp compensation signal, wherein when a control signal CON is at a low level, a ramp compensation circuit is in a compensation phase; when the control signal CON is at a high level, the slope compensation circuit is in a non-compensation phase.

As shown in fig. 4, the compensation phase specifically includes the following processes:

As shown in fig. 5, specifically, the non-compensation phase includes the following processes:

In practical application, if the compensation slope is insufficient or overcompensated, the proportion relation between the three P3 and the four P4 of the PMOS tube can be adjusted, and the compensation slope can be increased or reduced more conveniently under the condition that the sizes of the first capacitor C1, the first current source I1 and the second current source I2 are not changed, so that a proper compensation effect is achieved.

As shown in fig. 6, when the input signal GON is at a high level, it is a system shutdown time, and no slope compensation is needed; when the input signal GON is low, it is the inductor current charging time, and the system needs to perform slope compensation.

As shown in fig. 6, vs lope_ref is a reference voltage, vs lope_in is a ramp voltage, and when the input signal GON is at a high level, the Vs lope_in level is equal to the Vs lope_ref level, at which time i_p1=i_p2, and the ramp compensation signal is slope=0. When the input signal GON is low, the Vs slope_in signal generates a slope voltage based on the Vs slope_ref voltage, and the output terminal generates a corresponding slope compensation current is slope, which can be used to compensate the slope compensation voltage required by the system.

Example III

As shown in fig. 7, a third aspect of the present invention provides an electronic chip, including: the device comprises a ramp compensation module, an enabling control module, an amplifier, a comparator, a logic control module, a driving module, a current limiting detection module and a switch MOS tube.

The oblique wave compensation module is the oblique wave compensation circuit and is used for outputting an oblique wave compensation signal is slope; the enabling control module is used for controlling the enabling of the electronic chip; the amplifier is used for detecting the change of the feedback signal FB voltage; the comparator is used for comparing the output signal of the amplifier with the output signal of the ramp compensation circuit so as to output a signal capable of controlling the duty ratio of the electronic chip; the logic control module is used for controlling logic change of the electronic chip, including protection logic, starting logic and power-on logic, and the logic control is application of the prior art and is not described herein in detail; the driving module is used for amplifying the logic signals output by the logic control module so as to control the on and off of the upper switch MOS tube and the lower switch MOS tube; the current limiting detection module is used for detecting the current flowing in the switch MOS tube and limiting the current in the switch MOS tube, so that the working current of the electronic chip is prevented from being too large to burn the chip; the switch MOS tube comprises an NMOS tube N4 and a PMOS tube P5, and the charge and discharge of the external inductor are controlled through the turn-off and turn-on of the two switch MOS tubes.

The amplifier is an error amplifier, the inverting input end of the error amplifier is input with a feedback signal FB, the non-inverting input end of the error amplifier is connected with a threshold voltage which can be 0.6V, the feedback signal FB is compared with the threshold voltage of 0.6V, and whether the output of the chip is in a threshold range or not is monitored; the output end is connected with the inverting input end of the comparator, the output end is also electrically connected with a resistor five R5 and a capacitor two C2 which are connected in series, the resistor five R5 and the capacitor two R2 are used for loop compensation, the working stability of the chip is ensured, the output end of the comparator is connected with a logic control module, the logic control module is also connected with a current limiting detection module and a driving module, and the current limiting detection module is also electrically connected with a ramp wave compensation circuit;

the electronic chip comprises a VIN port connected with the current limiting detection module, an EN port connected with the enabling control module, and an FB port connected with the inverting input end of the error amplifier, wherein the FB port is used for inputting a feedback signal FB.

The foregoing description is only a preferred embodiment of the present invention, and the present invention is not limited thereto, but it is to be understood that modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art, although the present invention has been described in detail with reference to the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A simple ramp compensation circuit comprising:

the signal input module (101) is used for inputting a control signal CON and short-circuiting a capacitor C1 when the external circuit does not need compensation;

the direct current reference module (102) is used for providing direct current working current, so that the NMOS tube I N1 and the NMOS tube II N2 are fully conducted, the function of the whole-course compensation of the oblique wave compensation circuit is realized, and when the external circuit does not need to be compensated, the compensation output module (103) does not output signals;

a compensation output module (103) for outputting a ramp compensation signal Islope;

the direct current reference module (102) is respectively and electrically connected with the signal input module (101) and the compensation output module (103).

2. The simple slope compensation circuit according to claim 1, wherein the signal input module (101) comprises a first current source I1, a second NMOS transistor N2, a third NMOS transistor N3, a third NMOS transistor R3 and a second NMOS transistor R2, one end of the first current source I1 is electrically connected with the third NMOS transistor R3 and the gate of the second NMOS transistor N2, the source of the second NMOS transistor N2 is connected with the second NMOS transistor R2, the drain is connected with the compensation output module (103), the other end of the second NMOS transistor R2 is grounded, the other end of the third NMOS transistor R3 is connected with the drain of the first capacitor C1 and the third NMOS transistor N3, the other end of the first capacitor C1 and the source of the third NMOS transistor N3 are grounded, and the gate of the third NMOS transistor N3 is connected with the control signal CON;

the direct current reference module (102) comprises a current source II I2, a resistor I R1, a resistor IV R4, an NMOS tube I N1 and a first current mirror unit, wherein one end of the current source II I2 is electrically connected with a grid electrode of the NMOS tube I N1 and the resistor IV R4, a drain electrode of the NMOS tube I N1 is connected with the first current mirror unit, a source electrode is connected with the resistor I R1, the other ends of the resistor I R1 and the resistor IV R4 are grounded, and the first current mirror unit is connected with the compensation output module (103);

3. The simple slope compensation circuit according to claim 2, wherein the compensation output module (103) comprises a second current mirror unit, the second current mirror unit comprises a PMOS transistor three P3 and a PMOS transistor four P4, the gate and the drain of the PMOS transistor three P3 are electrically connected to the gate of the PMOS transistor four P4 and the drain of the NMOS transistor two N2, and the drain of the PMOS transistor four P4 outputs the ramp compensation signal Islope.

4. The simple slope compensation circuit according to claim 3, wherein the first current mirror unit comprises a first PMOS transistor P1 and a second PMOS transistor P2, wherein the gate and the drain of the first PMOS transistor P1 are short-circuited to the drain of the first NMOS transistor N1, the gate of the first PMOS transistor P1 is connected with the gate of the second PMOS transistor P2, and the drain of the second PMOS transistor P2 is electrically connected with the gate and the drain of the third PMOS transistor P3.

5. The simple slope compensation circuit according to claim 4, wherein the first current source I1 and the second current source I2 are electrically connected to a power supply, and the sources of the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3 and the fourth PMOS transistor P4 are electrically connected to the power supply.

6. A method of generating a ramp compensation signal, implemented by a simple ramp compensation circuit according to any one of claims 1 to 5, characterized in that the ramp compensation circuit is in a compensation phase when the control signal CON is low; when the control signal CON is at a high level, the slope compensation circuit is in a non-compensation phase, the compensation phase comprising the following processes:

7. The method of generating a ramp compensation signal of claim 6 wherein the non-compensation phase comprises the following process:

at this time, the PMOS transistor three P3 and the PMOS transistor four P4 in the second current mirror do not generate current, and the output ramp compensation signal islope=0.

8. An electronic chip, comprising:

a ramp compensation module, which is the ramp compensation circuit of any one of claims 1 to 5, for outputting a ramp compensation signal Islope;

an enabling control module for controlling the enabling of the electronic chip;

an amplifier for detecting a change in the feedback signal FB voltage;

the switch MOS tube comprises an NMOS tube N4 and a PMOS tube P5.

9. The electronic chip of claim 8, wherein the amplifier is an error amplifier, an inverting input end of the error amplifier is input with a feedback signal FB, a non-inverting input end of the error amplifier is connected with a threshold voltage, an output end of the error amplifier is connected with an inverting input end of a comparator, the output end of the error amplifier is further electrically connected with a resistor five R5 and a capacitor two C2 which are connected in series, the output end of the comparator is connected with a logic control module, the logic control module is further connected with a current limiting detection module and a driving module, and the current limiting detection module is further electrically connected with a ramp compensation circuit;