CN111181552B - Bidirectional frequency synchronous oscillator circuit - Google Patents
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Abstract
A bidirectional frequency synchronous oscillator circuit comprises an oscillator main body module, a synchronous clock signal generation module, an external clock signal detection module and an internal and external clock signal mutual interference prevention module, wherein the oscillator main body module is connected with an external resistor to control a triangular wave signal generated by periodic charging and discharging of an external capacitor, and a charging and discharging circuit of the external capacitor and a related control circuit are arranged inside the oscillator main body module; when no clock signal exists outside the synchronous clock signal generation module, the synchronous clock signal generation module outputs the clock signal generated by the oscillator main body module and can be used as the clock signal of other power supply systems; the external clock signal detection module is used for detecting whether a clock signal exists outside or not, and synchronizing the external clock signal to the external clock signal through the oscillator control main body module when the external clock signal is detected; the internal and external clock signal mutual interference prevention module is used for avoiding the mutual interference of an external clock signal and a clock signal generated inside, so that the external clock signal and the clock signal generated inside cannot occur simultaneously, and logic errors are avoided.
Description
Technical Field
The invention belongs to the technical field of power management, and particularly relates to a bidirectional frequency synchronous oscillator circuit.
Background
The switching power supply is widely applied to power supply systems of various electronic products due to its excellent properties of light weight, high efficiency and the like. The clock generation circuit is an important module of the switching power supply control system, and the frequency of the generated clock signal determines the switching frequency of the switching power supply system. Generally, an electronic product includes a plurality of switching power supply modules, and the switching power supply modules operate at different switching frequencies, so that electromagnetic interference and switching noise generate strong interference to circuits. The effect is particularly serious when a plurality of switching power supplies are connected in parallel or in series. The switching frequency of the switching power supply is usually generated by an internal oscillator, and the frequency is fixed and cannot be changed along with the change of the external environment. At present, the switch power supply and an external clock have the same frequency function through a phase-locked loop, but the method needs to consider the loop stability of the phase-locked loop, the circuit design is complex, and the frequency needs to be locked for a long time. In addition, a circuit for switching a power supply to have a common frequency or a high frequency is also available at present, and the working principle of the circuit is that a high frequency signal discharges triangular waves of an oscillator in advance to realize a high frequency synchronization function. The design method cannot provide a clock signal with a frequency from the same frequency to the external lower clock frequency, and cannot provide the clock signal for other circuits.
Disclosure of Invention
Aiming at the defects that the frequency of an oscillator in the traditional switching power supply is fixed, a clock can not be provided for other circuits, the stability and complexity problems exist when the frequency of the oscillator is the same as that of an external clock, and only circuits from the same frequency to the high frequency exist, the invention provides a bidirectional frequency synchronous oscillator circuit which can synchronize to external high-frequency and low-frequency clock signals and also provide clock synchronous signals for other circuits, so that bidirectional frequency synchronization is realized, and the bidirectional frequency synchronous oscillator circuit can be widely applied to various frequency synchronous switching power supply systems.
The technical scheme of the invention is as follows:
a bidirectional frequency synchronous oscillator circuit comprises an oscillator main body module, a synchronous clock signal generation module, an external clock signal detection module and an internal and external clock signal mutual interference prevention module,
the oscillator main body module comprises a first constant current source, a switch, a first comparator, a second comparator, a third comparator, a first OR gate, a first NOT gate, a second NOT gate, a third NOT gate, a first NAND gate, a second NAND gate and a third NAND gate,
one end of the switch is connected with an input signal of the oscillator circuit, positive input ends of the first comparator and the second comparator, and a negative input end of the third comparator, and the other end of the switch is grounded after passing through the first constant current source;
the input signal of the oscillator circuit is a triangular wave signal;
the negative input end of the first comparator is connected with a first reference voltage, and the output end of the first comparator is connected with the first input end of the first OR gate;
the negative input end of the second comparator is connected with a second reference voltage, and the output end of the second comparator is connected with the second input end of the first OR gate and outputs a second marking signal;
the third input end of the first OR gate is connected with the output end of the external clock signal detection module, and the output end of the first OR gate is connected with the first input end of the second NAND gate after passing through the first NOT gate;
the positive input end of the third comparator is connected with a third reference voltage, and the output end of the third comparator is connected with the input end of the second NOT gate and the first input end of the first NOT gate;
the first reference voltage and the second reference voltage are high limit voltages, the third reference voltage is a low limit voltage, and the voltage value of the first reference voltage is higher than that of the second reference voltage;
the second input end of the first NAND gate is connected with an enable signal, and the output end of the first NAND gate is connected with the first input end of the third NAND gate;
the second input end of the second NAND gate is connected with the output end of the third NAND gate, the output end of the second NAND gate is connected with the second input end of the third NAND gate, and a switch control signal is output to control the switch to be turned on or turned off;
the input end of the third NOT gate is connected with the output end of the second NOT gate, and the output end of the third NOT gate outputs a first flag signal;
the synchronous clock signal generation module comprises a delay unit, a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, a seventh NOT gate, an eighth NOT gate, a ninth NOT gate, a first AND gate, a fourth NAND gate, a second constant current source, a first resistor, a first capacitor, a second capacitor, a first latch, a first Schmitt trigger, a second Schmitt trigger, a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube and a second NMOS tube MN2, wherein the first PMOS tube, the second PMOS tube, the first NMOS tube and the second NMOS tube MN2 are MOS tubes with driving capability;
the input end of the delay unit is connected with the first mark signal, and the output end of the delay unit is connected with the S input end of the first latch after passing through the fourth NOT gate;
the input end of the fifth NOT gate is connected with the second mark signal, and the output end of the fifth NOT gate is connected with the R input end of the first latch;
the input end of the eighth NOT gate is connected with an enabling signal, the grounding end of the eighth NOT gate is grounded after passing through the second constant current source, and the output end of the eighth NOT gate is connected with the input end of the first Schmitt trigger and is grounded after passing through the first capacitor;
the first input end of the first AND gate is connected with the output end of the first latch, the second input end of the first AND gate is connected with the output end of the first Schmitt trigger and the first input end of the fourth NAND gate, and the output end of the first AND gate is connected with the input end of the sixth NAND gate;
the input end of the seventh NOT gate is connected with the output end of the sixth NOT gate and the grid electrode of the second NMOS tube, and the output end of the seventh NOT gate is connected with the grid electrode of the second PMOS tube;
the second input end of the fourth NAND gate is connected with the second mark signal, and the output end of the fourth NAND gate is connected with the input end of the ninth NAND gate;
the ground end of the ninth NOT gate is grounded through the first resistor, and the output end of the ninth NOT gate is connected with the input end of the second Schmitt trigger and grounded through the second capacitor;
the source electrode of the first PMOS tube is connected with a power supply, the grid electrode of the first PMOS tube is connected with the grid electrode of the first NMOS tube and the output end of the second Schmitt trigger, and the drain electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube;
the drain electrode of the second NMOS tube is connected with the drain electrode of the second PMOS tube, generates an output clock signal of the oscillator circuit and is connected to the clock end of the oscillator circuit, and the source electrode of the second NMOS tube is connected with the drain electrode of the first NMOS tube;
the source electrode of the first NMOS tube is grounded;
the module for detecting the external clock signal comprises a fourth comparator, a fifth comparator, a second AND gate, a tenth NOT gate, an eleventh NOT gate and a second latch,
the negative input end of the fourth comparator is connected with a fourth reference voltage, the positive input end of the fourth comparator is connected with the input signal of the oscillator circuit, and the output end of the fourth comparator is connected with the first input end of the second AND gate;
the first flag signal is connected with the S input end of the second latch after passing through a tenth NOT gate, and the second flag signal is connected with the R input end of the second latch after passing through an eleventh NOT gate;
the second input end of the second AND gate is connected with the output end of the second latch, the third input end of the second AND gate is connected with the enable signal, and the output end of the second AND gate is connected with the enable end of the fifth comparator;
a negative input end of the fifth comparator is connected with a fifth reference voltage, a positive input end of the fifth comparator is connected with a clock end of the oscillator circuit, and an output end of the fifth comparator is used as an output end of the external clock signal detection module; the clock end of the oscillator circuit is also connected with an external clock signal;
the internal and external clock signal mutual interference prevention module comprises a twelfth NOT gate, a thirteenth NOT gate, a fourteenth NOT gate, a fifteenth NOT gate, a fifth NOT gate, a third AND gate, a third latch, a first D trigger, a second D trigger, a third PMOS tube, a third NMOS tube, a second resistor, a third capacitor and a third Schmitt trigger,
the first flag signal is connected with the S input end of the third latch after passing through a twelfth NOT gate, and the second flag signal is connected with the R input end of the third latch after passing through a thirteenth NOT gate;
the data input end of the first D flip-flop is connected with a high level, the clock input end of the first D flip-flop is connected with the output end of the external clock signal detection module, the setting end of the first D flip-flop is connected with the first flag signal, and the output end of the first D flip-flop is connected with the first input end of a fifth NAND gate;
the second input end of the fifth NAND gate is connected with the output end of the third latch, and the output end of the fifth NAND gate is connected with the grids of the third PMOS tube and the third NMOS tube;
the source electrode of the third PMOS tube is connected with a power supply, and the drain electrode of the third PMOS tube is connected with one end of the second resistor, one end of the third capacitor and the input end of the third Schmitt trigger;
the drain electrode of the third NMOS tube is connected with the other end of the second resistor, and the source electrode of the third NMOS tube is connected with the other end of the third capacitor and grounded;
the input end of the fourteenth NOT gate is connected with the output end of the third Schmitt trigger, and the output end of the fourteenth NOT gate is connected with the data input end of the second D trigger;
the clock input end of the second D trigger is connected with the first mark signal, and the output end of the second D trigger is connected with the first input end of the third AND gate after passing through the fifteenth NOT gate;
and the second input end of the third AND gate is connected with an enabling signal, and the output end of the third AND gate is connected with the enabling end of a second comparator in the oscillator main body module.
Specifically, an input signal of the oscillator circuit is generated by an external resistor and an external capacitor, one end of the external resistor is connected with a power supply, and the other end of the external resistor is grounded after passing through the external capacitor; the power supply charges the external capacitor through the external resistor, and the voltage on the external capacitor is an input signal of the oscillator circuit.
Specifically, the voltage value of the fourth reference voltage is higher than the voltage value of the third reference voltage.
The invention has the beneficial effects that: the invention provides a new external frequency synchronizing method, which avoids the adoption of a complex phase-locked loop structure in the traditional frequency synchronizing method; the bidirectional frequency synchronous oscillator circuit provided by the invention can not only be used for outputting clock signals from the same frequency to the high frequency, but also be used for outputting synchronous clock signals from the same frequency to the low frequency without increasing chip pins; the invention can realize more functions and improve the flexibility of chip application at the same cost.
Drawings
Fig. 1 is a circuit diagram of an oscillator main body module in a bi-directional frequency synchronous oscillator circuit according to the present invention.
Fig. 2 is a circuit diagram of a synchronous clock signal generating module in a bi-directional frequency synchronous oscillator circuit according to the present invention.
FIG. 3 is a circuit diagram of a block for detecting an external clock signal in a bi-directional synchronous oscillator circuit according to the present invention.
Fig. 4 is a circuit diagram of a module for preventing mutual interference between internal and external clock signals in a bi-directional frequency synchronous oscillator circuit according to the present invention.
FIG. 5 is a timing diagram of the output of a synchronous clock signal from a bi-directional synchronous frequency oscillator circuit according to the present invention.
FIG. 6 is a timing diagram of a bi-directional synchronous oscillator circuit according to the present invention for synchronizing to a high frequency clock signal.
FIG. 7 is a timing diagram of a dual-way synchronous oscillator circuit for synchronizing to a low frequency clock signal according to the present invention.
Detailed Description
The invention is further illustrated with reference to the figures and the specific embodiments.
The invention provides a bidirectional frequency synchronous oscillator circuit, which comprises four parts, namely an oscillator main body module, a synchronous clock signal generation module, an external clock signal detection module and an internal and external clock signal mutual interference prevention module shown in figures 1, 2, 3 and 4. The oscillator main body module is connected with an external resistor to control a triangular wave signal generated by periodic charging and discharging of an external capacitor, and a charging and discharging circuit of the external capacitor and a related control circuit are arranged in the oscillator main body module; when no clock signal exists outside the synchronous clock signal generation module, the synchronous clock signal generation module outputs the clock signal generated by the oscillator main body module and can be used as the clock signal of other power supply systems; the external clock signal detection module is mainly used for detecting whether a clock signal exists outside or not, and synchronizing the external clock signal to the external clock signal by controlling the oscillator main body module when the external clock signal is detected; the internal and external clock signal mutual interference prevention module is mainly used for avoiding the mutual interference between an external clock signal and a clock signal generated inside, and the oscillator circuit can not generate an internal clock signal when the external clock signal is detected; if no clock signal exists outside, the oscillator circuit generates a clock signal inside; therefore, the two will not occur simultaneously, avoiding logic errors.
As shown in fig. 1, the oscillator main body module includes a first constant current source Id1, a switch, a first comparator CP1, a second comparator CP2, a third comparator CP3, a first OR gate OR1, a first not gate INV1, a second not gate INV2, a third not gate INV3, a first NAND gate NAND1, a second NAND gate NAND2, and a third NAND gate NAND3, one end of the switch is connected to an input signal RTCT of the oscillator circuit, positive input terminals of the first comparator CP1 and the first comparator CP2, and a negative input terminal of the third comparator CP3, and the other end thereof is grounded after passing through the first constant current source Id 1; a negative input end of the first comparator CP1 is connected to the first reference voltage Vref1, and an output end thereof is connected to a first input end of the first OR gate OR 1; a negative input end of the first comparator CP2 is connected to the second reference voltage Vref2, and an output end thereof is connected to a second input end of the first OR gate OR1 and outputs a second flag signal RTCT _ Max; the third input end of the first OR gate OR1 is connected with the output end of the external clock signal detection module, and the output end of the first OR gate OR1 is connected with the first input end of the second NAND gate NAND2 after passing through the first not gate INV 1; a positive input end of the third comparator CP3 is connected to the third reference voltage Vref3, and an output end thereof is connected to an input end of the second not gate INV2 and a first input end of the first not gate NAND 1; the second input end of the first NAND gate NAND1 is connected with an enable signal, and the output end of the first NAND gate NAND1 is connected with the first input end of the third NAND gate NAND 3; the second input end of the second NAND gate NAND2 is connected with the output end of the third NAND gate NAND3, the output end of the second NAND gate NAND2 is connected with the second input end of the third NAND gate NAND3, and a switch control signal Id _ Ctrl is output to control the on and off of the switch; an input end of the third not gate is connected to an output end of the second not gate INV2, and an output end thereof outputs the first flag signal Clr _ H.
An input signal RTCT of the oscillator circuit is a triangular wave signal, as shown in figure 1, the input signal RTCT of the oscillator circuit is generated by an external resistor RT and an external capacitor CT, one end of the external resistor RT is connected with a power supply VREF, and the other end of the external resistor RT is grounded after passing through the external capacitor CT; and the power supply VREF charges the external capacitor CT through the external resistor RT, and the voltage on the external capacitor CT is the input signal RTCT of the oscillator circuit.
The first reference voltage Vref1 and the second reference voltage Vref2 are high limit voltages, the third reference voltage Vref3 is a low limit voltage, and in order to realize that the oscillator can reach a low frequency signal at the same frequency, the voltage value of the first reference voltage Vref1 needs to be set to be higher than the voltage value of the second reference voltage Vref2, when the second comparator is not enabled, the high limit voltage is increased from the second reference voltage Vref2 to the first reference voltage Vref1, so that the charging time of the external capacitor CT is increased, and the frequency is reduced. The enabling signal of the second comparator is generated by the internal and external clock signal mutual interference prevention module, when the internal and external clock signal mutual interference prevention module detects an external clock signal, the enabling signal CP2_ EN of the second comparator is output to be at a low level, and the second comparator CP2 is invalid; when the internal and external clock signal mutual interference prevention module does not detect the external clock signal, the enable signal CP2_ EN of the second comparator is output to be at a high level, and the second comparator CP2 works normally.
When the voltage on the external capacitor CT (i.e. the input signal RTCT of the oscillator circuit) reaches the oscillator high-limit voltage (when the second comparator CP2 works normally, the input signal RTCT of the oscillator circuit is compared with the second reference voltage Vref2, and when the second comparator CP2 fails, the input signal RTCT of the oscillator circuit is compared with the first reference voltage Vref 1), the output of the second comparator CP2 (OR the first comparator CP 1) is high, and the switch control signal Id _ Ctrl is output to control the switch to be closed after passing through the first OR gate OR1, the first not gate INV1, the second NAND gate 2 and the third NAND gate NAND3, so as to control the external capacitor CT to discharge to the ground through the first constant current source Id 1; when the voltage on the external capacitor CT drops to the low-limit voltage level third reference voltage Vref3, the third comparator CP3 outputs a high-level pulse, and outputs a signal switch control signal Id _ Ctrl to control the switch to be turned off after passing through the first OR gate OR1, the first not gate INV1, the second NAND gate NAND2, and the third NAND gate NAND3, so as to turn off the first constant current source Id1, and the external capacitor CT completes discharging, thereby completing charging and discharging of one cycle.
According to the node charging and discharging current conditions of the external resistor RT and the capacitor CT, the charging time T determined by the oscillator circuit can be obtained ON Comprises the following steps:
discharge time T OFF Comprises the following steps:
the key of the present invention is to realize the bidirectional frequency synchronization function based on the main oscillator circuit, and the process is described below with reference to specific circuits of other modules.
As shown in fig. 2, the synchronous clock signal generating module includes a delay unit, a fourth not gate INV4, a fifth not gate INV5, a first Latch1, a first AND gate AND1, a sixth not gate INV6, a seventh not gate INV7, an eighth not gate INV8, a second constant current source Id2, a first capacitor C1, a first smith flip-flop SMIT1, a fourth NAND gate NAND4, a ninth not gate INV9, a first resistor R1, a second capacitor C2, a second smith flip-flop SMIT2, a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, AND a second NMOS transistor MN2, wherein an input end of the delay unit is connected to a first flag signal Clr _ H, AND an output end thereof is connected to an S input end of the first Latch1 through the fourth not gate INV 4; the input end of the fifth not gate INV5 is connected to the second flag signal RTCT _ Max, and the output end thereof is connected to the R input end of the first Latch 1; the input end of the eighth not gate INV8 is connected to the enable signal EN, the ground end thereof is grounded through the second constant current source Id2, and the output end thereof is connected to the input end of the first schmitt trigger SMIT1 and is grounded through the first capacitor C1; a first input end of the first AND gate AND1 is connected with an output end of the first Latch1, a second input end of the first AND gate AND1 is connected with an output end of the first schmitt trigger SMIT1 AND a first input end of the fourth NAND gate NAND4, AND an output end of the first AND gate AND1 is connected with an input end of the sixth not gate INV 6; the input end of the seventh not gate INV7 is connected to the output end of the sixth not gate INV6 and the gate of the second NMOS transistor MN2, and the output end thereof is connected to the gate of the second PMOS transistor MP 2; a second input end of the fourth NAND gate NAND4 is connected with the second flag signal RTCT _ Max, and an output end of the fourth NAND gate NAND4 is connected with an input end of the ninth not gate INV 9; the grounding end of the ninth not gate INV9 is grounded through the first resistor R1, and the output end thereof is connected to the input end of the second schmitt trigger SMIT2 and is grounded through the second capacitor C2; the source electrode of the first PMOS tube MP1 is connected with a power supply VREF, the grid electrode of the first PMOS tube MP1 is connected with the grid electrode of the first NMOS tube MN1 and the output end of the second Schmitt trigger SMIT2, and the drain electrode of the first PMOS tube MP1 is connected with the source electrode of the second PMOS tube MP 2; the drain electrode of the second NMOS tube MN2 is connected with the drain electrode of the second PMOS tube MP2, generates an output clock signal of the oscillator circuit and is connected with the clock end SYNC of the oscillator circuit, and the source electrode of the second NMOS tube MN2 is connected with the drain electrode of the first NMOS tube MN 1; the source electrode of the first NMOS transistor MN1 is grounded.
The first marking signal Clr _ H is a marking signal for starting charging of the external capacitor CT, is a square wave pulse and is short in duration; the second flag signal RTCT _ Max is a flag signal that the external capacitor CT starts to discharge when no external clock signal is present, and is a square wave pulse with short duration. After the external electrification of the chip is finished, the enable signal EN is high, and after a certain time delay is generated by the second constant current source Id2, the first capacitor C1 and the first Schmitt trigger SMIT1, the subsequent logic starts to work normally. When the first flag signal Clr _ H is high, after a certain delay by the delay unit, the output of the first Latch1 is a high level; when the second flag signal RTCT _ Max is a high level pulse, the output of the first Latch1 is a low level, the output signal Ctrl _ L of the sixth inverter INV6 and the output signal Ctrl _ H of the seventh inverter INV7 are a high level and a low level, respectively, and the second NMOS transistor MN2 and the second PMOS transistor MP2 are both in a conducting state. The ninth not gate INV9 charges the second capacitor C2 quickly, the second SMIT2 outputs a low level, the first PMOS transistor MP1 is turned on, and the clock terminal SYNC of the oscillator circuit is pulled to a high level. When the second flag signal RTCT _ Max of the narrow square wave pulse changes to a low level, the second capacitor C2 discharges to the ground through the first resistor R1, after a certain time, the second capacitor C2 is at a low level, the output of the second schmitt trigger SMIT2 is high, and the clock end SYNC of the oscillator circuit is pulled to the ground potential. Due to the presence of the first resistor R1, the square wave signal output by the clock terminal SYNC of the oscillator circuit, i.e. the output clock signal of the oscillator circuit, is widened in width with respect to the second flag signal RTCT _ Max. The output clock signal output by the clock end SYNC of the oscillator circuit can be used as a synchronous clock signal of other chips, so that the output first PMOS transistor MP1, the second PMOS transistor MP2, the first NMOS transistor MN1, and the second NMOS transistor MN2 need to have certain driving capability, and the driving capability of the first PMOS transistor MP1, the second PMOS transistor MP2, the first NMOS transistor MN1, and the second NMOS transistor MN2 can be set according to the load condition. The time delay of the first flag signal Clr _ H is needed to output a high-frequency clock signal with a high duty ratio, because the discharge time of the external capacitor CT is short when the high-frequency clock signal with the high duty ratio is generated, and the discharge time may be smaller than the output clock signal of the circuit; the first NMOS tube MN1 and the second NMOS tube MN2 are turned off in advance, and an output clock signal of a clock end SYNC of the oscillator circuit is at a middle potential; this may cause subsequent logic to be in error. The enable signal EN needs to be delayed because the output clock signal and the external clock signal are likely to interfere with each other when the chip is just built, so the module needs to be shielded in the initial stage, and the module starts to function after being stabilized.
As shown in fig. 3, the external clock signal detecting module includes a fourth comparator CP4, a fifth comparator CP5, a second AND gate AND2, a tenth not gate INV10, an eleventh not gate INV11, AND a second Latch2, wherein a negative input terminal of the fourth comparator CP is connected to the fourth reference voltage Vref4, a positive input terminal thereof is connected to the input signal RTCT of the oscillator circuit, AND an output terminal thereof is connected to the first input terminal of the second AND gate AND 2; the first flag signal Clr _ H passes through the tenth inverter INV10 and then is connected to the S input terminal of the second Latch2, and the second flag signal RTCT _ Max passes through the eleventh inverter INV11 and then is connected to the R input terminal of the second Latch 2; a second input end of the second AND gate AND2 is connected to an output end of the second Latch2, a third input end thereof is connected to the enable signal EN, AND an output end thereof is connected to an enable end of the fifth comparator CP 5; the negative input end of the fifth comparator CP5 is connected to the fifth reference voltage Vref5, the positive input end thereof is connected to the clock end of the oscillator circuit, and the output end thereof, which is used as the output end of the external clock signal detection module, is connected to the first OR gate OR1 in the oscillator main module.
The clock terminal of the oscillator circuit is also connected with an external clock signal, namely the clock terminal of the oscillator circuit is connected with the external clock signal and outputs an output clock signal generated by the oscillator circuit when the external clock signal is not detected. The clock terminal SYNC of the oscillator circuit connected to the positive input terminal of the fifth comparator CP5 is used to detect the external clock signal, AND when the Q output terminal of the second Latch2 is high, which is determined by the first flag signal Clr _ H AND the second flag signal RTCT _ Max, AND when the input signal RTCT voltage of the oscillator circuit exceeds the fourth reference voltage Vref4, the output DT _ H of the fourth comparator CP4 is high, the enable signal CP5_ EN of the fifth comparator CP5 output by the second AND gate AND2 is high, AND the fifth comparator CP5 starts to operate. When the clock end SYNC voltage of the oscillator circuit exceeds a fifth reference voltage Vref5 (the fifth reference voltage Vref5 is used for determining a high level threshold of the external clock signal), an output signal SYNC _ H of the fifth comparator CP5 is a high level pulse signal, the output signal SYNC _ H of the fifth comparator CP5 is used as an output signal of the external clock signal detection module and is connected to an input end of a first OR gate OR1 in the oscillator main body module, and the high level pulse signal SYNC _ H controls a first constant current source Id1 to discharge to the external capacitor CT through the first nor gate OR1, so that synchronization to the external clock signal is realized.
In some embodiments, the fourth reference voltage Vref4 is set to be higher than the low-limit voltage of the input signal RTCT of the oscillator circuit (i.e., the third reference voltage Vref 3), so as to prevent the external capacitor CT from being charged and discharged for a short time when the external clock frequency is too high relative to the frequency determined by the oscillator of the present invention, and subsequent logic does not respond in time, which causes a certain disorder, thereby determining that the oscillator of the present invention can synchronize the highest frequency of the external clock signal. The first flag signal Clr _ H is at a high level, the Q output terminal of the second Latch2 is at a high level, and the Q output terminal of the second Latch2 is at a low level when the second flag signal RTCT _ Max is high, thereby ensuring that the external detection external clock signal is only in the charging stage of the externally-hung capacitor CT; as can be seen from fig. 2, the output synchronous clock signal detects that the generation time of the external clock signal and the internal clock signal is in different time periods in the discharging stage of the external capacitor CT, so as to avoid the occurrence of both signals and cause the circuit to be abnormal.
The internal AND external clock signal mutual interference prevention module is used for preventing the external clock signal AND the clock signal generated inside from mutual interference, as shown in fig. 4, the internal AND external clock signal mutual interference prevention module comprises a twelfth not gate INV12, a thirteenth not gate INV13, a third Latch3, a first D flip-flop DFF1, a fifth not gate NAND5, a third PMOS transistor MP3, a third NMOS transistor MN3, a first resistor R1, a third capacitor C3, a third schmitt trigger SMIT3, a fourteenth not gate INV14, a second D flip-flop DFF2, a fifteenth not gate INV15 AND a third AND gate AND3, a first flag signal Clr _ H passes through the twelfth not gate INV12 AND then is connected to the S input end of the third Latch3, AND a second flag signal rtmax passes through the thirteenth not gate INV13 AND then is connected to the R input end of the third Latch 3; the data input end of the first D flip-flop DFF1 is connected to a high level, the clock input end thereof is connected to the SYNC _ H signal output by the output end of the external clock signal detection module, the set end thereof is connected to the first flag signal Clr _ H, and the output end thereof is connected to the first input end of the fifth NAND gate NAND 5; a second input end of the fifth NAND gate NAND5 is connected with an output end of the third Latch3, and an output end of the fifth NAND gate NAND5 is connected with gates of a third PMOS transistor MP3 and a third NMOS transistor MN 3; the source electrode of the third PMOS tube MP3 is connected with a power supply VREF, and the drain electrode of the third PMOS tube MP3 is connected with one end of the second resistor R2, one end of the third capacitor C3 and the input end of the third Schmitt trigger SMIT 3; the drain electrode of the third NMOS transistor MN3 is connected with the other end of the second resistor R2, and the source electrode of the third NMOS transistor MN3 is connected with the other end of the third capacitor C3 and grounded; an input end of the fourteenth not gate INV14 is connected to the output end of the third schmitt trigger SMIT3, and an output end thereof is connected to the data input end of the second D flip-flop DFF 2; a clock input end of the second D flip-flop DFF2 is connected to the first flag signal Clr _ H, AND an output end thereof is connected to a first input end of a third AND gate AND3 after passing through a fifteenth not gate INV 15; a second input end of the third AND gate AND3 is connected to the enable signal EN, AND an output end thereof outputs an enable signal CP2_ EN of the second comparator CP2 in the oscillator main block, which is connected to an enable end of the second comparator CP 2.
The Q output of the third Latch3 is kept at a high state during the charging phase of the external capacitor CT (the operation principle is similar to the second Latch2 of the block for detecting the external clock signal in fig. 3). When detecting that the output signal SYNC _ H of the external clock signal module is at a high level, the first flip-flop DFF1 transmits a high level signal to the input end of the fifth NAND gate NAND5, so that the output of the fifth NAND gate NAND5 is at a low level, the third PMOS transistor MP3 rapidly charges the third capacitor C3 to a high level, and thus the D-terminal of the second flip-flop DFF2 is at a high level; at this time, because the output signal SYNC _ H of the module for detecting the external clock signal is high, the external capacitor CT starts to discharge, the second flag signal RTCT _ Max cannot be generated, and the Q output end of the third Latch3 is always kept high; when the external capacitor CT finishes discharging and starts charging again, the first flag signal Clr _ H is high, the Q output terminal of the DFF1 of the first D flip-flop is low, and after the delay of the second resistor R2 and the third capacitor C3, the output input terminal, i.e., the D terminal, of the second D flip-flop DFF2 maintains a high level for a period of time, so as to ensure that when the rising edge of the first flag signal Clr _ H arrives, the data input terminal, i.e., the D terminal, of the second D flip-flop DFF2 can sample a high level signal. Then, the third AND gate AND3 outputs the enable signal CP2_ EN of the second comparator CP2 at a low level, which makes the output of the second comparator CP2 in the oscillator main block always low, AND the second comparator CP2 fails, that is, the second flag signal RTCT _ Max always remains at a low level, at this time, the high limit comparator of the oscillator is determined by the first comparator CP1, AND the first reference voltage Vref1 determines the lowest frequency that the oscillator can reach. Therefore, when the resistance value of the external resistor RT and the capacitance value of the external capacitor CT are determined, the oscillator provided by the invention can be synchronized to an external clock signal, and the frequency can be high or low. If there is no external clock signal, the output signal SYNC _ H of the external clock signal detection module is always at a low level, and the forward output terminal of the second D flip-flop DFF2 is at a low level before the rising edge of the first flag signal Clr _ H arrives. Therefore, the enable signal CP2_ EN of the second comparator CP2 output from the third AND gate AND3 is always at a high level, AND the second comparator CP2 is in a normal operation state. The second flag signal RTCT _ Max is normally generated and a synchronous clock signal can still be generated for use by other modules. When the synchronous clock signal is generated, the fifth comparator CP5 in fig. 3 may be temporarily in an operating state, the SYNC _ H signal temporarily outputs a high level, and after the second Latch2 responds, the fifth comparator CP5 is disabled, and the SYNC _ H signal is at a low level; since the second flag signal RTCT _ Max is in a high level pulse state, the data input terminal, i.e., the D terminal, of the second D flip-flop is always kept in a low level state until the rising edge of the first flag signal Clr _ H arrives, so that the output signal CP2_ EN of the third AND gate AND3 is still in a high level in the next period.
FIG. 5 is a timing diagram of the synchronous clock signal output by the dual-direction synchronous oscillator circuit according to the present invention. When the voltage of the input signal RTCT of the oscillator circuit reaches the second reference voltage Vref2, the second flag signal RTCT _ Max outputs a narrow pulse, and a clock signal is output at the clock terminal SYNC after passing through a certain expander circuit. When the input signal RTCT voltage of the oscillator circuit is higher than the fourth reference voltage Vref4, the output signal DT _ H of the fourth comparator CP4 is at a high level. DFF2_ D is a data input terminal of the second flip-flop, i.e., a D terminal signal, and in a discharging stage of an input signal RTCT of the oscillator circuit, although the SYNC _ H signal is high, the output of the first D flip-flop is low, so the D terminal of the second D flip-flop is maintained in a low level state; during the RTCT charging phase, the Q output terminal of the first D flip-flop DFF1 is maintained at a low level, so the data input terminal, i.e., the D terminal, of the second D flip-flop DFF2 is maintained at a low level state. Therefore, when there is no external clock signal, the oscillator provided by the present invention generates an output clock signal at the clock end SYNC, which can be used as a synchronous clock signal of other circuits.
Fig. 6 is a timing diagram of a bidirectional frequency synchronous oscillator circuit according to the present invention for synchronizing to a high frequency clock signal. The external clock signal is detected only when the external capacitor CT is charged and the voltage of the input signal RTCT of the oscillator circuit is higher than the fourth reference voltage Vref4, so that the first two SYNC pulse signals are not detected, and the second flag signal RTCT _ Max outputs a high-level pulse signal. When an external high-frequency clock signal is detected to appear at the clock end SYNC, the external capacitor CT starts to discharge, the SYNC _ H signal is output to be high, the data input end, namely the D end, of the second D trigger DFF2 still keeps a high level state when the rising edge of the first flag signal Clr _ H arrives, so that the output signal CP2_ EN outputs a low level, the second comparator CP2 does not work, and the input signal RTCT of each period oscillator circuit is synchronized to the external high-frequency clock signal.
FIG. 7 is a timing diagram of a synchronous to low frequency clock signal of a dual-way synchronous oscillator circuit according to the present invention. The clock terminal SYNC first signal is not detected because the input signal RTCT of the oscillator circuit has a voltage smaller than the fourth reference voltage Vref4. The second flag signal RTCT _ Max outputs a narrow pulse. When the clock end SYNC detects an external low frequency clock signal, CP2_ EN is at a low level, so that the second comparator CP2 does not operate, and the first comparator CP1 is still in an operating state. At this time, the RTCT high-limit reference voltage rises from the second reference voltage Vref2 to the first reference voltage Vref1, and thus can be synchronized to the external low-frequency clock signal; the lowest frequency of the external clock signal is determined by the first reference voltage Vref 1. The clock end SYNC detects an external clock signal, and the external capacitor CT starts to discharge, so that the period is repeated, and the RTCT can be synchronized to the external low-frequency clock signal. Also, since the second comparator CP2 is disabled, the second flag signal RTCT _ Max does not output a pulse signal, and the internal clock signal generation circuit is in a non-operating state. Therefore, the clock end SYNC serves as both an output pin and an input pin, and after the relevant logic processing, the two pins do not interfere with each other, thereby potentially affecting the circuit.
In summary, the present invention provides a bidirectional frequency synchronous oscillator circuit, which detects whether a clock signal exists outside through an external clock signal detection module, enables a second comparator through an internal and external clock signal interference prevention module, enables the second comparator when the external clock signal is not detected, compares an RTCT signal with a second reference voltage to control charging and discharging of an external capacitor, and generates an output clock signal inside the oscillator circuit; when the external clock signal is detected, the second comparator is not enabled, and the output signal of the external clock signal detection module controls the external capacitor CT to discharge, so that the same frequency with the external clock signal is realized. One clock pin is used for generating an output clock signal of an internal circuit and synchronizing the output clock signal to an external clock signal, mutual interference cannot be generated, the clock signal from the same frequency to the high frequency and the clock signal from the same frequency to the low frequency can be generated, and the application range is wide.
Those skilled in the art, having the benefit of this disclosure, may effect numerous modifications thereto and changes may be made without departing from the scope of the invention in its broader aspects.
Claims (3)
1. A bidirectional frequency synchronous oscillator circuit is characterized by comprising an oscillator main body module, a synchronous clock signal generation module, an external clock signal detection module and an internal and external clock signal mutual interference prevention module,
the oscillator main body module comprises a first constant current source, a switch, a first comparator, a second comparator, a third comparator, a first OR gate, a first NOT gate, a second NOT gate, a third NOT gate, a first NAND gate, a second NAND gate and a third NAND gate,
one end of the switch is connected with an input signal of the oscillator circuit, positive input ends of the first comparator and the second comparator, and a negative input end of the third comparator, and the other end of the switch is grounded after passing through the first constant current source;
the input signal of the oscillator circuit is a triangular wave signal;
the negative input end of the first comparator is connected with a first reference voltage, and the output end of the first comparator is connected with the first input end of the first OR gate;
the negative input end of the second comparator is connected with a second reference voltage, and the output end of the second comparator is connected with the second input end of the first OR gate and outputs a second mark signal;
the third input end of the first OR gate is connected with the output end of the external clock signal detection module, and the output end of the first OR gate is connected with the first input end of the second NAND gate after passing through the first NOT gate;
the positive input end of the third comparator is connected with a third reference voltage, and the output end of the third comparator is connected with the input end of the second NOT gate and the first input end of the first NAND gate;
the first reference voltage and the second reference voltage are high limit voltages, the third reference voltage is a low limit voltage, and the voltage value of the first reference voltage is higher than that of the second reference voltage;
the second input end of the first NAND gate is connected with an enable signal, and the output end of the first NAND gate is connected with the first input end of the third NAND gate;
the second input end of the second NAND gate is connected with the output end of the third NAND gate, and the output end of the second NAND gate is connected with the second input end of the third NAND gate and outputs a switch control signal to control the on and off of the switch;
the input end of the third NOT gate is connected with the output end of the second NOT gate, and the output end of the third NOT gate outputs a first mark signal;
the synchronous clock signal generation module comprises a delay unit, a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, a seventh NOT gate, an eighth NOT gate, a ninth NOT gate, a first AND gate, a fourth NAND gate, a second constant current source, a first resistor, a first capacitor, a second capacitor, a first latch, a first Schmitt trigger, a second Schmitt trigger, a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube and a second NMOS tube MN2, wherein the first PMOS tube, the second PMOS tube, the first NMOS tube and the second NMOS tube MN2 are MOS tubes with driving capability;
the input end of the delay unit is connected with the first mark signal, and the output end of the delay unit is connected with the S input end of the first latch after passing through the fourth NOT gate;
the input end of the fifth NOT gate is connected with the second mark signal, and the output end of the fifth NOT gate is connected with the R input end of the first latch;
the input end of the eighth NOT gate is connected with an enabling signal, the grounding end of the eighth NOT gate is grounded after passing through the second constant current source, and the output end of the eighth NOT gate is connected with the input end of the first Schmitt trigger and is grounded after passing through the first capacitor;
the first input end of the first AND gate is connected with the output end of the first latch, the second input end of the first AND gate is connected with the output end of the first Schmitt trigger and the first input end of the fourth NAND gate, and the output end of the first AND gate is connected with the input end of the sixth NAND gate;
the input end of the seventh NOT gate is connected with the output end of the sixth NOT gate and the grid electrode of the second NMOS tube, and the output end of the seventh NOT gate is connected with the grid electrode of the second PMOS tube;
the second input end of the fourth NAND gate is connected with the second mark signal, and the output end of the fourth NAND gate is connected with the input end of the ninth NAND gate;
the ground end of the ninth NOT gate is grounded through the first resistor, and the output end of the ninth NOT gate is connected with the input end of the second Schmitt trigger and grounded through the second capacitor;
the source electrode of the first PMOS tube is connected with a power supply, the grid electrode of the first PMOS tube is connected with the grid electrode of the first NMOS tube and the output end of the second Schmitt trigger, and the drain electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube;
the drain electrode of the second NMOS tube is connected with the drain electrode of the second PMOS tube, generates an output clock signal of the oscillator circuit and is connected to the clock end of the oscillator circuit, and the source electrode of the second NMOS tube is connected with the drain electrode of the first NMOS tube;
the source electrode of the first NMOS tube is grounded;
the module for detecting the external clock signal comprises a fourth comparator, a fifth comparator, a second AND gate, a tenth NOT gate, an eleventh NOT gate and a second latch,
the negative input end of the fourth comparator is connected with a fourth reference voltage, the positive input end of the fourth comparator is connected with the input signal of the oscillator circuit, and the output end of the fourth comparator is connected with the first input end of the second AND gate;
the first flag signal is connected with the S input end of the second latch after passing through a tenth NOT gate, and the second flag signal is connected with the R input end of the second latch after passing through an eleventh NOT gate;
a second input end of the second AND gate is connected with an output end of the second latch, a third input end of the second AND gate is connected with an enable signal, and an output end of the second AND gate is connected with an enable end of the fifth comparator;
a negative input end of the fifth comparator is connected with a fifth reference voltage, a positive input end of the fifth comparator is connected with a clock end of the oscillator circuit, and an output end of the fifth comparator is used as an output end of the external clock signal detection module; the clock end of the oscillator circuit is also connected with an external clock signal;
the internal and external clock signal mutual interference prevention module comprises a twelfth NOT gate, a thirteenth NOT gate, a fourteenth NOT gate, a fifteenth NOT gate, a fifth NOT gate, a third AND gate, a third latch, a first D trigger, a second D trigger, a third PMOS tube, a third NMOS tube, a second resistor, a third capacitor and a third Schmitt trigger,
the first flag signal is connected with the S input end of the third latch after passing through a twelfth NOT gate, and the second flag signal is connected with the R input end of the third latch after passing through a thirteenth NOT gate;
the data input end of the first D flip-flop is connected with a high level, the clock input end of the first D flip-flop is connected with the output end of the external clock signal detection module, the setting end of the first D flip-flop is connected with the first flag signal, and the output end of the first D flip-flop is connected with the first input end of a fifth NAND gate;
the second input end of the fifth NAND gate is connected with the output end of the third latch, and the output end of the fifth NAND gate is connected with the grids of the third PMOS tube and the third NMOS tube;
the source electrode of the third PMOS tube is connected with a power supply, and the drain electrode of the third PMOS tube is connected with one end of the second resistor, one end of the third capacitor and the input end of the third Schmitt trigger;
the drain electrode of the third NMOS tube is connected with the other end of the second resistor, and the source electrode of the third NMOS tube is connected with the other end of the third capacitor and grounded;
the input end of the fourteenth NOT gate is connected with the output end of the third Schmitt trigger, and the output end of the fourteenth NOT gate is connected with the data input end of the second D trigger;
the clock input end of the second D trigger is connected with the first mark signal, and the output end of the second D trigger is connected with the first input end of the third AND gate after passing through the fifteenth NOT gate;
and the second input end of the third AND gate is connected with an enabling signal, and the output end of the third AND gate is connected with the enabling end of a second comparator in the oscillator main body module.
2. The bi-directional frequency synchronous oscillator circuit according to claim 1, wherein the input signal of the oscillator circuit is generated by an external resistor and an external capacitor, one end of the external resistor is connected with a power supply, and the other end of the external resistor is grounded after passing through the external capacitor; the power supply charges the external capacitor through the external resistor, and the voltage on the external capacitor is an input signal of the oscillator circuit.
3. The bidirectional frequency synchronous oscillator circuit according to claim 1 or 2, wherein a voltage value of the fourth reference voltage is higher than a voltage value of the third reference voltage.
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| CN116599465B (en) * | 2023-07-19 | 2023-12-08 | 芯天下技术股份有限公司 | Oscillator circuit and memory chip |
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