JP2006030136A - Real-time clock circuit, semiconductor integrated circuit, and watt-hour meter device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To generate a clock signal for highly-accurate time clocking by correcting an oscillation error generated from an individual error or the like of a vibrator used for a real-time clock circuit. <P>SOLUTION: This clock circuit is equipped with a frequency divider 12 for generating a window pulse Pw1 from a reference clock signal CLKref, oscillation circuits 19, 25 for generating clock signals CLK1, CLK2, first and second selection circuits 26, 29, the first AND gate circuit 13 into which a clock signal selected by the first selection circuit and the window pulse are inputted, a counter 30 for counting outputs from the second selection circuit, a resister 31, a comparator 32 for comparing count data from the counter 30 with data stored in the resister and generating a clock signal CLK3 for time clocking, the second AND gate circuit 34 into which the clock signals CLK3, CLK2 are inputted, and a counter 35 for counting outputs from the second AND gate circuit. The clock circuit is characterized by storing count data from the first counter or count data from the second counter in the resister 31. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a real-time clock circuit for generating a clock signal used for timekeeping, a semiconductor integrated circuit incorporating the clock signal, and a watt-hour meter device mounting the semiconductor integrated circuit.

  Time counting is performed by counting a clock signal generated by the real-time clock circuit with a counter or the like. In a conventional simple real-time clock circuit, an oscillation circuit using a crystal resonator that oscillates at 32.768 KHz is used. The clock signal generated by this oscillation circuit is divided by 16 by a frequency divider, and this is used as a 1-second pulse signal. Further, the 1-second pulse signal is sequentially counted by the minute counter and the time counter, whereby a timepiece can be configured.

  However, crystal resonators originally have individual errors (variations). In addition, the oscillation frequency fluctuates not a little depending on the error of the load capacitor used in the oscillation circuit, and also on the usage environment temperature. Thus, since several factors are intertwined, it is very difficult to predict an oscillation error in advance in an oscillation circuit using a crystal resonator. For example, if an error of one clock occurs when counting one second using a 32.768 kHz crystal unit, the characteristic of the crystal unit has an error of (1/32768) = 30.5 ppm. This error is approximately 2.63 seconds ((1/32768) × 60 × 60 × 24) per day, and approximately 81.53 seconds per month (31 days). Such a variation error is less likely to be a problem in a system in which the time can be readjusted even after a real-time clock circuit is incorporated into the product. However, if the time cannot be adjusted easily, the time error increases as time elapses.

  One example of a product incorporating a real-time clock circuit is a watt-hour meter device. In this watt-hour meter device, a power charge is automatically calculated based on the amount of power used. In some cases, the midnight power charge is set at a lower price than the daytime power charge. In such a case, it is necessary to change the price per unit power amount according to the time zone and calculate the power charge. At that time, in order to determine the time zone, it is necessary to measure the time accurately. However, if the time cannot be adjusted, the time error increases as time elapses, making it impossible to calculate the power rate accurately.

In Patent Document 1, a reference clock is input from the outside to an electronic device, and the oscillation clock of the crystal unit is counted for a predetermined measurement time measured using the reference clock, and the time is measured using the reference clock. During the measurement time, the clock output of the real-time clock circuit with error correction function is counted, the correction value is calculated by taking the difference between the count value of the measurement result and the known adjustment target count value, and the calculated correction value is A time correction method and apparatus for a real time clock set in a real time clock circuit with an error correction function is described.
JP 2003-270369 A

  The present invention has been made in consideration of the above-described circumstances, and an object of the present invention is to provide a real-time signal that can generate a clock signal for accurate time measurement even if the clock signal generated in the oscillation circuit varies. It is to provide a clock circuit.

  Another object of the present invention is to provide a semiconductor integrated circuit having a built-in real-time clock circuit that can generate a clock signal for performing accurate timing even if the clock signal generated by the oscillation circuit varies. .

  Furthermore, an object of the present invention is to incorporate a real-time clock circuit that counts clock signals and counts the time, and from among a plurality of charging information that varies depending on the time zone, charging information corresponding to the time zone of the timing time is provided. In the watt-hour meter device equipped with the semiconductor integrated circuit that selects and calculates the power usage fee according to the billing information and the power usage amount, even if the clock signal generated in the oscillation circuit varies, it is possible to accurately measure the time. It is an object of the present invention to provide a watt-hour meter device that can generate a clock signal to be performed and can accurately calculate a power charge according to a time zone.

  The real-time clock circuit according to the present invention includes a frequency divider that divides a reference clock signal to generate a window pulse, a first oscillation circuit that generates a first clock signal having a first period, and the first A second oscillation circuit that generates a second clock signal having a second period longer than the first period, and a first clock signal that selects and outputs one of the first and second clock signals. Selection circuit, a first AND circuit that takes a logical product of the clock signal selected by the first selection circuit and the window pulse, the clock signal selected by the first selection circuit, and the first A second selection circuit that selects and outputs one of the outputs of the AND circuit, a first counter that counts the output of the second selection circuit, and a register that stores predetermined data The first A comparator that generates a clock signal for timekeeping by comparing the count data of the counter with the data stored in the register, and a logical product of the clock signal for timekeeping and the second clock signal. 2 and a second counter that counts the output of the second AND circuit, and the register divides the count data of the first counter or the count data by a fixed number. Or the count data of the second counter or the data obtained by dividing the count data by a fixed number is stored.

  The real-time clock circuit of the present invention generates a window pulse by dividing the reference clock signal, counts the clock signal generated by the oscillation circuit during the generation period of the window pulse, and outputs data corresponding to the count number. The clock signal is stored in a register, the clock signal is counted again, and the count data is compared with the data stored in the register by a comparator to generate a clock signal for time measurement.

  The real-time clock circuit of the present invention divides the reference clock signal to generate a window pulse, and a first clock signal having a first period generated by the first oscillation circuit during the generation period of the window pulse. And the data corresponding to the counted number is stored in the register, the first clock signal is counted again, and the comparator compares this count data with the data stored in the register to obtain the first Of the first clock generated by the second oscillation circuit during the generation period of the window pulse using the first clock signal for the clock as a window pulse. A second clock signal having a longer second period is counted, and data corresponding to the counted number is stored again in the register, and The second clock signal again, counted, by the comparator and generates a clock signal of the second time timekeeping compared with the data stored the count data in the register.

  A semiconductor integrated circuit according to the present invention includes a frequency divider that divides a reference clock signal input from an external terminal to generate a window pulse, a central processing unit that generates control data, and the central processing unit A first oscillator for generating a first clock signal having a first period, connected to a bus for transmitting control data generated by the central processing unit, and a crystal resonator via an external terminal A crystal oscillator connected via an external terminal, a second oscillation circuit for generating a second clock signal having a second period longer than the first period, and the bus, A first selection circuit that selects and outputs one of the first and second clock signals according to the control data on the bus, and a clock selected by the first selection circuit Signal and the above A first logical product circuit that performs a logical product with a window pulse, and a clock signal connected to the bus and selected by the first selection circuit according to control data on the bus, and the first logical circuit A second selection circuit that selects and outputs one of the outputs of the product circuit; a first counter that is connected to the bus and counts an output of the second selection circuit; and is connected to the bus; A register for storing data on the bus, a comparator for comparing the count data of the first counter with the data stored in the register and generating a clock signal for time measurement, and generated by the comparator A second logical product circuit that performs a logical product of the clock signal and the second clock signal, and a second counter that is connected to the bus and counts the output of the second logical product circuit. did It has an internal time clock circuit, and the register has the count data of the first counter or the data after the count data is divided by a fixed number by the central processing unit, or the count of the second counter Data or data obtained by dividing the count data by a predetermined number by the central processing unit is stored.

  The watt-hour meter device of the present invention is connected to a commercial AC power source, generates a pulse signal having a frequency corresponding to the amount of power used, and calculates the amount of power used by counting the pulse signal. Built-in real-time clock circuit that generates a clock signal for timekeeping and counts the clock signal to count the time, and responds to the time zone of the time from among multiple billing information that varies depending on the time zone And a semiconductor integrated circuit that calculates a usage power charge according to the charging information and the calculated power consumption. The semiconductor integrated circuit includes a reference clock input from an external terminal. A frequency divider that divides a signal to generate a window pulse, a central processing unit that generates control data, and a central processing unit that is connected to the central processing unit and is generated by the central processing unit A crystal oscillator is connected to the bus for transmitting the control data, a crystal oscillator via an external terminal, and generates a first clock signal having a first period, and the crystal oscillation via the external terminal A second oscillation circuit for generating a second clock signal having a second period longer than the first period, and a child connected to the bus, in accordance with control data on the bus A first selection circuit that selects and outputs one of the first and second clock signals, and a logical product of the clock signal selected by the first selection circuit and the window pulse. A first logical product circuit that is connected to the bus and selected by the first selection circuit in accordance with control data on the bus and an output of the first logical product circuit Select one of them and output Two selection circuits, a first counter connected to the bus and counting the output of the second selection circuit, a register connected to the bus and storing data on the bus, and the first A logical product of a comparator that compares the count data of the counter with the data stored in the register to generate a clock signal for timekeeping, and the clock signal generated by the comparator and the second clock signal And a second counter that is connected to the bus and counts the output of the second AND circuit, and the register includes count data of the first counter. Alternatively, the data after the count data is divided by a fixed number by the central processing unit, or the count data of the second counter or the count data is the intermediate data Data divided by a fixed number by the central processing unit is stored.

  According to the real-time clock circuit of the present invention, it is possible to generate a clock signal for performing accurate timing even if the clock signal generated in the oscillation circuit varies.

  In the semiconductor integrated circuit incorporating the real-time clock circuit of the present invention, a clock signal for accurate time measurement can be generated even if the clock signal generated by the oscillation circuit varies.

  Furthermore, in the watt-hour meter device of the present invention, it is possible to generate a clock signal for accurate time measurement even if the clock signal generated in the oscillation circuit varies, and thus accurately calculate the power rate according to the time zone. can do.

  The present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing only a circuit portion related to a real-time clock circuit extracted from a semiconductor integrated circuit according to the present invention. The external terminal 11 is supplied with a reference clock signal CLKref calibrated in advance from several Hz to several tens Hz from the outside of the semiconductor integrated circuit. A frequency divider 12 is connected to the external terminal 11. The frequency divider 12 divides the reference clock signal CLKref to generate a window pulse Pw1 for a predetermined period. This window pulse Pw1 is supplied to one input terminal of the first AND gate circuit (first AND circuit) 13.

  An oscillation crystal resonator 15 is connected between the pair of external terminals 14a and 14b. A load capacitor 16 is connected between the pair of external terminals 14a and 14b and the ground potential node. Inside the semiconductor integrated circuit, an oscillation inverting circuit 17 and a feedback resistance element 18 are connected in parallel between the pair of external terminals 14a and 14b. The crystal oscillator 15, the load capacitor 16, the inverting circuit 17, and the resistance element 18 constitute a first oscillation circuit 19. In the first oscillation circuit 19, the natural frequency of the crystal unit 15 is selected so that the oscillation frequency becomes several MHz, for example.

  Further, an oscillation crystal resonator 21 is connected between the pair of external terminals 20a and 20b. A load capacitor 22 is connected between the pair of external terminals 20a and 20b and the ground potential node. Inside the semiconductor integrated circuit, an oscillation inverting circuit 23 and a feedback resistance element 24 are connected in parallel between the pair of external terminals 20a and 20b. The crystal oscillator 21, the load capacitor 22, the inverting circuit 23, and the resistance element 24 constitute a second oscillation circuit 25. In the second oscillation circuit 25, the natural frequency of the crystal unit 21 is selected so that the oscillation frequency is, for example, several KHz.

  The operations of the inverting circuits 17 and 23 for oscillation provided in the first and second oscillation circuits 19 and 25 are controlled according to control signals, respectively, and the first and second oscillation circuits 19 are controlled by these control signals. , 25 is selected to enable or disable the oscillation operation. During the oscillation operation, the first oscillation circuit 19 generates a first clock signal CLK1 having a first period, and the second oscillation circuit 25 has a second period having a second period longer than the first period. Generate clock signal CLK2. That is, the second clock signal CLK2 has a frequency lower than that of the first clock signal CLK1, the first oscillation circuit 19 oscillates at high speed, and the second oscillation circuit 25 oscillates at low speed.

  Both the first clock signal CLK 1 and the second clock signal CLK 2 generated by the first and second oscillation circuits 19 and 25 are supplied to the first selection circuit 26. The first selection circuit 26 selects one of the first clock signal CLK1 and the second clock signal CLK2 in accordance with the control data transmitted on the bus 28 connected to the CPU 27. Output. The clock signal selected by the first selection circuit 26 is supplied to the other input terminal of the first AND gate circuit 13.

The clock signal selected by the first selection circuit 26 and the output of the first AND gate circuit 13 are both supplied to the second selection circuit 29. The second selection circuit 29 selects either the clock signal selected by the first selection circuit 26 or the output of the first AND gate circuit 13 in accordance with the control data transmitted on the bus 28. And output. The signal selected by the second selection circuit 29 is supplied to the first counter (counter 1) 30. The first counter 30 counts the signals selected and output from the second selection circuit 29. The count data of the first counter 30 is sent to the CPU 27 via the bus 28. The CPU 27 stores the count data of the first counter 30 as it is or the data obtained by dividing the count data by a fixed number in a non-volatile storage device such as an E ² PROM, and the data is stored in the register via the bus 28. 31 to be stored.

The count data of the first counter 30 and the data stored in the register 31 are compared by a comparator 32 to generate a clock signal CLK3 for timekeeping. The time clock signal CLK3 generated by the comparator 32 is sent to a clock frequency divider (not shown) for time clocking and further divided by the frequency divider 33, and then the second clock signal CLK3. This is supplied to one input terminal of an AND gate circuit (second AND circuit) 34. A second clock signal CLK2 generated by the second oscillation circuit 25 is supplied to the other input terminal of the second AND gate circuit. The output of the second AND gate circuit 34 is supplied to a second counter (counter 2) 35. The second counter 35 counts the output of the second AND gate circuit 34. The count data of the second counter 34 is sent to the CPU 27 via the bus 28. The CPU 27 stores the count data of the second counter 34 as it is or the data obtained by dividing the count data by a fixed number in a non-volatile storage device such as the E ² PROM and the data via the bus 28. To the register 31 for storage.

  Note that the first clock signal CLK1 and the second clock signal CLK2 generated by the first and second oscillation circuits 19 and 25 are used as synchronization signals when the CPU 27 performs a processing operation. The first oscillation circuit 19 that oscillates at a high speed operates when the CPU 27 requires a large processing capacity, and the second oscillation circuit 25 that oscillates at a low speed does not require a large processing capacity. The control signal is controlled so as to operate when the power supplied to the semiconductor integrated circuit is cut off and a backup operation using a battery is performed.

  In the semiconductor integrated circuit having the above configuration, the first and second clock signals CLK1 and CLK2 generated by the first and second oscillation circuits 19 and 25 are used to generate a clock signal CLK3 for timekeeping. Is done. As described above, the crystal unit originally has an individual error, and the oscillation frequency of the oscillation circuit varies depending on the error of the load capacitor and the use environment temperature. Therefore, the clock signal CLK3 for timekeeping generated using the first and second clock signals CLK1 and CLK2 also varies. Therefore, when the semiconductor integrated circuit is shipped from the factory, accuracy measurement and correction of the crystal resonator in the real-time clock circuit shown in FIG. 1 are performed.

  This accuracy measurement and correction is performed as follows. First, the semiconductor integrated circuit is set in an operating state, and an accurate reference clock signal CLKref calibrated in advance of several to several tens Hz is input from the external terminal 11. At this time, the first and second oscillation circuits 19 and 25 are operated. When the reference clock signal CLKref is input, the first selection circuit 26 selects the clock signal CLK 1 generated by the first oscillation circuit 19, and the second selection circuit 29 outputs the output of the first AND gate circuit 13. The first and second selection circuits 26 and 29 are controlled to be switched by the processing of the CPU 27 so as to select. The connection state of the circuit of FIG. 1 at this time is extracted and shown in FIG. By dividing the reference clock signal CLKref input from the external terminal 11 by the frequency divider 12, for example, a window pulse Pw1 having a period of 1 second is generated, and one input terminal of the first AND gate circuit 13 is generated. Is input. On the other hand, the first clock signal CLK 1 generated by the first oscillation circuit 19 is input to the other input terminal of the first AND gate circuit 13 via the first selection circuit 26. Then, during the period when the window pulse Pw1 is established, the first clock signal CLK1 is output from the first AND gate circuit 13 and counted by the first counter 30. As a result, the number of clocks of the first clock signal CLK1 generated in an accurate 1 second period is measured. After this measurement is completed, the reference clock signal CLKref input from the outside can be disconnected, and thereafter the processing by the CPU 27 is performed.

  The count data of the first counter 30 is read into the CPU 27 via the bus 28 by a transfer instruction of the CPU 27, and the count data is left as it is or data obtained by dividing the count data by a certain number is stored in the nonvolatile storage device. In addition to being stored, the data is transferred again to the register 31 via the bus 28 and stored. If the window pulse Pw1 is established for 1 second as described above, the count data of the counter 30 is transferred to the register 31 and stored as it is. However, when the establishment period of the window pulse Pw1 is set to 1 second or more by increasing the frequency division number of the frequency divider 12, the count data of the counter 30 read by the CPU 27 is the CPU 27. Is divided by a fixed number that is the number of seconds corresponding to the establishment period of the window pulse Pw1 and converted into data of a period of 1 second, and the converted data is stored in the nonvolatile memory device. Stored in the register 31.

  Thereafter, the second selection circuit 29 is controlled to be switched by the processing of the CPU 27 so that the second selection circuit 29 selects the output of the first selection circuit 26. The selection operation of the first selection circuit 26 does not change. The connection state of the circuit of FIG. 1 at this time is extracted and shown in FIG. At this time, the register 31 stores data corresponding to the number of clocks of the first clock signal CLK1 generated in an accurate period of 1 second. Then, the first clock signal CLK 1 generated by the first oscillation circuit 19 is counted by the first counter 30, and the count data is compared with the data stored in the register 31 by the comparator 32. As a result, the comparator 32 generates the clock signal CLK3 having a 1-second period with less error. By dividing the clock signal CLK3, a highly accurate timepiece can be realized.

  In this way, a window pulse Pw1 in units of seconds (for example, 1 second) is generated using an accurate reference clock signal CLKref input from the outside, and a high oscillation frequency (MHz or higher) during the period in which the window pulse Pw1 is established. When the count number of the first clock signal CLK1 having () is measured by the counter 30, the number of clocks necessary for counting one second can be obtained using the first clock signal CLK1. Since the minimum measurement unit at this time is one clock of the counter 30, a resolution error corresponding to a half clock of the first clock signal CLK1 occurs at the time of measurement. Further, when the window pulse Pw1 rises and falls, a measurement error corresponding to one clock and a total of two clocks occurs. However, this increases the frequency division number of the frequency divider 12 that divides the accurate reference clock signal CLKref inputted from the outside, and elongates the establishment period of the window pulse Pw1, such as 16 seconds, If the measurement time by the counter 30 is lengthened, the ratio of the measurement error to the total error can be reduced.

  The total error is expressed as the sum of the resolution error based on the resolution of the counter 30 and the measurement error. When the frequency of the first clock signal CLK1 is f1 (Hz) and the measurement time is t1 (s), the resolution is The error is (1 / f1 × 2), the measurement error is (2 / f1 × t1), and the total error is (1 / f1 × 2) + (2 / f1 × t1) (ppm). If the actual oscillation frequency is 10,00010 Hz when the first oscillation circuit 19 is operated at 1 MHz, the first clock signal CLK1 without correction has an error of 10 ppm. On the other hand, when the measurement time in the counter 30 is 16 seconds, the error of the clock CLK3 generated by the comparator 32 is reduced to 0.625 ppm.

  Next, the clock CLK3 generated by the comparator 32 is divided by the frequency divider 33, thereby generating a window pulse Pw2 having a period of 1 second, for example, and one input of the second AND gate circuit 34. Input to the terminal. On the other hand, the second clock signal CLK 2 generated by the second oscillation circuit 25 is input to the other input terminal of the second AND gate circuit 34. The connection state of the circuit of FIG. 1 at this time is extracted and shown in FIG. During the period in which the window pulse Pw2 is established, the second clock signal CLK2 is output from the second AND gate circuit 34 and counted by the second counter 35. As a result, the number of clocks of the second clock signal CLK2 generated in an accurate 1 second period is measured.

  The count data of the second counter 35 is read into the CPU 27 via the bus 28 by a transfer instruction of the CPU 27, and the count data is left as it is or data obtained by dividing the count data by a certain number is stored in the nonvolatile storage device. In addition to being stored, the data is transferred again to the register 31 via the bus 28 and stored. When the window pulse Pw2 is established for 1 second as described above, the count data of the counter 35 is stored in the register 31 as it is. However, when the window pulse Pw2 is established for 1 second or more by increasing the frequency division number of the frequency divider 33, the count data of the counter 35 read to the CPU 27 is the operation instruction of the CPU 27. Thus, the data is divided by a fixed number, which is the number of seconds corresponding to the establishment period of the window pulse Pw2, and converted into data of a period of 1 second, and the converted data is stored in the register 31.

  Thereafter, the first selection circuit 26 is controlled to be switched by the processing of the CPU 27 so that the first selection circuit 26 selects the clock signal CLK2 generated by the first oscillation circuit 25. The selection operation of the second selection circuit 29 does not change. The connection state of the circuit of FIG. 1 at this time is extracted and shown in FIG. At this time, the register 31 stores data corresponding to the number of clocks of the second clock signal CLK2 generated in an accurate period of 1 second. Then, the second clock signal CLK2 generated by the second oscillation circuit 25 is counted by the first counter 30, and the counted data is compared with the data stored in the register 31 by the comparator 32. The comparator 32 generates a clock signal CLK3 having a 1-second period with little error. By dividing the clock signal CLK3, a highly accurate timepiece can be realized.

  By the way, when a semiconductor integrated circuit having a built-in real-time clock circuit as shown in FIG. 1 is incorporated in an actual product to perform a timing operation, when a power supply voltage is stably supplied, as shown in FIG. The first oscillation circuit 19 operates, and the first clock signal CLK1 generated by the first oscillation circuit 19 is sent to the first counter 30 via the first selection circuit 26 and the second selection circuit 29. Then, the first counter 30 counts the first clock signal CLK1. Then, the count data of the first counter 30 is compared with the data stored in the register 31. At this time, in the register 31, the first clock signal CLK1 is counted by the counter 30 during the period in which the window pulse Pw1 in seconds generated using the accurate reference clock signal CLKref input from the outside is established. The data after being stored is stored. During this period, the operation of the second oscillation circuit 25 is stopped by the control signal.

  Therefore, when the power supply voltage is stably supplied, the first clock signal CLK1 generated by the first oscillation circuit 19 that oscillates at high speed is used to generate the clock signal CLK3 having a 1-second error-free period. Generated.

  On the other hand, when the power supply voltage supplied to the semiconductor integrated circuit is cut off and a backup operation by a battery is performed, the second oscillation circuit 25 operates as shown in FIG. The generated second clock signal CLK2 is supplied to the first counter 30 via the first selection circuit 26 and the second selection circuit 29, and the second clock signal CLK2 is counted by the first counter 30. The Then, the count data of the first counter 30 is compared with the data stored in the register 31. At this time, as shown in FIG. 4, the register 31 receives the second clock signal CLK2 from the second counter 35 during the period in which the window pulse Pw2 in seconds generated using the clock signal CLK3 is established. Stores the data after being counted in. During this period, the operation of the first oscillation circuit 19 is stopped by the control signal.

  Therefore, when the backup operation by the battery is performed, the second clock signal CLK2 generated by the second oscillation circuit 25 that oscillates at a low speed is used to generate the clock signal CLK3 having a cycle with a small error of 1 second. The

  Further, after the power supply voltage is restored, as shown in FIG. 3, the first oscillation circuit 19 operates, and the first clock signal CLK1 generated by the first oscillation circuit 19 is changed to the first selection circuit 26. The clock signal CLK3 is supplied to the first counter 30 via the second selection circuit 29 and the count data is compared with the data stored in the register 31 to generate a clock signal CLK3 having a one-second period with little error. Is done. At this time, in the register 31, the first clock signal CLK1 is counted by the counter 30 during the period in which the window pulse Pw1 in seconds generated using the accurate reference clock signal CLKref input from the outside is established. The data after being stored is stored.

  As described above, according to the semiconductor integrated circuit of the above-described embodiment, the accurate reference clock signal CLKref calibrated in advance is input from the external terminal 11 at the time of factory shipment, and the accuracy of the crystal resonator in the real-time clock circuit is obtained. By performing measurement and correction, the clock signal CLK3 having a 1-second period with less error can be generated by operating the internal oscillation circuit after incorporation into an actual product. Moreover, even when the power supply voltage is stably supplied or when the power supply voltage is cut off and the battery backup operation is performed, the clock signal CLK3 having a 1-second cycle with less error can be generated. Of course, even after the power supply voltage is restored after the power supply voltage is cut off, the clock signal CLK3 having a one-second period with less error can be generated without inputting the reference clock signal CLKref from the outside.

  FIG. 6 is a block diagram showing an application example of a semiconductor integrated circuit incorporating a real-time clock circuit according to the present invention. In this application example, the semiconductor integrated circuit shown in FIG. 1 is applied to a watt-hour meter device that automatically calculates a power charge based on the amount of power used by a commercial AC power supply with a different midnight power charge and daytime power charge. It is.

  In FIG. 6, reference numeral 50 denotes a semiconductor integrated circuit incorporating a real-time clock circuit having the configuration shown in FIG. In this semiconductor integrated circuit 50, the external terminals CIN1 and COUT1 correspond to the external terminals 14a and 14b in FIG. 1, and both the external terminals CIN1 and COUT1 have the crystal oscillator 15 and the load constituting the first oscillation circuit 19 described above. A capacitor 16 is connected. Similarly, the external terminals CIN2 and COUT2 correspond to the external terminals 20a and 20b in FIG. 1, and the crystal oscillator 21 and the load capacitance capacitor 22 constituting the second oscillation circuit 25 are connected to both the external terminals CIN2 and COUT2. Connected.

  In the semiconductor integrated circuit 50, as shown in FIG. 1, the first counter 30 generates the first and second clock signals CLK1 and CLK2 generated by the first and second oscillation circuits 19 and 25, respectively. The clock signal CLK3 having a period of 1 second generated by counting and comparing with the data stored in the register 31 in the comparator 32 is divided to measure the time consisting of seconds, minutes, and hours. It has a timekeeping function.

  In FIG. 6, reference numeral 60 denotes a power amount measuring unit that measures the amount of power used by a 200V or 100V commercial AC power supply. This electric energy measuring unit 60 has, for example, a ΔΣ AD conversion semiconductor integrated circuit (ΔΣ AD conversion IC), measures an AC pulse (voltage / current) of a commercial AC power supply, and converts it into a digital pulse signal of several Hz to several KHz. And output. The frequency of the converted pulse signal is proportional to the amount of power used. In other words, the higher the frequency, the more power is used. This pulse signal is supplied as a drive pulse to a step motor of a mechanical display 71 provided in the used electric energy display unit 70, whereby the used accumulated electric energy is displayed numerically. The power consumption display unit 70 has a front panel 72 made of, for example, a liquid crystal display (LCD) in addition to the mechanical display 71 described above. The front panel 72 performs display based on various display information output from the semiconductor integrated circuit 50.

  The digital pulse signal output from the power amount measuring unit 60 is supplied to an external terminal (I / O) for power measurement input of the semiconductor integrated circuit 50 through a photo coupler 61.

  A power supply circuit (Regulator) 80 generates a DC voltage from a commercial AC power supply. The DC voltage generated by the power supply circuit 80 is supplied to the power supply voltage supply external terminal (VDD) of the semiconductor integrated circuit 50 through the diode 81 and the power supply voltage detection external terminal of the semiconductor integrated circuit 50. (I / O). Further, a backup battery 82 at the time of power-off is connected to an external terminal (VDD) for supplying power supply voltage of the semiconductor integrated circuit 50 via a diode 83.

  In the semiconductor integrated circuit 50, when the DC voltage is generated in the power supply circuit 80, this is detected, and the first clock signal CLK1 generated in the first oscillation circuit 19 (shown in FIG. 1) is the counter 30. A pulse signal CLK3 having a period of 1 second is generated by counting with a comparator 32 (illustrated in FIG. 1) and comparing with a comparator 32 (illustrated in FIG. 1), and further dividing the pulse signal CLK3. The time is counted at.

On the other hand, in the semiconductor integrated circuit 50, the power consumption is measured by counting the digital pulse signal supplied to the external terminal (I / O) for power measurement input, and the measured power consumption and time Billing information corresponding to the time zone of the clocking time is selected from a plurality of billing information that differs depending on the band, and the power consumption fee is calculated according to the billing information and the calculated power consumption. The calculated power charge is stored in a non-volatile storage device, for example, E ² PROM 90, as billing information. The CPU 27 in FIG. 1 may store the count data of the first counter 30 or data obtained by dividing the count data by a certain number in the E ² PROM 90.

The semiconductor integrated circuit 50 is provided with an external terminal (UART / SIO) mainly for connecting an infrared LED (light emitting diode) and an infrared light receiving element. Then, information is exchanged by light with the external terminal for meter reading through the infrared LED and infrared light receiving element connected to the external terminal, and the monthly billing information stored in the E ² PROM 90 Is supplied to the external terminal for meter reading, and information for changing the unit price and changing the function is supplied to the semiconductor integrated circuit 50. When the unit price is changed and the function is changed, display information is generated by the semiconductor integrated circuit 50 based on the input information, and the display information is supplied to the front panel 72, so that the information when the unit price is changed and the function is changed. May be displayed on the front panel 72.

  On the other hand, when the AC power supply is cut off and no DC voltage is generated in the power supply circuit 80 and is detected in this state by the semiconductor integrated circuit 50, the second oscillation circuit 25 is replaced with the first oscillation circuit 19 described above. The second clock signal CLK2 generated by the second oscillation circuit 25 is counted by the counter 30 and is compared by the comparator 32 to generate a pulse signal CLK3 having a period of 1 second. Further, the time is counted by dividing the pulse signal CLK3. That is, in the semiconductor integrated circuit 50 having a built-in real-time clock circuit as shown in FIG. 1, the current time can always be measured stably, so that the time can be measured almost accurately even after the AC power is shut off. After that, even if the AC power supply is restored, the power rate can be accurately calculated based on the price per unit power amount according to the time zone.

  Needless to say, the present invention is not limited to the above-described embodiment, and various modifications are possible. For example, in the semiconductor integrated circuit shown in FIG. 1, the case where the clock signal CLK3 generated by the comparator 32 is counted by the frequency divider 33 to generate the window pulse Pw2 having a period of 1 second has been described. When the clock signal CLK3 itself is a clock signal having a period of 1 second, the frequency divider 33 may be omitted and the clock signal CLK3 itself may be supplied to the second AND gate circuit 34 as the window pulse Pw2. .

FIG. 3 is a circuit diagram showing only a circuit portion related to a real-time clock circuit extracted from the semiconductor integrated circuit according to the present invention. The circuit diagram which extracts and shows the circuit connection state when operating the circuit of FIG. The circuit diagram which extracts and shows the circuit connection state when operating the circuit of FIG. The circuit diagram which extracts and shows the circuit connection state when operating the circuit of FIG. The circuit diagram which extracts and shows the circuit connection state when operating the circuit of FIG. 1 is a block diagram showing an application example of a semiconductor integrated circuit incorporating a real-time clock circuit according to the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11, 14a, 14b, 20a, 20b ... External terminal, 12 ... Frequency divider, 13 ... 1st AND gate circuit, 15, 21 ... Crystal oscillator, 19 ... 1st oscillation circuit, 25 ... 2nd oscillation Circuit, 26 ... first selection circuit, 27 ... CPU, 28 ... bus, 29 ... second selection circuit, 30 ... first counter, 31 ... register, 32 ... comparator, 33 ... frequency divider, 34 ... 2nd AND gate circuit, 35 ... second counter, 50 ... semiconductor integrated circuit, 60 ... electric energy measuring unit, 61 ... photocoupler, 70 ... used electric energy display unit, 71 ... display, 72 ... front panel, 80 ... Power supply circuit, 81 ... Diode, 82 ... Battery for backup, 83 ... Diode, 90 ... E ² PROM.

Claims (5)

A frequency divider that divides the reference clock signal to generate a window pulse;
A first oscillation circuit for generating a first clock signal having a first period;
A second oscillation circuit for generating a second clock signal having a second period longer than the first period;
A first selection circuit that selects and outputs one of the first and second clock signals;
A first AND circuit that takes a logical product of the clock signal selected by the first selection circuit and the window pulse;
A second selection circuit that selects and outputs either the clock signal selected by the first selection circuit or the output of the first AND circuit;
A first counter that counts the output of the second selection circuit;
A register for storing predetermined data; and
A comparator that compares the count data of the first counter with the data stored in the register to generate a clock signal for timekeeping;
A second AND circuit that takes a logical product of the clock signal for timekeeping and the second clock signal;
A second counter that counts the output of the second AND circuit;
The register stores the count data of the first counter or data obtained by dividing the count data by a certain number, or the count data of the second counter or data obtained by dividing the count data by a certain number. A real-time clock circuit. The reference clock signal is divided to generate a window pulse, and the clock signal generated by the oscillation circuit is counted during the generation period of the window pulse, and data corresponding to the count number is stored in the register.
A real-time clock circuit which counts the clock signal again and compares the count data with data stored in the register by a comparator to generate a clock signal for time measurement. The reference clock signal is divided to generate a window pulse. During the window pulse generation period, the first clock signal having the first period generated by the first oscillation circuit is counted to obtain the count number. The corresponding data is stored in the register,
The first clock signal is counted again, and the count data is compared with the data stored in the register by a comparator to generate a clock signal for the first clock.
The second clock having the second period longer than the first period generated by the second oscillation circuit is generated in the generation period of the window pulse by using the first clock signal for timekeeping as the window pulse. The clock signal is counted and the data corresponding to the count number is stored again in the register,
The second clock signal is counted again, and the count data is compared with the data stored in the register by the comparator to generate a second clock signal for time measurement. Clock circuit. A frequency divider that divides a reference clock signal input from an external terminal to generate a window pulse;
A central processing unit for generating control data;
A bus connected to the central processing unit for transmitting control data generated by the central processing unit;
A first oscillation circuit that is connected to a crystal resonator via an external terminal and generates a first clock signal having a first period;
A second oscillation circuit that is connected to a crystal resonator via an external terminal and generates a second clock signal having a second period longer than the first period;
A first selection circuit that is connected to the bus and selects and outputs one of the first and second clock signals according to the control data on the bus;
A first AND circuit that takes a logical product of the clock signal selected by the first selection circuit and the window pulse;
A first signal that is connected to the bus and that selects and outputs either the clock signal selected by the first selection circuit or the output of the first AND circuit according to the control data on the bus; Two selection circuits;
A first counter connected to the bus and counting an output of the second selection circuit;
A register connected to the bus for storing data on the bus;
A comparator that compares the count data of the first counter with the data stored in the register to generate a clock signal for timekeeping;
A second AND circuit that takes a logical product of the clock signal generated by the comparator and the second clock signal;
A real-time clock circuit that is connected to the bus and includes a second counter that counts the output of the second AND circuit;
In the register, the count data of the first counter or the data after the count data is divided by a fixed number by the central processing unit, or the count data of the second counter or the count data is the central data A semiconductor integrated circuit in which data divided by a predetermined number by an arithmetic processing unit is stored. An electric energy measuring unit that is connected to a commercial AC power source and generates a pulse signal having a frequency according to the used electric energy;
The power consumption is calculated by counting the pulse signal, and a clock signal for timekeeping is generated, and a real-time clock circuit that counts the clock signal and counts the time is built in, and varies depending on the time zone A semiconductor integrated circuit that selects billing information according to the time zone of the clocking time from a plurality of billing information, and calculates a power consumption fee according to the billing information and the calculated power consumption amount,
The semiconductor integrated circuit is:
A frequency divider that divides a reference clock signal input from an external terminal to generate a window pulse;
A central processing unit for generating control data;
A bus connected to the central processing unit for transmitting control data generated by the central processing unit;
A first oscillation circuit that is connected to a crystal resonator via an external terminal and generates a first clock signal having a first period;
A second oscillation circuit that is connected to a crystal resonator via an external terminal and generates a second clock signal having a second period longer than the first period;
A first selection circuit that is connected to the bus and selects and outputs one of the first and second clock signals according to the control data on the bus;
A first AND circuit that takes a logical product of the clock signal selected by the first selection circuit and the window pulse;
A first signal that is connected to the bus and that selects and outputs either the clock signal selected by the first selection circuit or the output of the first AND circuit according to the control data on the bus; Two selection circuits;
A first counter connected to the bus and counting an output of the second selection circuit;
A register connected to the bus for storing data on the bus;
A comparator that compares the count data of the first counter with the data stored in the register to generate a clock signal for timekeeping;
A second AND circuit that takes a logical product of the clock signal generated by the comparator and the second clock signal;
A second counter connected to the bus and counting the output of the second AND circuit;
In the register, the count data of the first counter or the data after the count data is divided by a fixed number by the central processing unit, or the count data of the second counter or the count data is the central data A watt-hour meter device storing data divided by a fixed number by an arithmetic processing unit.

Images