JP7392576B2 - Real-time clock circuit, real-time clock module, electronic equipment and real-time clock circuit correction method - Google Patents

Description

The present invention relates to a real-time clock circuit, a real-time clock module, an electronic device, and a correction method for a real-time clock circuit.

Patent Document 1 discloses that the total amount of adjustment required for the time reference signal can be reduced within one adjustment period by employing a distributed adjustment method in which a plurality of adjustment operations with short adjustment amounts are performed in a distributed manner within one adjustment period. A logical adjustment circuit has been disclosed that can minimize the amount of expansion and contraction of the time reference signal in the adjustment timing while ensuring that the interference between the adjustment timing and the required output timing can be ignored.

Japanese Patent Application Publication No. 06-027265

However, Patent Document 1 does not disclose how to generate correction data for setting the adjustment amount. For example, there are methods that output a 32kHz source oscillation signal or its frequency-divided signal to an external device, measure the frequency of the signal with the external device, and generate correction data based on the measurement results, and A possible method is to generate correction data by comparing the cumulative delay of time measurement data with an accurate reference time in units of . However, in the former case, a configuration for measuring the frequency is required in the external device. Moreover, in the latter case, long-term measurement is required to improve the correction accuracy.

One aspect of the real-time clock circuit according to the present invention is
an oscillation circuit that generates a first clock signal by oscillating a vibrator;
a first frequency dividing circuit that divides the first clock signal to generate a second clock signal;
a second frequency dividing circuit that frequency divides the second clock signal to generate a third clock signal, and generates first time measurement data for a time shorter than one second based on the second clock signal;
a timekeeping circuit that generates second timekeeping data for a time of one second or more based on the third clock signal;
Using correction data generated based on the amount of change in the first time measurement data at intervals synchronized with the reference signal, the first frequency dividing circuit is subjected to slow and fast processing during a period of length corresponding to the intervals. and a logic circuit that performs.

One aspect of the real-time clock module according to the present invention is
One aspect of the real-time clock circuit,
and the vibrator.

One aspect of the electronic device according to the present invention is
One aspect of the real-time clock circuit,
a host device communicating with the real-time clock circuit.

One aspect of the real-time clock circuit correction method according to the present invention is as follows:
an oscillation circuit that oscillates a vibrator to generate a first clock signal; a first frequency divider circuit that divides the frequency of the first clock signal to generate a second clock signal; and a first frequency divider circuit that divides the frequency of the second clock signal. a second frequency dividing circuit that generates a third clock signal based on the second clock signal, and generates first time measurement data for a time shorter than one second based on the third clock signal; A method for correcting a real-time clock circuit, comprising: a clock circuit that generates second clock data for a time of
The real-time clock circuit performs the first frequency division in a period corresponding to the interval using correction data generated based on the amount of change in the first clock data at intervals synchronized with the reference signal. It includes a step of performing slow and fast processing on the circuit.

FIG. 2 is a functional block diagram of a real-time clock module according to the first embodiment. The figure which shows the example of a structure of a timekeeping circuit. The figure which shows the example of a structure of a 1st frequency division circuit. The figure which shows the example of a structure of the 2nd frequency division circuit when selection data SEL is 0. FIG. 7 is a diagram illustrating a configuration example of a second frequency dividing circuit when selection data SEL is 1; The figure which shows an example of the relationship between the correction period and the timing of gradual and rapid processing when selection data SEL is 0. The figure which shows an example of the relationship between the correction period and the timing of gradual and rapid processing when selection data SEL is 1. FIG. 7 is a timing chart diagram when control signals PE and PD are both at low level at the timing of slow/fast processing. FIG. 7 is a timing chart diagram when the control signal PE is at a high level and the control signal PD is at a low level at the timing of slow/fast processing. FIG. 7 is a timing chart diagram when the control signal PE is at a low level and the control signal PD is at a high level at the timing of slow/fast processing. FIG. 3 is a diagram illustrating an example of a procedure of a method for correcting a real-time clock circuit according to the first embodiment. FIG. 3 is a functional block diagram of a real-time clock module according to a second embodiment. FIG. 7 is a diagram illustrating an example of a procedure of a correction method for a real-time clock circuit according to a second embodiment. FIG. 7 is a diagram illustrating an example of a procedure of a correction method for a real-time clock circuit according to a third embodiment. FIG. 2 is a functional block diagram of an embodiment of an electronic device. FIG. 1 is a diagram illustrating an example of the appearance of an embodiment of an electronic device.

Hereinafter, preferred embodiments of the present invention will be described in detail using the drawings. Note that the embodiments described below do not unduly limit the content of the present invention described in the claims. Furthermore, not all of the configurations described below are essential components of the present invention.

1. Real-time clock circuit, real-time clock module 1-1. First embodiment 1-1-1. Configuration of Real-Time Clock Module FIG. 1 is a functional block diagram of a real-time clock module 1 according to the first embodiment. As shown in FIG. 1, the real-time clock module 1 includes a vibrator 2 and a real-time clock circuit 3.

The real-time clock module 1 is supplied with a power supply voltage VDD, which is a first power supply voltage, from a main power supply 4 through a terminal P1 of the real-time clock circuit 3, and a second power supply voltage VDD, which is a first power supply voltage, is supplied from a backup power supply 5 through a terminal P2 of the real-time clock circuit 3. A power supply voltage VBAT, which is a power supply voltage of , is supplied.

The vibrator 2 may be a tuning fork type crystal vibrator, an AT-cut crystal vibrator, an SC-cut crystal vibrator, or a SAW (Surface Acoustic Wave) resonator or a piezoelectric vibrator other than a crystal vibrator. Good too. Further, the vibrator 2 may be a MEMS (Micro Electro Mechanical Systems) vibrator made of silicon semiconductor. The vibrator 2 may be excited by piezoelectric effect or may be driven by Coulomb force (electrostatic force).

The real-time clock circuit 3 includes an oscillation circuit 10, a first frequency dividing circuit 20, a second frequency dividing circuit 30, a clock circuit 40, a logic circuit 50, a write buffer 60, a read buffer 70, an event time register 80, an interface circuit 90, and a memory. 100, an interrupt generation circuit 110, a power supply voltage selection circuit 120, a power supply voltage determination circuit 130, and a regulator 140. However, the real-time clock circuit 3 may have a configuration in which some of these elements are omitted or changed, or other elements are added. In the present embodiment, the real-time clock circuit 3 is a one-chip integrated circuit (IC), but it may be configured with a plurality of integrated circuit chips, or at least a portion may be configured with discrete components. good.

The power supply voltage determination circuit 130 monitors the power supply voltage VDD, determines whether the power supply voltage VDD is equal to or higher than a predetermined voltage value VT, and outputs a determination signal VDET. In this embodiment, the power supply voltage determination circuit 130 outputs a high-level determination signal VDET when determining that the power supply voltage VDD is equal to or higher than the voltage value VT, and determines that the power supply voltage VDD is less than the voltage value VT. If so, a low level determination signal VDET is output.

Power supply voltage selection circuit 120 selects power supply voltage VDD or power supply voltage VBAT based on determination signal VDET and outputs it as power supply voltage VOUT. Specifically, when the determination signal VDET is at a high level, that is, when the power supply voltage determination circuit 130 determines that the power supply voltage VDD is equal to or higher than the voltage value VT, the power supply voltage selection circuit 120 selects the power supply voltage VDD. Select. Further, the power supply voltage selection circuit 120 selects the power supply voltage VBAT when the determination signal VDET is at a low level, that is, when the power supply voltage determination circuit 130 determines that the power supply voltage VDD is less than the voltage value VT. .

Therefore, when the power supply voltage VDD is supplied from the main power supply 4 to the real-time clock module 1, the power supply voltage VOUT is the power supply voltage VDD and has a predetermined voltage value higher than VT. When the supply of power supply voltage VDD from main power supply 4 to real-time clock module 1 is cut off, power supply voltage VOUT immediately switches to power supply voltage VBAT and becomes a predetermined voltage value below VT. Therefore, the real-time clock module 1 can continue the timekeeping operation even while the supply of the power supply voltage VDD from the main power supply 4 is cut off. On the other hand, the host device 6 that controls the operation of the real-time clock module 1 operates when the power supply voltage VDD is supplied from the main power supply 4, and does not operate when the supply of the power supply voltage VDD from the main power supply 4 is cut off. Stop.

The regulator 140 generates a stabilized power supply voltage VOSC and a power supply voltage VLOGIC having a constant voltage value based on the power supply voltage VOUT.

Power supply voltage VOSC is supplied to the oscillation circuit 10. Further, the power supply voltage VLOGIC includes a first frequency dividing circuit 20, a second frequency dividing circuit 30, a clock circuit 40, a logic circuit 50, a write buffer 60, a read buffer 70, an event time register 80, an interface circuit 90, a storage section 100, The signal is supplied to the interrupt generation circuit 110.

The oscillation circuit 10 causes the vibrator 2 to oscillate and generates the first clock signal CK1. Specifically, the oscillation circuit 10 is electrically connected to both ends of the vibrator 2 via terminals P3 and P4 of the real-time clock circuit 3, and amplifies the output signal of the vibrator 2 and feeds it back. The vibrator 2 is caused to oscillate and a first clock signal CK1 is output. In this embodiment, two types of vibrators 2 having different resonance frequencies can be selected, and the frequency of the first clock signal CK1 is one of two different frequencies, for example, 32.768 kHz and 32 kHz. In order to make the first clock signal CK1 an accurate frequency, the oscillation circuit 10 is preferably an oscillation circuit equipped with a temperature compensation function and a frequency control function.

The first frequency dividing circuit 20 divides the first clock signal CK1 to generate a second clock signal CK2 having a desired frequency. In this embodiment, the frequency division ratio of the first frequency dividing circuit 20 is fixed. For example, when the frequency of the first clock signal CK1 is 32.768 kHz or 32 kHz and the frequency division ratio of the first frequency dividing circuit 20 is 32, the frequency of the second clock signal CK2 is 1.024 kHz or 1 kHz. Note that details of the first frequency dividing circuit 20 will be described later.

The second frequency dividing circuit 30 divides the second clock signal CK2 to generate a third clock signal CK3 having a desired frequency. In this embodiment, the second frequency dividing circuit 30 operates as a binary counter or a BCD (Binary Coded Decimal) counter depending on the value of the selection data SEL, and in either case, the frequency of the third clock signal CK3 generated is is 1Hz. Specifically, if the selection data SEL is 0, the second frequency dividing circuit 30 operates as a binary counter, and divides the second clock signal CK2 by the first frequency division ratio to generate the third clock signal of 1Hz. Generate CK3. For example, if the frequency of the second clock signal CK2 is 1.024 kHz, the first frequency division ratio is 1024. Further, if the selection data SEL is 1, the second frequency dividing circuit 30 operates as a BCD counter, and divides the second clock signal CK2 by a second frequency division ratio to generate a third clock signal CK3 of 1 Hz. do. For example, if the frequency of the second clock signal CK2 is 1 kHz, the second frequency division ratio is 1000.

Further, the second frequency dividing circuit 30 generates time measurement data SUB_T for a time shorter than one second based on the second clock signal CK2. For example, if the frequency of the second clock signal CK2 is 1.024kHz, the clock data SUB_T is clock data in units of 1/1024 seconds, and if the frequency of the second clock signal CK2 is 1kHz, it is clock data in units of 1/1000 seconds. This is timing data.

Further, the second frequency dividing circuit 30 outputs the fourth clock signal CK4 to the logic circuit 50. In this embodiment, the second frequency dividing circuit 30 outputs the fourth clock signal CK4 of 8 Hz when the selection data SEL is 0 and operates as a binary counter, and outputs the fourth clock signal CK4 of 8 Hz when the selection data SEL is 1 and operates as a BCD counter. When operating, the fourth clock signal CK4 of 10 Hz is output. Note that details of the second frequency dividing circuit 30 will be described later.

The clock circuit 40 generates clock data BCD_T and BIN_T for a time of one second or more based on the third clock signal CK3. The clock data BCD_T includes BCD values of year, month, day, hour, minute, and second, and the clock data BIN_T is a binary value. Note that details of the clock circuit 40 will be described later.

The logic circuit 50 uses the correction data TD to perform speed-up and speed processing on the first frequency dividing circuit 20 during a correction period that is a period corresponding to an interval synchronized with the reference signal REF. In this embodiment, the reference signal REF is a signal generated by the host device 6 and input from the terminal P5 of the real-time clock circuit 3. The reference signal REF is a signal having exactly a predetermined frequency. For example, the host device 6 has a GPS receiver (not shown), and the reference signal REF
may be a signal output from the GPS receiver, or may be a signal generated based on the signal output from the GPS receiver. The correction data TD is data generated based on the amount of change in the clock data SUB_T at intervals synchronized with the reference signal REF. In this embodiment, the correction data TD is stored in the storage unit 100. Further, the interval synchronized with the reference signal REF has a length that is an integral multiple of one period of the reference signal REF. Therefore, using the correction data TD, the logic circuit 50 performs a speed-up process on the first frequency dividing circuit 20 during a correction period having a length that is an integral multiple of one period of the reference signal REF. Specifically, the logic circuit 50 generates a control signal PE for increasing the frequency of the second clock signal CK2 during the correction period or a control signal PD for decreasing the frequency of the second clock signal CK2 during the correction period. . For example, the logic circuit 50 may perform delta-sigma modulation on the correction data TD to generate the control signals PE and PD. The first frequency dividing circuit 20 generates a second clock signal CK2 whose average frequency during the correction period is a predetermined frequency according to the control signals PE and PD.

In this embodiment, the correction period setting data PN is input to the logic circuit 50, and the logic circuit 50 uses the correction period setting data PN and the fourth clock signal CK4 output from the second frequency dividing circuit 30 as described above. The interval synchronized with the reference signal REF is determined. Specifically, when the value of the correction period setting data PN is n, the frequency of the fourth clock signal CK4 is f, and the predetermined value is m, the interval is n×m/f seconds. . For example, if n is 32, the frequency of the fourth clock signal CK4 is 8 Hz, and m is 8, the interval is 32×8/8=32 seconds. At this time, for example, the frequency of the reference signal REF is 1 Hz, and the interval is 32 times as long as one period of the reference signal REF. Further, when n is 256, the frequency of the fourth clock signal CK4 is 10 Hz, and m is 8, the interval is 32×8/10=25.6 seconds. At this time, for example, the frequency of the reference signal REF is 1.25 Hz, and the interval is 32 times as long as one cycle of the reference signal REF. In this way, the correction period setting data PN is information specifying an interval synchronized with the reference signal REF described above.

In addition, in the present embodiment, the logic circuit 50 performs slowing/fastening processing on the first frequency dividing circuit 20 at the cycle of the fourth clock signal CK4 during the correction period. For example, when the frequency of the second clock signal CK2 is 1.024 kHz, the frequency of the fourth clock signal CK4 is 8 Hz, so the logic circuit 50 performs the speed-up process at intervals of 0.125 seconds. Furthermore, when the frequency of the second clock signal CK2 is 1 kHz, the frequency of the fourth clock signal CK4 is 10 Hz, so the logic circuit 50 performs the speed-up process at intervals of 0.1 seconds.

The write buffer 60 acquires and holds write data WDAT output from the interface circuit 90 in response to a write request signal (not shown) from the interface circuit 90. A part of the write data WDAT held by the write buffer 60 is output to the second frequency dividing circuit 30 as write data SUB_WD, and another part of the write data WDAT is output to the clock circuit 40 as write data BCD_WD, BIN_WD. Ru.

The read buffer 70 acquires at least one of the clock data SUB_T generated by the second frequency dividing circuit 30 and the clock data BCD_T and BIN_T generated by the clock circuit 40 in response to a read request signal (not shown) from the interface circuit 90. and outputs the held time measurement data to the interface circuit 90 as read data RDAT.

The event time register 80 stores the clock data SUB_T generated by the second frequency dividing circuit 30 and the clock data SUB_T generated by the clock circuit 40 at a predetermined timing when the voltage level of the reference signal REF inputted from the terminal P5 of the real-time clock circuit 3 changes. This is a buffer circuit that holds time measurement data BCD_T and BIN_T. For example, the predetermined timing at which the voltage level of the reference signal REF transitions may be the timing at which the reference signal REF transitions from a low level to a high level, or the timing at which the reference signal REF transitions from a high level to a low level. There may be. The event time register 80 has a size capable of holding a predetermined number of time measurement data, and outputs the held predetermined number of time measurement data to the interface circuit 90 as time data TSTMP. Hereinafter, the function by which the event time register 80 acquires and holds time measurement data SUB_T, BCD_T, and BIN_T based on the reference signal REF will be referred to as a "time stamp function."

The interface circuit 90 is an interface circuit for communication between the real-time clock module 1 and the host device 6. In this embodiment, the interface circuit 90 is an interface circuit compatible with an I ² C (Inter-Integrated Circuit) bus, and receives a serial clock signal SCL input via a terminal P6 of the real-time clock circuit 3 and The host device 6 communicates with the host device 6 based on the serial data signal SDA input/output via the terminal P7. However, the interface circuit 90 may be an interface circuit compatible with other serial buses such as SPI (Serial Peripheral Interface), or may be an interface circuit compatible with parallel buses.

The interface circuit 90 receives an access signal from the host device 6 via terminals P6 and P7, and performs various processes according to the received access signal.

Specifically, when the interface circuit 90 receives an access signal requesting rewriting of at least one of the clock data SUB_T, BCD_T, and BIN_T, the interface circuit 90 sends a write request signal (not shown) requesting writing of the clock data to be rewritten. Occur. The interface circuit 90 then outputs the write request signal and write data WDAT to the write buffer 60. After that, if the time measurement data SUB_T is to be rewritten, the interface circuit 90 outputs the write clock signal SUB_WCK to the second frequency dividing circuit 30, and the second frequency dividing circuit 30 performs time measurement according to the write clock signal SUB_WCK. Data SUB_T is updated to write data SUB_WD, which is part of write data WDAT. Further, when the clock data BCD_T is to be rewritten, the interface circuit 90 outputs the write clock signal BCD_WCK to the clock circuit 40, and the clock circuit 40 converts the clock data BCD_T into the write data according to the write clock signal BCD_WCK. Update to write data BCD_WD which is part of WDAT. Further, when the clock data BIN_T is to be rewritten, the interface circuit 90 outputs the write clock signal BIN_WCK to the clock circuit 40, and the clock circuit 40 converts the clock data BIN_T into the write data in accordance with the write clock signal BIN_WCK. Update to write data BIN_WD which is part of WDAT.

Further, when the interface circuit 90 receives an access signal requesting reading of at least one of the clock data SUB_T, BCD_T, and BIN_T, it generates a read request signal (not shown) requesting reading of the clock data to be read, Output to read buffer 70. Then, the interface circuit 90 acquires read data RDAT, which is the time measurement data to be read acquired and held by the read buffer 70, converts the read data RDAT into a serial data signal SDA, and sends the serial data signal SDA to the host device 6 via the terminal P7. Send to.

Further, when the interface circuit 90 receives an access signal requesting to read the time data TSTMP, the interface circuit 90 selects the time measurement data to be read out of the time measurement data SUB_T, BCD_T, and BIN_T included in the time data TSTMP held by the event time register 80. , converts the time measurement data into a serial data signal SDA, and transmits it to the host device 6 via the terminal P7.

Note that in this embodiment, when the time stamp function is enabled and the interface circuit 90 receives an access signal instructing to disable the time stamp function, the interface circuit 90 disables the time stamp function. A control signal (not shown) for this purpose is output to the event time register 80. Further, when the time stamp function is disabled and the interface circuit 90 receives an access signal instructing to enable the time stamp function, the interface circuit 90 performs a process (not shown) to enable the time stamp function. A control signal is output to the event time register 80.

Further, when the interface circuit 90 receives an access signal requesting writing or reading data to or from the storage unit 100, the interface circuit 90 writes or reads data to or from the storage unit 100. In particular, in this embodiment, the interface circuit 90 receives the correction data TD from the host device 6 and writes it into the storage unit 100. Further, the interface circuit 90 may receive the correction period setting data PN from the host device 6 and write it into the storage unit 100. Thereby, the host device 6 can appropriately change the correction period setting data PN to an optimal value in accordance with environmental changes and time measurement changes of the real-time clock circuit 3. Similarly, the interface circuit 90 may receive selection data SEL from the host device 6 and write it into the storage unit 100.

The storage unit 100 is a circuit that stores various data. In this embodiment, the storage unit 100 includes a non-volatile memory and a register (not shown). Various data are stored in the non-volatile memory, and when the power supply voltage VLOGIC rises from 0V and reaches a predetermined voltage value, the various data stored in the non-volatile memory is transferred to the register. The various data transferred to the registers are then output to each circuit.

For example, the nonvolatile memory of the storage unit 100 stores the selection data SEL and the initial values of the correction period setting data PN, and the selection data SEL transferred to the register is output to the second frequency dividing circuit 30 and stored in the register. The correction period setting data PN transferred to is output to the logic circuit 50 and the interrupt generation circuit 110. Thereafter, the selection data SEL and the correction period setting data PN may be updated by being written from the host device 6 to the register of the storage unit 100 via the interface circuit 90. Note that if there is no need to change the selection data SEL or the correction period setting data PN, the selection data SEL or the correction period setting data PN do not need to be updated as they are at their initial values. Further, the correction data TD is written from the host device 6 to the register of the storage unit 100 via the interface circuit 90 and output to the logic circuit 50.

The interrupt generation circuit 110 generates an interrupt signal IRQ based on the reference signal REF and the correction period setting data PN, and outputs the interrupt signal IRQ to the host device 6 via the terminal P8 of the real-time clock circuit 3. Specifically, assuming that the value of the correction period setting data PN is n, the interrupt generation circuit 110 generates the interrupt signal IRQ when a predetermined timing at which the voltage level of the reference signal REF changes occurs n+1 times. For example, the predetermined timing at which the voltage level of the reference signal REF transitions may be the timing at which the reference signal REF transitions from a low level to a high level, or the timing at which the reference signal REF transitions from a high level to a low level. There may be. Upon receiving the interrupt signal IRQ, the host device 6 performs an interrupt process, reads out two pieces of clock data included in the time data TSTMP, and generates correction data TD based on the two pieces of clock data. The two pieces of clock data read by the host device 6 are, for example, two pieces of clock data held in the event time register 80 at the timings when the voltage level of the reference signal REF changes for the first time and the (n+1) time. The host device 6 calculates the amount of change in the clock data SUB_T at intervals of n cycles of the reference signal REF based on the difference between the clock data SUB_T included in the two clock data, and generates correction data TD.

Note that the clock data SUB_T is an example of "first clock data", and the clock data BCD_T or clock data BIN_T is an example of "second clock data".

1-1-2. Configuration of Time Counting Circuit FIG. 2 is a diagram showing an example of the configuration of the time counting circuit 40. As shown in FIG. As shown in FIG. 2, the clock circuit 40 includes counters 41 to 47.

The counter 41 is a second counter, and generates a count value representing time in seconds by performing a counting operation in synchronization with the third clock signal CK3. For example, the counter 41 is a sexagesimal BCD (Binary Coded Decimal) counter, and sequentially generates BCD count values representing decimal numbers 0 to 59 in synchronization with the pulses of the third clock signal CK3. When the count value becomes equal to the value representing decimal number 59, the counter 41 resets the count value to 0 and outputs the carry signal CA1 in synchronization with the next pulse of the third clock signal CK3. The count value generated by the counter 41 is used as time measurement data BCD_T1 representing time in seconds. That is, the counter 41 updates the clock data BCD_T1 in units of one second. Further, the counter 41 updates the count value, that is, the clock data BCD_T1, to the value of 1 byte of bits 0 to 7 of the write data BCD_WD in synchronization with the pulse of the write clock signal BCD_WCK.

The counter 42 is a minute counter, and generates a count value representing time in minutes by performing a counting operation in synchronization with the carry signal CA1. For example, the counter 42 is a sexagesimal BCD counter, and sequentially generates BCD count values representing decimal numbers 0 to 59 in synchronization with the pulses of the carry signal CA1. When the count value becomes equal to a value representing decimal number 59, the counter 42 resets the count value to 0 and outputs the carry signal CA2 in synchronization with the next pulse of the carry signal CA1. The count value generated by the counter 42 is used as time measurement data BCD_T2 representing time in minutes. That is, the counter 42 updates the clock data BCD_T2 on a minute-by-minute basis. Further, the counter 42 updates the count value, that is, the clock data BCD_T2, to the value of 1 byte of bits 8 to 15 of the write data BCD_WD in synchronization with the pulse of the write clock signal BCD_WCK.

The counter 43 is an hour counter, and generates a count value representing time in hours by performing a counting operation in synchronization with the carry signal CA2. For example, the counter 43 is a 24-ary BCD counter, and sequentially generates BCD count values representing decimal numbers 0 to 23 in synchronization with the pulses of the carry signal CA2. When the count value becomes equal to the value representing decimal number 23, the counter 43 resets the count value to 0 and outputs the carry signal CA3 in synchronization with the next pulse of the carry signal CA2. The count value generated by the counter 43 is used as time measurement data BCD_T3 representing time in hours. That is, the counter 43 updates the clock data BCD_T3 on an hourly basis. Further, the counter 43 updates the count value, that is, the clock data BCD_T3, to the value of 1 byte of bits 16 to 23 of the write data BCD_WD in synchronization with the pulse of the write clock signal BCD_WCK.

The counter 44 is a day counter, and generates a count value representing time in days by performing a counting operation in synchronization with the carry signal CA3. For example, the counter 44 is a decimal BCD counter, and sequentially generates BCD count values representing decimal numbers 1 to 31 in synchronization with the pulses of the carry signal CA3. However, depending on the month, the count value on the last day of the month needs to be 28 or 30, and in February of a leap year, the count value on the last day of the month needs to be 29. Therefore, the counter 44 compares a count value representing time on a daily basis with a count upper limit value set based on a count value representing time on a monthly basis and a count value representing time on a yearly basis. When the count value becomes equal to the count upper limit value, the counter 44 resets the count value to 1 and outputs the carry signal CA4 in synchronization with the next pulse of the carry signal CA3. The count value generated by the counter 44 is used as time measurement data BCD_T4 representing the time on a daily basis. That is, the counter 44 updates the clock data BCD_T4 on a daily basis. Further, the counter 44 updates the count value, that is, the clock data BCD_T4, to the value of 1 byte of bits 24 to 31 of the write data BCD_WD in synchronization with the pulse of the write clock signal BCD_WCK.

The counter 45 is a monthly counter, and generates a count value representing time on a monthly basis by performing a counting operation in synchronization with the carry signal CA4. For example, the counter 45 is composed of a hexadecimal BCD counter, and sequentially generates BCD count values representing decimal numbers 1 to 12 in synchronization with the pulses of the carry signal CA4. When the count value becomes equal to the value representing decimal number 12, the counter 45 resets the count value to 1 and outputs the carry signal CA5 in synchronization with the next pulse of the carry signal CA4. The count value generated by the counter 45 is used as time measurement data BCD_T5 representing time on a monthly basis. That is, the counter 45 updates the clock data BCD_T5 on a monthly basis. Further, the counter 45 updates the count value, that is, the clock data BCD_T5, to the value of 1 byte of bits 32 to 39 of the write data BCD_WD in synchronization with the pulse of the write clock signal BCD_WCK.

The counter 46 is a year counter, and generates a count value representing time in units of years by performing a counting operation in synchronization with the carry signal CA5. For example, the counter 46 is composed of a decimal BCD counter, and in synchronization with the pulse of the carry signal CA5, a BCD count representing the lower two digits of the decimal number 2020, 2021, 2022, etc. in the case of the Western calendar year. Generate values sequentially. The count value generated by the counter 46 is used as time measurement data BCD_T6 representing time in units of years. That is, the counter 46 updates the time measurement data BCD_T6 on a yearly basis. Further, the counter 46 updates the count value, that is, the clock data BCD_T6, to the value of 1 byte of bits 40 to 47 of the write data BCD_WD in synchronization with the pulse of the write clock signal BCD_WCK.

The aforementioned time measurement data BCD_T is composed of time measurement data BCD_T6 to BCD_T1, which are count values of year, month, day, hour, minute, and second.

The counter 47 is a second counter, and generates a count value representing time in seconds by performing a counting operation in synchronization with the third clock signal CK3. For example, the counter 41 is a binary counter and sequentially generates binary values that increase in synchronization with the pulses of the third clock signal CK3. The count value generated by the counter 47 is used as time measurement data BIN_T representing year, month, day, hour, minute, and second as time in seconds. That is, the counter 47 updates the time measurement data BIN_T in units of one second. Further, the counter 47 updates the count value, that is, the clock data BIN_T, to the value of the write data BIN_WD in synchronization with the pulse of the write clock signal BIN_WCK.

As described above, in the present embodiment, the timekeeping circuit 40 generates timekeeping data BCD_T that represents the year, month, day, hour, minute, and second using BCD count values, and also generates the year, month, day, hour, minute, and second. Time measurement data BIN_T representing seconds as a binary value in units of seconds is also generated. The host device 6 can read or write one or both of the clock data BCD_T and BIN_T from the real-time clock module 1 depending on the purpose of the system, and can perform processes necessary for the system.

1-1-3. Configuration of First Frequency Divider Circuit FIG. 3 is a diagram showing a configuration example of the first frequency divider circuit 20. As shown in FIG. 3, the first frequency dividing circuit 20 includes a frequency dividing circuit 21 and frequency dividing circuits 22 to 25.

The frequency dividing circuit 21 basically generates the clock signal CKA by dividing the frequency of the first clock signal CK1 by two. The divide-by-2 circuit 22 generates the clock signal CKB by dividing the frequency of the clock signal CKA by two. The divide-by-2 circuit 23 generates the clock signal CKC by dividing the clock signal CKB by two. The divide-by-2 circuit 24 generates the clock signal CKD by dividing the clock signal CKC by two. The divide-by-2 circuit 25 generates a second clock signal CK2 by dividing the clock signal CKD by two.

The first frequency dividing circuit 20 configured in this manner operates as a binary counter and generates a second clock signal CK2 by dividing the frequency of the first clock signal CK1 by 32. For example, when the frequency of the first clock signal CK1 is 32.764 kHz, the frequency of the second clock signal CK2 is 1.024 kHz. Furthermore, when the frequency of the first clock signal CK1 is 32 kHz, the frequency of the second clock signal CK2 is 1 kHz.

However, for example, if the frequency of the first clock signal CK1 is adjusted to be the target frequency when the environmental temperature is 25 degrees Celsius, the temperature characteristics of the vibrator 2 may cause the first clock signal to The error of the frequency of CK1 with respect to the target frequency becomes large. Furthermore, due to changes in the vibrator 2 over time, the error in the frequency of the first clock signal CK1 relative to the target frequency increases.

Therefore, in this embodiment, as shown in FIG. Gradual processing is carried out. In this embodiment, the control signals PE and PD are both low level signals or only one signal is high level, and when the control signals PE and PD are both low level, the frequency dividing circuit 21 outputs the first clock signal CK1. A clock signal CKA obtained by dividing the frequency by two is output. Further, when the control signal PE is at a high level, the frequency dividing circuit 21 outputs the first clock signal CK1 as it is as the clock signal CKA without dividing the frequency by two. Furthermore, when the control signal PD is at a high level, the frequency dividing circuit 21 outputs a clock signal CKA obtained by dividing the first clock signal CK1 by four. In this way, by performing the speed-up process on the frequency dividing circuit 21, the average frequency of the second clock signal CK2 approaches the desired frequency.

1-1-4. Configuration of Second Frequency Divider Circuit As described above, the second frequency divider circuit 30 operates as a binary counter or a BCD counter depending on the value of the selection data SEL.

FIG. 4 is a diagram showing a configuration example of the second frequency dividing circuit 30 when the selection data SEL is 0. As shown in FIG. 4, the second frequency divider circuit 30 includes frequency divider circuits 31 to 3A. When the selection data SEL is 0, the frequency of the second clock signal CK2 input to the second frequency dividing circuit 30 is 1.024 kHz.

The divide-by-2 circuit 31 divides the second clock signal CK2 of 1.024 kHz by two to generate a clock signal of 512 Hz. This 512 Hz clock signal is used as bit 0 of time measurement data SUB_T. Furthermore, the divide-by-2 circuit 31 updates the value of bit 0 of the clock data SUB_T to the value of bit 0 of the write data SUB_WD in synchronization with the pulse of the write clock signal SUB_WCK.

The divide-by-2 circuit 32 divides the frequency of the 512 Hz clock signal generated by the divide-by-2 circuit 31 by two to generate a 256 Hz clock signal. This 256 Hz clock signal is used as bit 1 of time measurement data SUB_T. Further, the divide-by-2 circuit 32 updates the value of bit 1 of the clock data SUB_T to the value of bit 1 of the write data SUB_WD in synchronization with the pulse of the write clock signal SUB_WCK.

The divide-by-2 circuit 33 divides the 256 Hz clock signal generated by the divide-by-2 circuit 32 by two to generate a 128 Hz clock signal. This 128 Hz clock signal is used as bit 2 of time measurement data SUB_T. Further, the divide-by-2 circuit 33 updates the value of bit 2 of the clock data SUB_T to the value of bit 2 of the write data SUB_WD in synchronization with the pulse of the write clock signal SUB_WCK.

The divide-by-2 circuit 34 divides the 128 Hz clock signal generated by the divide-by-2 circuit 33 by two to generate a 64 Hz clock signal. This 64 Hz clock signal is used as bit 3 of time measurement data SUB_T. Further, the divide-by-2 circuit 34 updates the value of bit 3 of the clock data SUB_T to the value of bit 3 of the write data SUB_WD in synchronization with the pulse of the write clock signal SUB_WCK.

The divide-by-2 circuit 35 divides the frequency of the 64 Hz clock signal generated by the divide-by-2 circuit 34 by two to generate a 32 Hz clock signal. This 32 Hz clock signal is used as bit 4 of time measurement data SUB_T. Further, the divide-by-2 circuit 35 updates the value of bit 4 of the clock data SUB_T to the value of bit 4 of the write data SUB_WD in synchronization with the pulse of the write clock signal SUB_WCK.

The divide-by-2 circuit 36 divides the frequency of the 32 Hz clock signal generated by the divide-by-2 circuit 35 by two to generate a 16 Hz clock signal. This 16 Hz clock signal is used as bit 5 of time measurement data SUB_T. Further, the divide-by-2 circuit 36 updates the value of bit 5 of the clock data SUB_T to the value of bit 5 of the write data SUB_WD in synchronization with the pulse of the write clock signal SUB_WCK.

The divide-by-2 circuit 37 divides the frequency of the 16 Hz clock signal generated by the divide-by-2 circuit 36 by two to generate an 8 Hz clock signal. This 8 Hz clock signal is used as bit 6 of the time measurement data SUB_T and is also used as the fourth clock signal CK4. Further, the divide-by-2 circuit 37 updates the value of bit 6 of the clock data SUB_T to the value of bit 6 of the write data SUB_WD in synchronization with the pulse of the write clock signal SUB_WCK.

The divide-by-2 circuit 38 divides the frequency of the 8 Hz clock signal generated by the divide-by-2 circuit 37 by two to generate a 4 Hz clock signal. This 4Hz clock signal is used as bit 7 of time measurement data SUB_T. Furthermore, the divide-by-2 circuit 38 updates the value of bit 7 of the clock data SUB_T to the value of bit 7 of the write data SUB_WD in synchronization with the pulse of the write clock signal SUB_WCK.

The divide-by-2 circuit 39 divides the frequency of the 4 Hz clock signal generated by the divide-by-2 circuit 38 by two to generate a 2 Hz clock signal. This 2Hz clock signal is used as bit 8 of time measurement data SUB_T. Further, the divide-by-2 circuit 39 updates the value of bit 8 of the clock data SUB_T to the value of bit 8 of the write data SUB_WD in synchronization with the pulse of the write clock signal SUB_WCK.

The divide-by-2 circuit 3A divides the frequency of the 2 Hz clock signal generated by the divide-by-2 circuit 39 by two to generate a third clock signal CK3 of 1 Hz. The third clock signal CK3 is the clock data SUB
Used as bit 9 of _T. Further, the divide-by-2 circuit 3A updates the value of bit 9 of the clock data SUB_T to the value of bit 9 of the write data SUB_WD in synchronization with the pulse of the write clock signal SUB_WCK.

In this way, when the selection data SEL is 0, the second frequency dividing circuit 30 divides the second clock signal CK2 of 1.024 kHz by 1024 to generate the third clock signal CK3 of 1 Hz, and also generates the third clock signal CK3 of 1 Hz. The second clock signal CK2 of 0.024 kHz is divided by 128 to generate a fourth clock signal CK4 of 8 Hz.

FIG. 5 is a diagram showing a configuration example of the second frequency dividing circuit 30 when the selection data SEL is 1. As shown in FIG. 5, the second frequency dividing circuit 30 includes counters 3B, 3C, and 3D. When the selection data SEL is 0, the frequency of the second clock signal CK2 input to the second frequency dividing circuit 30 is 1 kHz.

The counter 3B generates a count value representing time in units of 1/1000 seconds by performing a counting operation in synchronization with the second clock signal CK2 of 1 kHz. For example, the counter 3B is a decimal BCD counter, and sequentially generates BCD count values representing decimal numbers 0 to 9 in synchronization with the pulses of the second clock signal CK2. When the count value becomes equal to a value representing 9 in decimal, the counter 3B resets the count value to 0 and outputs a 100 Hz carry signal CA11 in synchronization with the next pulse of the second clock signal CK2. The count value generated by the counter 3B is used as time measurement data SUB_T1 representing time in units of 1/1000 seconds. That is, the counter 3B updates the time measurement data SUB_T1 in units of 1/1000 seconds. Further, the counter 3B updates the count value, that is, the time measurement data SUB_T1, to the value of 1 byte of bits 0 to 7 of the write data SUB_WD in synchronization with the pulse of the write clock signal SUB_WCK.

The counter 3C generates a count value representing time in units of 1/100 seconds by performing a counting operation in synchronization with the 100 Hz carry signal CA11. For example, the counter 3C is a decimal BCD counter, and sequentially generates BCD count values representing decimal numbers 0 to 9 in synchronization with the pulses of the carry signal CA11. When the count value becomes equal to the value representing 9 in decimal, the counter 3C resets the count value to 0 and outputs a 10 Hz carry signal CA12 in synchronization with the next pulse of the carry signal CA11. The count value generated by the counter 3C is used as time measurement data SUB_T2 representing time in units of 1/100 seconds. That is, the counter 3C updates the time measurement data SUB_T2 in units of 1/100 seconds. Furthermore, the 10 Hz carry signal CA12 is used as the fourth clock signal CK4. Further, the counter 3C updates the count value, that is, the time measurement data SUB_T2, to the value of 1 byte of bits 8 to 15 of the write data SUB_WD in synchronization with the pulse of the write clock signal SUB_WCK.

The counter 3D generates a count value representing time in units of 1/10 seconds by performing a counting operation in synchronization with the 10 Hz carry signal CA12. For example, the counter 3D is a decimal BCD counter and sequentially generates BCD count values representing decimal numbers 0 to 9 in synchronization with the pulses of the carry signal CA12. When the count value becomes equal to the value representing 9 in decimal, the counter 3D resets the count value to 0 in synchronization with the next pulse of the carry signal CA12, and outputs the third clock signal CK3 of 1 Hz. The count value generated by the counter 3D is used as time measurement data SUB_T3 representing time in 1/10 second units. That is, the counter 3D updates the time measurement data SUB_T3 in units of 1/10 seconds. Further, the counter 3D updates the count value, that is, the time measurement data SUB_T3, to the value of 1 byte of bits 16 to 23 of the write data SUB_WD in synchronization with the pulse of the write clock signal SUB_WCK.

In this way, when the selection data SEL is 1, the second frequency dividing circuit 30 divides the 1 kHz second clock signal CK2 by 1000 to generate the 1 Hz third clock signal CK3, and also generates the 1 kHz second clock signal CK3. The clock signal CK2 is divided by 100 to generate a fourth clock signal CK4 of 10 Hz. Further, the aforementioned time measurement data SUB_T is composed of time measurement data SUB_T3, SUB_T2, and SUB_T1, which are count values of 1/10 second, 1/100 second, and 1/1000 second.

1-1-5. Slow/Slow Processing by Logic Circuit As described above, the length of the correction period in which the slow/fast process is performed by the logic circuit 50 differs depending on the value of the selection data SEL.

FIG. 6 is a diagram illustrating an example of the relationship between the correction period and the timing of the adjustment process when the selection data SEL is 0. As shown in FIG. 6, when the selection data SEL is 0, one correction period is 32 seconds, which is 256 times 0.125 seconds, which is the time of one cycle of the 8Hz fourth clock signal CK4. be. Further, the timing of the slow/fast processing comes every cycle of the fourth clock signal CK4, that is, at intervals of 0.125 seconds. That is, in one correction period, a maximum of 256 slow and fast processes are possible.

FIG. 7 is a diagram illustrating an example of the relationship between the correction period and the timing of the adjustment process when the selection data SEL is 1. As shown in FIG. 7, when the selection data SEL is 1, one correction period is 25.6 times, which is 256 times the time of 0.1 second, which is the time of one period of the fourth clock signal CK4 of 10 Hz. Seconds. Further, the timing of the slow/fast processing occurs every cycle of the fourth clock signal CK4, that is, at intervals of 0.1 seconds. That is, in one correction period, a maximum of 256 slow and fast processes are possible.

Although only one correction period is illustrated in FIGS. 6 and 7, in reality, the next correction period starts every time one correction period ends. That is, the correction period shown in FIG. 6 or 7 is repeated without any interval.

The slow and fast processing performed at each timing during the correction period is controlled by control signals PE and PD. FIG. 8, FIG. 9, and FIG. 10 are diagrams for explaining the speed and speed processing performed in response to the control signals PE and PD. FIG. 8 is a timing chart when the control signals PE and PD are both at a low level at the timing of the speed-up process. FIG. 9 is a timing chart when the control signal PE is at a high level and the control signal PD is at a low level at the timing of the speed-up process. FIG. 10 is a timing chart when the control signal PE is at a low level and the control signal PD is at a high level at the timing of the speed-up process.

As shown in FIG. 8, when the control signals PE and PD are both at a low level at the timing of the speed-up process, the clock signal CKA remains a signal obtained by dividing the first clock signal CK1 by two. As a result, the number of pulses of the first clock signal CK1 in the half cycle of the second clock signal CK2 immediately after the timing remains 16. That is, the number of pulses of the first clock signal CK1 in one period of the second clock signal CK2 remains unchanged at 32.

On the other hand, as shown in FIG. 9, when the control signal PE is at a high level and the control signal PD is at a low level at the timing of the slow/fast process, the clock signal CKA matches the first clock signal CK1. As a result, the number of pulses of the first clock signal CK1 in the half cycle of the second clock signal CK2 immediately after the timing is 15. In other words, when the control signal PE is at a high level and the control signal PD is at a low level at the timing of the adjustment process, the number of pulses of the first clock signal CK1 becomes 31 for one cycle of the second clock signal CK2 immediately after that, and the number of pulses of the first clock signal CK1 becomes 31, and The period of the clock signal CK2 is shorter than each other period by one period of the first clock signal CK1.

Further, as shown in FIG. 10, when the control signal PE is at a low level and the control signal PD is at a high level at the timing of the slow/fast process, the clock signal CKA becomes a signal obtained by dividing the first clock signal CK1 by four. As a result, the number of pulses of the first clock signal CK1 in the half cycle of the second clock signal CK2 immediately after the timing is 17. In other words, when the control signal PE is at a low level and the control signal PD is at a high level at the timing of the adjustment process, the number of pulses of the first clock signal CK1 becomes 33 for one cycle of the second clock signal CK2 immediately after that, and the number of pulses of the first clock signal CK1 becomes 33, and This period of the clock signal CK2 is longer than each other period by one period of the first clock signal CK1.

When the correction data TD is 9-bit data that can take on 511 integer values from −255 to +255, the logic circuit 50 performs 256 times in one correction period according to the value of the correction data TD. The slow and fast processing is performed at timings from 0 to 255 of the slow and fast processing timings.

For example, if the number of pulses of the first clock signal CK1 in 32 seconds counted by the reference signal REF is 32 x 32768 = 1048576, the frequency of the first clock signal CK1 matches the target frequency of 32.768 kHz. The value of the correction data TD becomes 0. In this case, the logic circuit 50 fixes the control signals PE and PD to a low level in each correction period, so that the length of one cycle of the second clock signal CK2 is always equal to the length of 32 cycles of the first clock signal CK1. make them equal. As a result, the number of pulses of the first clock signal CK1 in 32,768 cycles of the second clock signal CK2 of 1.024 kHz is 1048,576, and the 32,768 cycles of the second clock signal CK2 match the 32 seconds counted by the reference signal REF.

On the other hand, if the number of pulses of the first clock signal CK1 in 32 seconds counted by the reference signal REF is 1048576-255=1048321, the frequency of the first clock signal CK1 is lower than the target frequency of 32.768kHz, The value of the correction data TD becomes +255. In this case, the logic circuit 50 sets the control signal PE to a high level at 255 timings out of 256 timings of slow/fast processing in each correction period, thereby increasing the length of one cycle of the second clock signal CK2 only 255 times. is made equal to the length of 31 cycles of the first clock signal CK1. As a result, the number of pulses of the first clock signal CK1 in 32768 periods of the second clock signal CK2 of 1.024 kHz is 1048576-255=1048321, and the 32768 periods of the second clock signal CK2 are equal to 32 seconds counted by the reference signal REF. Match.

Further, if the number of pulses of the first clock signal CK1 in 32 seconds counted by the reference signal REF is 1048576+255=1048831, the frequency of the first clock signal CK1 is higher than the target frequency of 32.768kHz, and the value of the correction data TD is becomes -255. In this case, the logic circuit 50 sets the control signal PD to a high level at 255 timings out of 256 timings of slow/fast processing in each correction period, thereby increasing the length of one period of the second clock signal CK2 by 255 times. is made equal to the length of 33 cycles of the first clock signal CK1. As a result, the number of pulses of the first clock signal CK1 in 32,768 cycles of the second clock signal CK2 of 1.024 kHz is 1048,576 + 255 = 1048,831, and the 32,768 cycles of the second clock signal CK2 match the 32 seconds counted by the reference signal REF. .

In this way, in the real-time clock circuit 3 of the present embodiment, the logic circuit 50 controls the first frequency dividing circuit 20 to adjust speed or speed during the correction period corresponding to an interval longer than 1 second, which is the period of the third clock signal CK3. Perform processing. Thereby, the real-time clock circuit 3 can correct the second clock signal CK2 with high resolution. For example, if the target frequency of the first clock signal CK1 is 32.768 kHz and the correction period is 32 seconds, the resolution is 1/32.768 kHz/32=0.954 ppm. Further, when the target frequency of the first clock signal CK1 is 32 kHz and the correction period is 25.6 seconds, the resolution is 1/32 kHz/25.6=1.22 ppm.

Furthermore, in the present embodiment, the logic circuit 50 performs the slowing/fastening process on the first frequency dividing circuit 20 at time intervals longer than the cycle of the second clock signal CK2 during the correction period. That is, the logic circuit 50 performs the speed and speed processing in a time-distributed manner, thereby making it possible to reduce variations in the amount of frequency fluctuation of the second clock signal CK2.

1-1-6. Method for correcting real-time clock circuit FIG. 11 is a diagram illustrating an example of a procedure for a method for correcting real-time clock circuit 3 according to the first embodiment.

As shown in FIG. 11, first, the host device 6 enables the time stamp function of the real-time clock circuit 3 (step S1).

Next, the host device 6 transmits the reference signal REF to the real-time clock circuit 3 (step S2).

Next, the real-time clock circuit 3 holds time measurement data in the event time register 80 at a predetermined timing when the voltage level of the reference signal REF changes (step S3). The clock data held in step S3 includes clock data SUB_T, and further includes clock data BCD_T or clock data BIN_T.

Then, steps S2 and S3 are repeated until the real-time clock circuit 3 receives the reference signal REF n+1 times (N in step S4). The integer n is the value of the correction period setting data PN described above. For example, if n is 32 and the period of the reference signal REF is 1 second, until the real-time clock circuit 3 receives the reference signal REF 33 times, that is, 32 seconds have elapsed since the first reception of the reference signal REF. Steps S2 and S3 are repeated until the process is completed.

When the real-time clock circuit 3 receives the reference signal REF n+1 times (Y in step S4), the host device 6 disables the time stamp function of the real-time clock circuit 3 (step S5).

Next, the real-time clock circuit 3 transmits an interrupt signal IRQ to the host device 6 (step S6).

Next, the host device 6 receives the interrupt signal IRQ and reads out the first and (n+1)th time measurement data held in the event time register 80 from the real-time clock circuit 3 (step S7).

Next, the host device 6 calculates the difference ΔT between the (n+1)th clock data and the first clock data (step S8). For example, if n is 32 and the period of the reference signal REF is 1 second, the difference ΔT corresponds to the amount of increase in the time measurement data for 32 seconds.

Then, if the error of the difference ΔT with respect to the expected value is within 1 second (Y in step S9), the host device 6 generates correction data TD based on the variation ΔSubCnt of less than 1 second, and the generated correction data TD is written into the storage unit 100 of the real-time clock circuit 3 (step S10). The amount of change ΔSubCnt is the difference between the (n+1)th time measurement data SUB_T and the first time measurement data SUB_T. For example, if n is 32 and the period of the reference signal REF is 1 second, the expected value of the difference ΔT is 32 seconds, so step S10 is performed when the difference ΔT is 31 seconds or more and 33 seconds or less. . Further, in step S10, the host device 6 calculates the value of the correction data TD by 200h-ΔSubCnt on the premise that the amount of change ΔSubCnt is a value in the range of −255 to +255.

Next, the real-time clock circuit 3 uses the correction data TD written to the storage unit 100 in step S10 to perform speed-up processing on the first frequency dividing circuit 20 (step S11). Thereafter, the real-time clock circuit 3 uses the correction data TD in each correction period to perform slow and fast processing in a temporally distributed manner until the correction data TD is updated.

On the other hand, if the difference ΔT is larger than 1 second (N in step S9), the host device 6 writes the current time data to the write buffer 60 of the real-time clock circuit 3 (step S12). For example, the host device 6 writes time data of the year, month, day, hour, minute, and second, and time data representing the year, month, day, hour, minute, and second in seconds to the write buffer 60.

Next, the real-time clock circuit 3 updates the clock data BCD_T, BIN_T of the clock circuit 40 to the current time data held by the write buffer 60 (step S13).

Then, after step S11 or step S13, steps S1 to S13 are repeatedly performed every time a predetermined interval time elapses (Y in step S14).

As described above, in the present embodiment, the logic circuit 50 adjusts the second clock signal in the same 32-second correction period based on the correction data TD generated based on the change amount ΔSubCnt of less than 1 second during 32 seconds, for example. Slow and fast processing is performed so that the frequency of CK2 becomes 1.024 kHz on average. Alternatively, the logic circuit 50 determines that the frequency of the second clock signal CK2 during the correction period, which is also 25.6 seconds, is Slow and fast processing is performed so that the average frequency is 1 kHz. For example, if the amount of change ΔSubCnt is in the range of -255 to +255, the target frequency of the first clock signal CK1 is 32.768 kHz, and the correction period is 32 seconds, then as mentioned above, the resolution of the slow/fast processing is approximately Since it is 0.954 ppm, the speed range is -243.19 ppm to +243.19 ppm. Further, when the target frequency of the first clock signal CK1 is 32 kHz and the correction period is 25.6 seconds, the resolution of the adjustment process is approximately 1.22 ppm, so the adjustment width is -311.28 ppm to +311. It is 28 ppm. Therefore, assuming that the maximum frequency fluctuation amount of the first clock signal CK1 due to changes in environmental temperature or changes over time is several ppm to several tens of ppm, the real-time clock circuit 3 can perform slow and fast processing with a sufficient width.

In addition, by matching the length of the correction period with the interval synchronized with the reference signal REF, which is the period for calculating the change amount ΔSubCnt of less than 1 second, the value of the correction data TD is reversed with the sign of the change amount ΔSubCnt. The calculation load of the correction data TD by the host device 6 can be reduced.

1-1-7. Effects As explained above, in the first embodiment, in the real-time clock circuit 3, the logic circuit 50 outputs time measurement data SU for a time shorter than one second at intervals synchronized with the reference signal REF.
Using the correction data TD generated based on the amount of change in B_T, the first frequency divider circuit 20 that generates the second clock signal CK2 performs a speed adjustment process. Therefore, the second clock signal CK2 is corrected using the correction data TD generated in an arbitrary short time period of one second or more. Then, the second frequency dividing circuit 30 divides the frequency of the second clock signal CK2 to generate a third clock signal CK3, and the clock circuit 40 generates clock data BCD_T for a time of one second or more based on the third clock signal CK3. Since BIN_T is generated, the clock data BCD_T and BIN_T are corrected in a short time. Further, in the real-time clock circuit 3, correction data TD is generated based on the amount of change in the time measurement data SUB_T at intervals synchronized with the reference signal REF. Therefore, there is no need for the real-time clock circuit 3 to output the third clock signal CK3 to the host device 6, and for the host device 6 to measure the frequency of the third clock signal CK3 and create the correction data TD. Therefore, according to the first embodiment, the real-time clock circuit 3 can easily acquire the correction data TD of the time measurement data in a short time. Furthermore, in the first embodiment, in the real-time clock circuit 3, the length of the period during which the speed-up/down process using the correction data TD is performed is the interval during which the amount of change in the time measurement data SUB_T is calculated in order to generate the correction data TD. Therefore, the value obtained by inverting the sign of the amount of change in the time measurement data SUB_T can be set as the value of the correction data TD. Therefore, according to the first embodiment, the host device 6 can easily generate the correction data TD. As described above, according to the first embodiment, excellent user convenience can be achieved.

Furthermore, in the first embodiment, in the real-time clock circuit 3, the interval at which the amount of change in the clock data SUB_T is calculated in order to generate the correction data TD is longer than 1 second, which is the period of the third clock signal CK3. , the logic circuit 50 can correct the second clock signal CK2 with high resolution. Furthermore, since the errors in the time measurement data SUB_T are averaged, the influence of jitter and the like on the first clock signal CK1 is also reduced. Furthermore, in the real-time clock circuit 3, the logic circuit 50 performs slowing/fastening processing on the first frequency dividing circuit 20 in a temporally distributed manner at time intervals longer than the period of the second clock signal CK2. It is possible to reduce variations in the amount of frequency fluctuation of the signal CK2. For example, as described above, by setting the resolution of the correction by the slow and fast processing to 0.954 ppm, it is possible to reduce the 1 second error between the clock data BCD_T and BIN_T to 1 ppm or less. In particular, when the logic circuit 50 performs the adjustment process on the first frequency dividing circuit 21 included in the first frequency dividing circuit 20, it is possible to reduce the error in the time measurement data SUB_T of less than one second.

Furthermore, in the first embodiment, in the real-time clock circuit 3, the frequency of the fourth clock signal CK4 is switched to 8 Hz or 10 Hz by switching the operation of the second frequency dividing circuit 30 according to the value of the selection data SEL. On the other hand, the logic circuit 5 The logic of slow and urgent processing will be standardized. Therefore, according to the first embodiment, even if the operation of the second frequency divider circuit 30 is switched in the real-time clock circuit 3, the influence on the control of the speed-up process is small.

Further, in the first embodiment, the host device 6 generates the correction data TD based on the time measurement data SUB_T held in the event time register 80 by the time stamp function of the real-time clock circuit 3. Therefore, according to the first embodiment, even if there is variation in the delay time required to read the time measurement data SUB_T held in the event time register 80, an error in the time measurement data SUB_T due to the variation in delay time does not occur, so that the host The device 6 is able to generate accurate correction data TD. Furthermore, since the host device 6 can generate the correction data TD in a short time without stopping the operation of the real-time clock module 1, it is also applicable to aging correction, for example. In particular, when aging correction is performed on the oscillation circuit 10, the frequency error of the first clock signal CK1 becomes large in high or low temperature environments due to the influence of the temperature characteristics of the resonator 2. In contrast, in the first embodiment, the frequency error of the first clock signal CK1 due to the temperature characteristics of the resonator 2 is taken into account and the frequency of the second clock signal CK2 is adjusted by the slowing/slowing process of the logic circuit 50. is corrected, so the error of 1 second can be reduced.

Further, according to the first embodiment, since the host device 6 generates the correction data TD, the real-time clock circuit 3 does not need to generate the correction data TD, and the size of the real-time clock circuit 3 can be reduced.

Further, in the first embodiment, the host device 6 can write the correction period setting data PN into the storage section 100 of the real-time clock circuit 3. Therefore, according to the first embodiment, in order for the host device 6 to generate the correction data TD, the interval at which the amount of change in the clock data SUB_T is calculated, that is, the length of the correction period, is determined as the accuracy of the correction. The user can set it arbitrarily, taking into consideration the trade-off with the time required for correction.

1-2. Second Embodiment In the first embodiment, the host device 6 generates the correction data TD, whereas in the second embodiment, the real-time clock circuit 3 generates the correction data TD. Hereinafter, regarding the second embodiment, components similar to those of the first embodiment will be given the same reference numerals, explanations that overlap with those of the first embodiment will be omitted or simplified, and mainly contents different from the first embodiment will be explained. do.

FIG. 12 is a functional block diagram of the real-time clock module 1 of the second embodiment. In FIG. 12, the same components as in FIG. 1 are given the same reference numerals.

As shown in FIG. 12, in the real-time clock module 1 of the second embodiment, the real-time clock circuit 3 includes the same components as in FIG. 1, and further includes a correction data generation circuit 150.

The correction data generation circuit 150 generates correction data TD based on the clock data held by the event time register 80. The correction data generation circuit 150 acquires two pieces of clock data included in the time data TSTMP, and generates correction data TD based on the two pieces of clock data. Specifically, the correction data generation circuit 150 counts the number of times a predetermined timing at which the voltage level of the reference signal REF changes occurs, and generates an event at the timing when the voltage level of the reference signal REF changes for the first time and the (n+1) time. Two pieces of time measurement data held in the time register 80 are acquired. For example, the predetermined timing at which the voltage level of the reference signal REF transitions may be the timing at which the reference signal REF transitions from a low level to a high level, or the timing at which the reference signal REF transitions from a high level to a low level. There may be. Further, the integer n is the value of the correction period setting data PN described above. Then, the correction data generation circuit 150 calculates the amount of change in the time measurement data SUB_T at intervals of n cycles of the reference signal REF based on the difference between the time measurement data SUB_T included in the two acquired time measurement data, and generates the correction data TD. generate. In this way, the correction data TD is data generated based on the amount of change in the clock data SUB_T at intervals synchronized with the reference signal REF.

Using the correction data TD generated by the correction data generation circuit 150, the logic circuit 50 performs a speed adjustment process on the first frequency dividing circuit 20 during the correction period, similarly to the first embodiment.

Further, the correction data generation circuit 150 outputs an interrupt control signal IRE to the interrupt generation circuit 110 when the amount of change in the clock data SUB_T at intervals of n cycles of the reference signal REF is larger than a predetermined value. The predetermined value is, for example, 1 second. The interrupt generation circuit 110 generates an interrupt signal IRQ upon receiving the interrupt control signal IRE, and outputs the interrupt signal IRQ to the host device 6 via the terminal P8 of the real-time clock circuit 3. When the host device 6 receives the interrupt signal IRQ, it performs interrupt processing, writes the current time data to the write buffer 60 of the real-time clock circuit 3, and updates the clock data BCD_T and BIN_T of the clock circuit 40.

The rest of the configuration of the real-time clock module 1 of the second embodiment is the same as that of the first embodiment, so its construction will be omitted.

FIG. 13 is a diagram showing an example of a procedure of a correction method for the real-time clock circuit 3 according to the second embodiment.

As shown in FIG. 13, first, the host device 6 enables the time stamp function of the real-time clock circuit 3 (step S101).

Next, the host device 6 transmits the reference signal REF to the real-time clock circuit 3 (step S102).

Next, the real-time clock circuit 3 holds time measurement data in the event time register 80 at a predetermined timing when the voltage level of the reference signal REF changes (step S103). The clock data held in step S3 includes clock data SUB_T, and further includes clock data BCD_T or clock data BIN_T.

Then, steps S102 and S103 are repeated until the real-time clock circuit 3 receives the reference signal REF n+1 times (N in step S104). The integer n is the value of the correction period setting data PN described above. For example, if n is 32 and the period of the reference signal REF is 1 second, until the real-time clock circuit 3 receives the reference signal REF 33 times, that is, 32 seconds have elapsed since the first reception of the reference signal REF. Steps S102 and S103 are repeated until the process is completed.

When the real-time clock circuit 3 receives the reference signal REF n+1 times (Y in step S104), the host device 6 disables the time stamp function of the real-time clock circuit 3 (step S105).

Next, the real-time clock circuit 3 calculates the difference ΔT between the (n+1)th clock data and the first clock data held in the event time register 80 (step S106). For example, if n is 32 and the period of the reference signal REF is 1 second, the difference ΔT corresponds to the amount of increase in the time measurement data for 32 seconds.

If the error of the difference ΔT from the expected value is within 1 second (Y in step S107), the real-time clock circuit 3 generates correction data TD based on the variation ΔSubCnt of less than 1 second (step S108). The amount of change ΔSubCnt is the difference between the (n+1)th time measurement data SUB_T and the first time measurement data SUB_T. For example, if n is 32 and the period of the reference signal REF is 1 second, the expected value of the difference ΔT is 32 seconds, so step S108 is performed when the difference ΔT is between 31 seconds and 33 seconds. . Further, in step S108, the host device 6 calculates the value of the correction data TD by 200h-ΔSubCnt on the premise that the amount of change ΔSubCnt is a value in the range of −255 to +255.

Next, the real-time clock circuit 3 uses the correction data TD generated in step S108 to perform speed-up processing on the first frequency dividing circuit 20 (step S109). Thereafter, the real-time clock circuit 3 uses the correction data TD in each correction period to perform slow and fast processing in a temporally distributed manner until the correction data TD is updated.

On the other hand, if the difference ΔT is larger than 1 second (N in step S107), the real-time clock circuit 3 transmits the interrupt signal IRQ to the host device 6 (step S110).

Next, the host device 6 receives the interrupt signal IRQ and writes the current time data into the write buffer 60 of the real-time clock circuit 3 (step S111). For example, the host device 6 writes time data of the year, month, day, hour, minute, and second, and time data representing the year, month, day, hour, minute, and second in seconds to the write buffer 60.

Next, the real-time clock circuit 3 updates the clock data BCD_T, BIN_T of the clock circuit 40 to the current time data held by the write buffer 60 (step S112).

Then, after step S109 or step S112, steps S101 to S112 are repeatedly performed every time a predetermined interval time elapses (Y in step S113).

As described above, in the present embodiment, the logic circuit 50 adjusts the second clock signal in the same 32-second correction period based on the correction data TD generated based on the change amount ΔSubCnt of less than 1 second during 32 seconds, for example. Slow and fast processing is performed so that the frequency of CK2 becomes 1.024 kHz on average. Alternatively, the logic circuit 50 determines that the frequency of the second clock signal CK2 during the correction period, which is also 25.6 seconds, is Slow and fast processing is performed so that the average frequency is 1 kHz. In this way, by matching the length of the correction period with the interval synchronized with the reference signal REF, which is the period for calculating the change amount ΔSubCnt of less than 1 second, the value of the correction data TD can be changed to the sign of the change amount ΔSubCnt. It is sufficient to use an inverted value, and the size of the correction data generation circuit 150 can be reduced.

As described above, in the second embodiment, in the real-time clock circuit 3, the correction data generation circuit 150 generates the time measurement data SUB_T held in the event time register 80 at a predetermined timing when the voltage level of the reference signal REF changes. Based on this, correction data TD is generated. Therefore, according to the second embodiment, there is no need for the host device 6 to generate the correction data TD, so that the calculation load on the host device 6 can be reduced.

Further, according to the second embodiment, there is no need for the host device 6 to read out the time measurement data SUB_T, and therefore an error in the time measurement data SUB_T due to variations in the delay time required for reading does not occur, so that the correction data generation circuit 150 can accurately Correction data TD can be generated.

In addition, the real-time clock module 1 of the second embodiment has the same effects as the real-time clock module 1 of the first embodiment, as appropriate.

1-3. Third Embodiment In the first embodiment, the host device 6 reads the clock data held in the event time register 80 of the real-time clock circuit 3 and generates the correction data TD, whereas in the third embodiment, The host device 6 reads current time measurement data from the real-time clock circuit 3 and generates correction data TD. Hereinafter, regarding the third embodiment, the same reference numerals are given to the same components as in the first embodiment, explanations that overlap with those in the first embodiment are omitted or simplified, and mainly contents different from the first embodiment will be explained. do.

The functional block diagram of the real-time clock module 1 of the third embodiment is the same as that in FIG. 1, so its illustration is omitted.

In this embodiment, the host device 6 reads time measurement data from the real-time clock circuit 3 at intervals synchronized with the reference signal REF generated internally or received from the outside. The clock data read by the host device 6 includes clock data SUB_T, and further includes clock data BCD_T or clock data BIN_T.

Specifically, the host device 6 transmits an access signal requesting the real-time clock circuit 3 to read the clock data SUB_T and the clock data BCD_T or the clock data BIN_T at a predetermined timing when the voltage level of the reference signal REF changes. do. For example, the predetermined timing at which the voltage level of the reference signal REF transitions may be the timing at which the reference signal REF transitions from a low level to a high level, or the timing at which the reference signal REF transitions from a high level to a low level. There may be. The interface circuit 90 of the real-time clock circuit 3 receives the access signal, generates a read request signal (not shown) requesting reading of the time measurement data to be read, and outputs it to the read buffer 70. Then, the interface circuit 90 acquires read data RDAT, which is the time measurement data to be read acquired and held by the read buffer 70, converts the read data RDAT into a serial data signal SDA, and sends the serial data signal SDA to the host device 6 via the terminal P7. The host device 6 acquires the clock data.

Thereafter, when a predetermined timing at which the voltage level of the reference signal REF changes occurs n times, the host device 6 sends an access signal requesting the real-time clock circuit 3 to read the clock data SUB_T and the clock data BCD_T or the clock data BIN_T. Send again and obtain the relevant time measurement data. The integer n is the value of the correction period setting data PN described above. Then, the host device 6 calculates the amount of change in the clock data SUB_T at intervals of n cycles of the reference signal REF based on the difference between the clock data SUB_T included in the two acquired clock data, and generates correction data TD. . In this way, the correction data TD is data generated based on the amount of change in the clock data SUB_T at intervals synchronized with the reference signal REF.

Using the correction data TD stored in the storage unit 100, the logic circuit 50 performs slowing/fastening processing on the first frequency dividing circuit 20 during the correction period, similarly to the first embodiment.

Furthermore, if the amount of change in the time measurement data SUB_T at intervals of n cycles of the reference signal REF is larger than a predetermined value, the host device 6 writes the current time data to the write buffer 60 of the real-time clock circuit 3, and writes the current time data to the write buffer 60 of the real-time clock circuit 3, The clock data BCD_T and BIN_T of 40 are updated.

The rest of the configuration of the real-time clock module 1 of the third embodiment is the same as that of the first embodiment, so its construction will be omitted. Note that the real-time clock circuit 3 does not need to have a time stamp function and an interrupt generation function, so it does not need to include the terminal P5, the event time register 80, and the interrupt generation circuit 110.

FIG. 14 is a diagram showing an example of a procedure of a correction method for the real-time clock circuit 3 according to the third embodiment.

As shown in FIG. 14, first, when the voltage level of the reference signal REF transitions from, for example, a low level to a high level (Y in step S201), the host device 6 reads time measurement data from the real-time clock circuit 3 (step S202). The clock data read in step S202 includes clock data SUB_T, and further includes clock data BCD_T or clock data BIN_T.

Next, when the voltage level of the reference signal REF changes, for example, from a low level to a high level n times (Y in step S203), the host device 6 reads time measurement data from the real-time clock circuit 3 (step S204). The clock data read in step S204 includes clock data SUB_T, and further includes clock data BCD_T or clock data BIN_T. The integer n is the value of the correction period setting data PN described above. For example, if n is 32 and the period of the reference signal REF is 1 second, when the real-time clock circuit 3 receives the reference signal REF 32 times, that is, after the voltage level of the reference signal REF changes in step S201. After 32 seconds have elapsed, the clock data is read out again.

Next, the host device 6 calculates the difference ΔT between the clock data read in step S204 and the clock data read in step S202 (step S205). For example, if n is 32 and the period of the reference signal REF is 1 second, the difference ΔT corresponds to the amount of increase in the time measurement data for 32 seconds.

If the error of the difference ΔT with respect to the expected value is within 1 second (Y in step S206), the host device 6 generates the correction data TD based on the variation ΔSubCnt of less than 1 second, and the generated correction data TD is written into the storage unit 100 of the real-time clock circuit 3 (step S207). The amount of change ΔSubCnt is the difference between the clock data SUB_T read in step S204 and the clock data SUB_T read in step S202. For example, if n is 32 and the period of the reference signal REF is 1 second, the expected value of the difference ΔT is 32 seconds, so step S207 is performed when the difference ΔT is between 31 seconds and 33 seconds. . Further, in step S207, the host device 6 calculates the value of the correction data TD by 200h-ΔSubCnt on the premise that the amount of change ΔSubCnt is a value in the range of −255 to +255.

Next, the real-time clock circuit 3 uses the correction data TD written in the storage unit 100 in step S207 to perform speed-up processing on the first frequency dividing circuit 20 (step S208). Thereafter, the real-time clock circuit 3 uses the correction data TD in each correction period to perform slow and fast processing in a temporally distributed manner until the correction data TD is updated.

On the other hand, if the difference ΔT is larger than 1 second (N in step S206), the host device 6 writes the current time data to the write buffer 60 of the real-time clock circuit 3 (step S209). For example, the host device 6 writes time data of the year, month, day, hour, minute, and second, and time data representing the year, month, day, hour, minute, and second in seconds to the write buffer 60.

Next, the real-time clock circuit 3 updates the clock data BCD_T, BIN_T of the clock circuit 40 to the current time data held by the write buffer 60 (step S210).

After step S208 or step S210, steps S201 to S210 are repeatedly performed every time a predetermined interval time elapses (Y in step S211).

As described above, in the third embodiment, the host device 6 reads the clock data from the real-time clock circuit 3 to generate correction data TD, and stores the generated correction data TD in the storage section 100 of the real-time clock circuit 3. Write. Therefore, according to the third embodiment, there is no need for the real-time clock circuit 3 to generate the correction data TD, so that the size of the real-time clock circuit 3 can be reduced.

Further, in the third embodiment, since the real-time clock circuit 3 does not need to hold time measurement data at each predetermined timing when the voltage level of the reference signal REF changes, the size of the real-time clock circuit 3 can be reduced, or The processing load on the real-time clock circuit 3 can be reduced.

In addition, the real-time clock module 1 of the third embodiment has the same effects as the real-time clock module 1 of the first embodiment, as appropriate.

1-4. Modifications In each of the above embodiments, when the second frequency dividing circuit 30 operates as a binary counter, the interval at which the correction data TD is generated and the length of the correction period are equal to the length of one period of the 1Hz reference signal REF. For example, if the second frequency dividing circuit 30 operates as a BCD counter, the interval at which the correction data TD is generated and the length of the correction period are 1.25 Hz. Although we have given an example of 25.6 seconds, which is 32 times the length of one period of the reference signal REF, the interval at which the correction data TD is generated, the length of the correction period, and the period of the reference signal REF are limited to this. I can't do it. For example, one period of the reference signal REF may be made to coincide with 32 seconds or 25.6 seconds, which is the interval at which the correction data TD is generated and the length of the correction period.

Furthermore, in each of the above embodiments, when the second frequency dividing circuit 30 operates as a BCD counter, the length of one period of the 1.25 Hz reference signal REF is 0.8 seconds, and the length of one period of the 1 PPS signal is 0.8 seconds. Although the length of one cycle of the reference signal REF is not an integral multiple of 1 second, the length of one cycle of the reference signal REF may be an integral multiple of 1 second. For example, assuming that the length of one cycle of the reference signal REF is 256 seconds, the difference between two pieces of time measurement data SUB_T acquired at an interval of one cycle of the reference signal REF is 1/10 and the sign is inverted, and the correction data TD is It may be the value of Alternatively, if the length of one cycle of the reference signal REF is 1 second, that is, a signal of 1 PPS is used as the reference signal REF, and the difference between two time measurement data SUB_T acquired at an interval of 256 cycles of the reference signal REF is 1/10. The value obtained by inverting the sign may be used as the value of the correction data TD.

Further, in each of the above embodiments, an example has been given in which the first frequency dividing circuit 20, the second frequency dividing circuit 30, and the clock circuit 40 are asynchronous ripple circuits, but the first frequency dividing circuit 20, the second frequency dividing circuit 30 and the clock circuit 40 may be synchronous counter circuits. For example, the first frequency dividing circuit 20 may be a counter circuit that operates in synchronization with the first clock signal CK1, and the second frequency dividing circuit 20 may be a counter circuit that operates in synchronization with the second clock signal CK2. Alternatively, the clock circuit 40 may be a counter circuit that operates in synchronization with the second clock signal CK2 or the third clock signal CK3.

2. Electronic Device FIG. 15 is a functional block diagram showing an example of the configuration of an electronic device using the real-time clock module 1 or the real-time clock circuit 3 of each embodiment described above. Further, FIG. 16 is a diagram showing an example of the appearance of a smartphone, which is an example of the electronic device of this embodiment.

The electronic device 300 of this embodiment includes a real-time clock module 1, a host device 320, an operation section 330, a storage section 340, a communication section 350, a display section 360, and a sound output section 370. Note that the electronic device 300 of this embodiment may have a configuration in which some of the components shown in FIG. 15 are omitted or changed, or other components are added.

As mentioned above, the real-time clock module 1 includes the vibrator 2 and the real-time clock circuit 3.

The host device 320 performs various calculation processes and control processes according to programs stored in the storage unit 340 and the like. Specifically, the host device 320 performs various processes according to operation signals from the operation unit 330, processes that control the communication unit 350 to perform data communication with other devices, and displays various information on the display unit 360. It performs a process of transmitting a display signal for display, a process of transmitting a sound signal for outputting various sounds from the sound output unit 370, and the like.

The host device 320 also communicates with the real-time clock circuit 3. For example, the host device 320 reads time data and the like from the real-time clock circuit 3 and performs various calculation processes and control processes. In addition, the host device 320 rewrites time measurement data in the real-time clock circuit 3. Further, the host device 320 may transmit various data including the above-mentioned correction data TD and the reference signal REF to the real-time clock circuit 3. The host device 320 is realized by, for example, an MCU (Micro Controller Unit) or an MPU (Micro Processor Unit). Note that the host device 320 corresponds to the host device 6 described above.

The operation unit 330 is an input device including operation keys, button switches, and the like, and outputs an operation signal to the host device 320 in accordance with a user's operation. For example, the host device 320 can set time information in the real-time clock circuit 3 according to a signal input from the operation unit 330.

The storage unit 340 stores programs, data, etc. for the host device 320 to perform various calculation processes and control processes. The storage unit 340 is also used as a work area for the host device 320, and includes programs and data read from the storage unit 340, data input from the operation unit 330, calculation results executed by the host device 320 according to various programs, etc. temporarily memorize. The storage unit 340 includes a ROM (Read Only Memory) and a RAM (Random Access Memory), and is configured by, for example, a hard disk, a flexible disk, an MO, an MT, various types of memories, a CD-ROM, a DVD-ROM, etc. Realized.

The communication unit 350 performs various controls for establishing data communication between the host device 320 and an external device.

The display unit 360 is a display device configured with an LCD (Liquid Crystal Display) or the like, and displays various information based on display signals input from the host device 320. The display section 360 may be provided with a touch panel that functions as the operation section 330.

The sound output unit 370 is configured with a speaker or the like, and outputs various information as sound or audio based on the sound signal input from the host device 320.

Since the electronic device 300 of this embodiment includes the real-time clock circuit 3 that can easily acquire correction data for time measurement data in a short time, it can achieve high reliability.

Various electronic devices can be considered as the electronic device 300, such as an electronic watch, a personal computer such as a mobile type, a laptop type, or a tablet type, a mobile terminal such as a smartphone or a mobile phone, a digital camera, an inkjet printer, etc. Inkjet ejection devices such as routers and switches, storage area network devices such as routers and switches, local area network devices, mobile terminal base station devices, televisions, video cameras, video recorders, car navigation devices, real-time clock devices, pagers, electronic notebooks , electronic dictionaries, calculators, electronic game devices, game controllers, word processors, workstations, videophones, security TV monitors, electronic binoculars, PO
Medical devices such as S terminals, electronic thermometers, blood pressure monitors, blood sugar meters, electrocardiogram measuring devices, ultrasound diagnostic devices, electronic endoscopes, fish finders, various measuring devices, instruments for vehicles, aircraft, ships, etc., flight simulators , head-mounted displays, motion tracing, motion tracking, motion controllers, pedestrian dead reckoning (PDR) devices, etc.

The present invention is not limited to this embodiment, and various modifications can be made within the scope of the gist of the present invention.

The above-described embodiments and modifications are merely examples, and the present invention is not limited thereto. For example, it is also possible to combine each embodiment and each modification as appropriate.

The present invention includes configurations that are substantially the same as those described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objectives and effects). Further, the present invention includes a configuration in which non-essential parts of the configuration described in the embodiments are replaced. Further, the present invention includes a configuration that has the same effects or a configuration that can achieve the same objective as the configuration described in the embodiment. Further, the present invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

The following content is derived from the above-described embodiment and modification.

One aspect of the real-time clock circuit is
an oscillation circuit that generates a first clock signal by oscillating a vibrator;
a first frequency dividing circuit that divides the first clock signal to generate a second clock signal;
a second frequency dividing circuit that frequency divides the second clock signal to generate a third clock signal, and generates first time measurement data for a time shorter than one second based on the second clock signal;
a timekeeping circuit that generates second timekeeping data for a time of one second or more based on the third clock signal;
Using correction data generated based on the amount of change in the first time measurement data at intervals synchronized with the reference signal, the first frequency dividing circuit is subjected to slow and fast processing during a period of length corresponding to the intervals. and a logic circuit that performs.

In this real-time clock circuit, the logic circuit generates the second clock signal using correction data generated based on the amount of change in the first clock data for a time shorter than one second at intervals synchronized with the reference signal. A slow/fast process is performed on the first frequency dividing circuit. Therefore, the second clock signal is corrected using correction data generated in an arbitrary short time period of one second or more. Then, the second frequency dividing circuit divides the frequency of the second clock signal to generate a third clock signal, and the time measurement circuit generates second time measurement data for a time of one second or more based on the third clock signal. The second time measurement data is corrected in a short time. Further, in this real-time clock circuit, correction data is generated based on the amount of change in the first time measurement data at intervals synchronized with the reference signal. Therefore, there is no need for the real-time clock circuit to output the third clock signal to the external device and for the external device to measure the frequency of the third clock signal and create correction data. Therefore, according to this real-time clock circuit, correction data for time measurement data can be easily obtained in a short time. Furthermore, in this real-time clock circuit, the length of the period in which the adjustment data is performed using the correction data matches the interval at which the amount of change in the first clock data is calculated to generate the correction data. A value obtained by inverting the sign of the amount of change in the time measurement data can be used as the value of the correction data. Therefore, according to this real-time clock circuit, it is easy to generate correction data. As described above, this real-time clock circuit can realize excellent user convenience.

In one aspect of the real-time clock circuit,
The interval is longer than the period of the third clock signal,
The logic circuit may perform the adjustment/acceleration processing at time intervals longer than a cycle of the second clock signal during the period.

According to this real-time clock circuit, the interval at which the amount of change in the first time measurement data is calculated to generate the correction data is one second or more, and the period of the third clock signal used by the time measurement circuit that generates the second time measurement data. , the logic circuit can correct the second clock signal with high resolution. Furthermore, according to this real-time clock circuit, the logic circuit performs slowing/fastening processing on the first frequency dividing circuit in a temporally distributed manner at time intervals longer than the period of the second clock signal. It is possible to reduce the variation in the amount of frequency fluctuation.

One aspect of the real-time clock circuit is:
The device may include a buffer circuit that holds the first time measurement data at a predetermined timing when the voltage level of the reference signal changes.

In this real-time clock circuit, the correction data is generated based on the first clock data held in the buffer circuit at a predetermined timing when the voltage level of the reference signal changes. Therefore, according to this real-time clock circuit, for example, when an external device reads the first clock data held in the buffer circuit and generates correction data, there is variation in the delay time required to read the first clock data. However, since no error occurs in the first clock data due to variations in delay time, the clock data can be corrected with high accuracy.

One aspect of the real-time clock circuit is:
The device may include a correction data generation circuit that generates the correction data based on the held first time measurement data.

In this real-time clock circuit, the correction data generation circuit generates correction data based on the first clock data held in the buffer circuit at a predetermined timing when the voltage level of the reference signal changes. Therefore, according to this real-time clock circuit, there is no need for the external device to generate correction data, so that the calculation load on the external device can be reduced. Furthermore, according to this real-time clock, there is no need for an external device to read out the first time measurement data, so errors in the first time measurement data due to variations in the delay time required for reading do not occur, so the time measurement data can be corrected with high precision. be able to.

One aspect of the real-time clock circuit is:
The device may also include an interface circuit that transmits the first time measurement data.

According to this real-time clock circuit, the external device can receive the first time measurement data transmitted by the interface circuit and generate correction data. Therefore, since the real-time clock circuit does not need to generate correction data, the size of the real-time clock circuit can be reduced.

In one aspect of the real-time clock circuit,
The interface circuit may receive information specifying the interval.

According to this real-time clock circuit, the interval at which the amount of change in the first time measurement data is calculated to generate the correction data, that is, the length of the period in which the adjustment data is performed using the correction data, is determined as the accuracy of the correction. The user can set it arbitrarily, taking into consideration the trade-off with the time required for correction.

One aspect of the real-time clock module is
One aspect of the real-time clock circuit,
and the vibrator.

One aspect of electronic equipment is
One aspect of the real-time clock circuit,
a host device communicating with the real-time clock circuit.

One aspect of the correction method for the real-time clock circuit is
an oscillation circuit that oscillates a vibrator to generate a first clock signal; a first frequency divider circuit that divides the frequency of the first clock signal to generate a second clock signal; and a first frequency divider circuit that divides the frequency of the second clock signal. a second frequency dividing circuit that generates a third clock signal based on the second clock signal, and generates first time measurement data for a time shorter than one second based on the third clock signal; A method for correcting a real-time clock circuit, comprising: a clock circuit that generates second clock data for a time of
The real-time clock circuit performs the first frequency division in a period corresponding to the interval using correction data generated based on the amount of change in the first clock data at intervals synchronized with the reference signal. It includes a step of performing slow and fast processing on the circuit.

In this correction method for a real-time clock circuit, the real-time clock circuit uses correction data generated based on the amount of change in first clock data at intervals shorter than one second at intervals synchronized with a reference signal to Slow and fast processing is performed on the first frequency dividing circuit that generates the clock signal. Therefore, the second clock signal is corrected using correction data generated in an arbitrary short time period of one second or more. Then, the second frequency dividing circuit divides the frequency of the second clock signal to generate a third clock signal, and the time measurement circuit generates second time measurement data for a time of one second or more based on the third clock signal. The second time measurement data is corrected in a short time. Further, in this real-time clock circuit correction method, correction data is generated based on the amount of change in the first time measurement data at intervals synchronized with the reference signal. Therefore, there is no need for the real-time clock circuit to output the third clock signal to the external device and for the external device to measure the frequency of the third clock signal and create correction data. Therefore, according to this real-time clock circuit correction method, correction data for time measurement data can be easily obtained in a short time. Furthermore, in this method of correcting the real-time clock circuit, the length of the period during which the adjustment process using the correction data is performed matches the interval at which the amount of change in the first clock data is calculated to generate the correction data. , a value obtained by inverting the sign of the amount of change in the first time measurement data can be used as the value of the correction data. Therefore, according to this real-time clock circuit correction method, it is easy to generate correction data. As described above, according to this real-time clock circuit correction method, excellent user convenience can be achieved.

One aspect of the method for correcting the real-time clock circuit is
a host device transmitting the reference signal to the real-time clock circuit;
a step in which the real-time clock circuit holds the first time measurement data at each predetermined timing when the voltage level of the reference signal changes;
the real-time clock circuit transmitting an interrupt signal to the host device;
the host device receiving the interrupt signal and reading the two pieces of first time measurement data held at the interval;
The method may include a step in which the host device generates the correction data based on the two read first clock data, and writes the generated correction data into a storage section of the real-time clock circuit.

In this real-time clock circuit correction method, a host device reads first time measurement data from a real-time clock circuit, generates correction data, and writes the generated correction data into a storage section of the real-time clock circuit. Therefore, according to this real-time clock circuit correction method, there is no need for the real-time clock circuit to generate correction data, so that the size of the real-time clock circuit can be reduced. Further, in this real-time clock circuit correction method, the host device generates correction data based on first time measurement data held by the real-time clock circuit at a predetermined timing when the voltage level of the reference signal changes. Therefore, according to this method of correcting the real-time clock circuit, even if there is variation in the delay time required for the host device to read the first time measurement data, an error in the first time measurement data due to the variation in delay time does not occur, resulting in a high Timing data can be corrected with precision.

One aspect of the method for correcting the real-time clock circuit is
a host device transmitting the reference signal to the real-time clock circuit;
a step in which the real-time clock circuit holds the first time measurement data at each predetermined timing when the voltage level of the reference signal changes;
The real-time clock circuit may include a step of generating the correction data based on the two pieces of first time measurement data held at the interval.

In this method of correcting a real-time clock circuit, the real-time clock circuit generates correction data based on the first clock data held in the buffer circuit at a predetermined timing when the voltage level of the reference signal changes. Therefore, according to this real-time clock circuit correction method, there is no need for the host device to generate correction data, so that the calculation load on the host device can be reduced. Further, in this real-time clock circuit correction method, the real-time clock circuit generates correction data based on the first time measurement data held at a predetermined timing when the voltage level of the reference signal changes. Therefore, according to this method of correcting the real-time clock circuit, there is no need for the host device to read the first time measurement data, so there is no error in the first time measurement data due to variations in the delay time required for reading, and therefore time can be measured with high accuracy. Data can be corrected.

One aspect of the method for correcting the real-time clock circuit is
a host device reading two pieces of the first time measurement data from the real-time clock circuit at the intervals;
The method may include a step in which the host device generates the correction data based on the two read first clock data, and writes the generated correction data into a storage section of the real-time clock circuit.

In this real-time clock circuit correction method, a host device reads first time measurement data from a real-time clock circuit, generates correction data, and writes the generated correction data into a storage section of the real-time clock circuit. Therefore, according to this real-time clock circuit correction method, there is no need for the real-time clock circuit to generate correction data, so that the size of the real-time clock circuit can be reduced. In addition, in this real-time clock circuit correction method, the real-time clock circuit does not need to hold the first time measurement data at each predetermined timing when the voltage level of the reference signal changes, so the size of the real-time clock circuit can be reduced. Alternatively, the processing load on the real-time clock circuit can be reduced.

1... Real-time clock module, 2... Oscillator, 3... Real-time clock circuit, 4
... Main power supply, 5... Backup power supply, 6... Host device, 10... Oscillator circuit, 20... First frequency dividing circuit, 21... Frequency dividing circuit, 22 to 25... 2 frequency dividing circuit, 30... Second frequency dividing circuit, 31 to 3A...2 frequency divider circuit, 3B, 3C, 3D... Counter, 40... Time measurement circuit, 41 to 47... Counter, 50... Logic circuit, 60... Write buffer, 70... Read buffer, 80... Event time register, 90 ...Interface circuit, 100...Storage unit, 110...Interrupt generation circuit, 120...Power supply voltage selection circuit, 130...Power supply voltage determination circuit, 140...Regulator, 150...Correction data generation circuit, 300...Electronic equipment, 320...Host device , 330...Operation unit, 340...Storage unit, 350...Communication unit, 360...Display unit, 370...Sound output unit

Claims (12)

an oscillation circuit that generates a first clock signal by oscillating a vibrator;
a first frequency divider circuit that divides the first clock signal to generate a second clock signal;
a second frequency dividing circuit that frequency divides the second clock signal to generate a third clock signal, and generates first time measurement data for a time shorter than one second based on the second clock signal;
a timekeeping circuit that generates second timekeeping data for a time of one second or more based on the third clock signal;
Using correction data generated based on the amount of change in the first time measurement data at intervals synchronized with the reference signal, the first frequency dividing circuit is subjected to slow and fast processing during a period of length corresponding to the intervals. A real-time clock circuit comprising: a logic circuit for performing The interval is longer than the period of the third clock signal,
2. The real-time clock circuit according to claim 1, wherein the logic circuit performs the slow/fast processing at time intervals longer than a cycle of the second clock signal during the period. 3. The real-time clock circuit according to claim 1, further comprising a buffer circuit that holds the first time measurement data at a predetermined timing when the voltage level of the reference signal changes. The real-time clock circuit according to claim 3, further comprising a correction data generation circuit that generates the correction data based on the held first time measurement data. The real-time clock circuit according to any one of claims 1 to 4, comprising an interface circuit that transmits the first time measurement data. 6. The real-time clock circuit of claim 5, wherein the interface circuit receives information specifying the interval. A real-time clock circuit according to any one of claims 1 to 6,
A real-time clock module comprising the vibrator. A real-time clock circuit according to any one of claims 1 to 6,
An electronic device, comprising: a host device communicating with the real-time clock circuit. an oscillation circuit that oscillates a vibrator to generate a first clock signal; a first frequency divider circuit that divides the frequency of the first clock signal to generate a second clock signal; and a first frequency divider circuit that divides the frequency of the second clock signal. a second frequency dividing circuit that generates a third clock signal based on the second clock signal, and generates first time measurement data for a time shorter than one second based on the third clock signal; A method for correcting a real-time clock circuit, comprising: a clock circuit that generates second clock data for a time of
The real-time clock circuit performs the first frequency division in a period corresponding to the interval using correction data generated based on the amount of change in the first clock data at intervals synchronized with the reference signal. A method for correcting a real-time clock circuit, which includes a step of performing slow and fast processing on the circuit. a host device transmitting the reference signal to the real-time clock circuit;
a step in which the real-time clock circuit holds the first time measurement data at each predetermined timing when the voltage level of the reference signal changes;
the real-time clock circuit transmitting an interrupt signal to the host device;
the host device receiving the interrupt signal and reading the two pieces of first time measurement data held at the interval;
The host device generates the correction data based on the two pieces of read first time measurement data, and writes the generated correction data into a storage section of the real-time clock circuit. How to correct real-time clock circuit. a host device transmitting the reference signal to the real-time clock circuit;
a step in which the real-time clock circuit holds the first time measurement data at each predetermined timing when the voltage level of the reference signal changes;
10. The method for correcting a real-time clock circuit according to claim 9, comprising the step of: generating the correction data based on the two pieces of first time measurement data held at the interval. a host device reading two pieces of the first time measurement data from the real-time clock circuit at the intervals;
The host device generates the correction data based on the two pieces of read first time measurement data, and writes the generated correction data into a storage section of the real-time clock circuit. How to correct real-time clock circuit.

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